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399 lines
9.9 KiB
399 lines
9.9 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2018, 2019 Cisco Systems |
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*/ |
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#include <linux/edac.h> |
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/platform_device.h> |
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#include <linux/stop_machine.h> |
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#include <linux/io.h> |
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#include <linux/of_address.h> |
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#include <linux/regmap.h> |
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#include "edac_module.h" |
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#define DRV_NAME "aspeed-edac" |
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#define ASPEED_MCR_PROT 0x00 /* protection key register */ |
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#define ASPEED_MCR_CONF 0x04 /* configuration register */ |
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#define ASPEED_MCR_INTR_CTRL 0x50 /* interrupt control/status register */ |
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#define ASPEED_MCR_ADDR_UNREC 0x58 /* address of first un-recoverable error */ |
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#define ASPEED_MCR_ADDR_REC 0x5c /* address of last recoverable error */ |
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#define ASPEED_MCR_LAST ASPEED_MCR_ADDR_REC |
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#define ASPEED_MCR_PROT_PASSWD 0xfc600309 |
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#define ASPEED_MCR_CONF_DRAM_TYPE BIT(4) |
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#define ASPEED_MCR_CONF_ECC BIT(7) |
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#define ASPEED_MCR_INTR_CTRL_CLEAR BIT(31) |
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#define ASPEED_MCR_INTR_CTRL_CNT_REC GENMASK(23, 16) |
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#define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12) |
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#define ASPEED_MCR_INTR_CTRL_ENABLE (BIT(0) | BIT(1)) |
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static struct regmap *aspeed_regmap; |
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static int regmap_reg_write(void *context, unsigned int reg, unsigned int val) |
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{ |
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void __iomem *regs = (void __iomem *)context; |
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/* enable write to MCR register set */ |
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writel(ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT); |
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writel(val, regs + reg); |
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/* disable write to MCR register set */ |
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writel(~ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT); |
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return 0; |
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} |
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static int regmap_reg_read(void *context, unsigned int reg, unsigned int *val) |
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{ |
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void __iomem *regs = (void __iomem *)context; |
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*val = readl(regs + reg); |
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return 0; |
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} |
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static bool regmap_is_volatile(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case ASPEED_MCR_PROT: |
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case ASPEED_MCR_INTR_CTRL: |
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case ASPEED_MCR_ADDR_UNREC: |
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case ASPEED_MCR_ADDR_REC: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static const struct regmap_config aspeed_regmap_config = { |
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.reg_bits = 32, |
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.val_bits = 32, |
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.reg_stride = 4, |
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.max_register = ASPEED_MCR_LAST, |
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.reg_write = regmap_reg_write, |
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.reg_read = regmap_reg_read, |
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.volatile_reg = regmap_is_volatile, |
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.fast_io = true, |
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}; |
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static void count_rec(struct mem_ctl_info *mci, u8 rec_cnt, u32 rec_addr) |
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{ |
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struct csrow_info *csrow = mci->csrows[0]; |
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u32 page, offset, syndrome; |
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if (!rec_cnt) |
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return; |
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/* report first few errors (if there are) */ |
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/* note: no addresses are recorded */ |
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if (rec_cnt > 1) { |
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/* page, offset and syndrome are not available */ |
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page = 0; |
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offset = 0; |
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syndrome = 0; |
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, rec_cnt-1, |
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page, offset, syndrome, 0, 0, -1, |
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"address(es) not available", ""); |
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} |
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/* report last error */ |
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/* note: rec_addr is the last recoverable error addr */ |
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page = rec_addr >> PAGE_SHIFT; |
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offset = rec_addr & ~PAGE_MASK; |
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/* syndrome is not available */ |
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syndrome = 0; |
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, |
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csrow->first_page + page, offset, syndrome, |
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0, 0, -1, "", ""); |
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} |
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static void count_un_rec(struct mem_ctl_info *mci, u8 un_rec_cnt, |
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u32 un_rec_addr) |
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{ |
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struct csrow_info *csrow = mci->csrows[0]; |
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u32 page, offset, syndrome; |
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if (!un_rec_cnt) |
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return; |
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/* report 1. error */ |
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/* note: un_rec_addr is the first unrecoverable error addr */ |
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page = un_rec_addr >> PAGE_SHIFT; |
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offset = un_rec_addr & ~PAGE_MASK; |
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/* syndrome is not available */ |
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syndrome = 0; |
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
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csrow->first_page + page, offset, syndrome, |
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0, 0, -1, "", ""); |
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/* report further errors (if there are) */ |
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/* note: no addresses are recorded */ |
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if (un_rec_cnt > 1) { |
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/* page, offset and syndrome are not available */ |
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page = 0; |
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offset = 0; |
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syndrome = 0; |
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, un_rec_cnt-1, |
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page, offset, syndrome, 0, 0, -1, |
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"address(es) not available", ""); |
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} |
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} |
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static irqreturn_t mcr_isr(int irq, void *arg) |
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{ |
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struct mem_ctl_info *mci = arg; |
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u32 rec_addr, un_rec_addr; |
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u32 reg50, reg5c, reg58; |
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u8 rec_cnt, un_rec_cnt; |
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regmap_read(aspeed_regmap, ASPEED_MCR_INTR_CTRL, ®50); |
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dev_dbg(mci->pdev, "received edac interrupt w/ mcr register 50: 0x%x\n", |
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reg50); |
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/* collect data about recoverable and unrecoverable errors */ |
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rec_cnt = (reg50 & ASPEED_MCR_INTR_CTRL_CNT_REC) >> 16; |
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un_rec_cnt = (reg50 & ASPEED_MCR_INTR_CTRL_CNT_UNREC) >> 12; |
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dev_dbg(mci->pdev, "%d recoverable interrupts and %d unrecoverable interrupts\n", |
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rec_cnt, un_rec_cnt); |
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regmap_read(aspeed_regmap, ASPEED_MCR_ADDR_UNREC, ®58); |
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un_rec_addr = reg58; |
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regmap_read(aspeed_regmap, ASPEED_MCR_ADDR_REC, ®5c); |
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rec_addr = reg5c; |
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/* clear interrupt flags and error counters: */ |
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regmap_update_bits(aspeed_regmap, ASPEED_MCR_INTR_CTRL, |
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ASPEED_MCR_INTR_CTRL_CLEAR, |
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ASPEED_MCR_INTR_CTRL_CLEAR); |
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regmap_update_bits(aspeed_regmap, ASPEED_MCR_INTR_CTRL, |
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ASPEED_MCR_INTR_CTRL_CLEAR, 0); |
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/* process recoverable and unrecoverable errors */ |
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count_rec(mci, rec_cnt, rec_addr); |
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count_un_rec(mci, un_rec_cnt, un_rec_addr); |
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if (!rec_cnt && !un_rec_cnt) |
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dev_dbg(mci->pdev, "received edac interrupt, but did not find any ECC counters\n"); |
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regmap_read(aspeed_regmap, ASPEED_MCR_INTR_CTRL, ®50); |
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dev_dbg(mci->pdev, "edac interrupt handled. mcr reg 50 is now: 0x%x\n", |
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reg50); |
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return IRQ_HANDLED; |
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} |
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static int config_irq(void *ctx, struct platform_device *pdev) |
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{ |
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int irq; |
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int rc; |
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/* register interrupt handler */ |
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irq = platform_get_irq(pdev, 0); |
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dev_dbg(&pdev->dev, "got irq %d\n", irq); |
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if (irq < 0) |
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return irq; |
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rc = devm_request_irq(&pdev->dev, irq, mcr_isr, IRQF_TRIGGER_HIGH, |
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DRV_NAME, ctx); |
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if (rc) { |
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dev_err(&pdev->dev, "unable to request irq %d\n", irq); |
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return rc; |
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} |
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/* enable interrupts */ |
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regmap_update_bits(aspeed_regmap, ASPEED_MCR_INTR_CTRL, |
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ASPEED_MCR_INTR_CTRL_ENABLE, |
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ASPEED_MCR_INTR_CTRL_ENABLE); |
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return 0; |
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} |
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static int init_csrows(struct mem_ctl_info *mci) |
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{ |
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struct csrow_info *csrow = mci->csrows[0]; |
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u32 nr_pages, dram_type; |
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struct dimm_info *dimm; |
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struct device_node *np; |
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struct resource r; |
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u32 reg04; |
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int rc; |
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/* retrieve info about physical memory from device tree */ |
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np = of_find_node_by_name(NULL, "memory"); |
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if (!np) { |
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dev_err(mci->pdev, "dt: missing /memory node\n"); |
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return -ENODEV; |
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} |
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rc = of_address_to_resource(np, 0, &r); |
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of_node_put(np); |
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if (rc) { |
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dev_err(mci->pdev, "dt: failed requesting resource for /memory node\n"); |
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return rc; |
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} |
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dev_dbg(mci->pdev, "dt: /memory node resources: first page r.start=0x%x, resource_size=0x%x, PAGE_SHIFT macro=0x%x\n", |
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r.start, resource_size(&r), PAGE_SHIFT); |
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csrow->first_page = r.start >> PAGE_SHIFT; |
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nr_pages = resource_size(&r) >> PAGE_SHIFT; |
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csrow->last_page = csrow->first_page + nr_pages - 1; |
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regmap_read(aspeed_regmap, ASPEED_MCR_CONF, ®04); |
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dram_type = (reg04 & ASPEED_MCR_CONF_DRAM_TYPE) ? MEM_DDR4 : MEM_DDR3; |
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dimm = csrow->channels[0]->dimm; |
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dimm->mtype = dram_type; |
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dimm->edac_mode = EDAC_SECDED; |
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dimm->nr_pages = nr_pages / csrow->nr_channels; |
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dev_dbg(mci->pdev, "initialized dimm with first_page=0x%lx and nr_pages=0x%x\n", |
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csrow->first_page, nr_pages); |
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return 0; |
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} |
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static int aspeed_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct edac_mc_layer layers[2]; |
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struct mem_ctl_info *mci; |
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void __iomem *regs; |
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u32 reg04; |
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int rc; |
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regs = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(regs)) |
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return PTR_ERR(regs); |
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aspeed_regmap = devm_regmap_init(dev, NULL, (__force void *)regs, |
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&aspeed_regmap_config); |
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if (IS_ERR(aspeed_regmap)) |
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return PTR_ERR(aspeed_regmap); |
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/* bail out if ECC mode is not configured */ |
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regmap_read(aspeed_regmap, ASPEED_MCR_CONF, ®04); |
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if (!(reg04 & ASPEED_MCR_CONF_ECC)) { |
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dev_err(&pdev->dev, "ECC mode is not configured in u-boot\n"); |
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return -EPERM; |
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} |
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edac_op_state = EDAC_OPSTATE_INT; |
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/* allocate & init EDAC MC data structure */ |
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
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layers[0].size = 1; |
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layers[0].is_virt_csrow = true; |
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layers[1].type = EDAC_MC_LAYER_CHANNEL; |
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layers[1].size = 1; |
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layers[1].is_virt_csrow = false; |
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); |
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if (!mci) |
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return -ENOMEM; |
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mci->pdev = &pdev->dev; |
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mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR4; |
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mci->edac_ctl_cap = EDAC_FLAG_SECDED; |
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mci->edac_cap = EDAC_FLAG_SECDED; |
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mci->scrub_cap = SCRUB_FLAG_HW_SRC; |
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mci->scrub_mode = SCRUB_HW_SRC; |
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mci->mod_name = DRV_NAME; |
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mci->ctl_name = "MIC"; |
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mci->dev_name = dev_name(&pdev->dev); |
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rc = init_csrows(mci); |
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if (rc) { |
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dev_err(&pdev->dev, "failed to init csrows\n"); |
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goto probe_exit02; |
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} |
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platform_set_drvdata(pdev, mci); |
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/* register with edac core */ |
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rc = edac_mc_add_mc(mci); |
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if (rc) { |
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dev_err(&pdev->dev, "failed to register with EDAC core\n"); |
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goto probe_exit02; |
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} |
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/* register interrupt handler and enable interrupts */ |
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rc = config_irq(mci, pdev); |
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if (rc) { |
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dev_err(&pdev->dev, "failed setting up irq\n"); |
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goto probe_exit01; |
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} |
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return 0; |
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probe_exit01: |
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edac_mc_del_mc(&pdev->dev); |
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probe_exit02: |
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edac_mc_free(mci); |
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return rc; |
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} |
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static int aspeed_remove(struct platform_device *pdev) |
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{ |
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struct mem_ctl_info *mci; |
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/* disable interrupts */ |
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regmap_update_bits(aspeed_regmap, ASPEED_MCR_INTR_CTRL, |
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ASPEED_MCR_INTR_CTRL_ENABLE, 0); |
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/* free resources */ |
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mci = edac_mc_del_mc(&pdev->dev); |
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if (mci) |
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edac_mc_free(mci); |
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return 0; |
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} |
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static const struct of_device_id aspeed_of_match[] = { |
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{ .compatible = "aspeed,ast2400-sdram-edac" }, |
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{ .compatible = "aspeed,ast2500-sdram-edac" }, |
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{ .compatible = "aspeed,ast2600-sdram-edac" }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, aspeed_of_match); |
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static struct platform_driver aspeed_driver = { |
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.driver = { |
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.name = DRV_NAME, |
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.of_match_table = aspeed_of_match |
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}, |
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.probe = aspeed_probe, |
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.remove = aspeed_remove |
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}; |
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module_platform_driver(aspeed_driver); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Stefan Schaeckeler <[email protected]>"); |
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MODULE_DESCRIPTION("Aspeed BMC SoC EDAC driver"); |
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MODULE_VERSION("1.0");
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