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45 lines
1.2 KiB
45 lines
1.2 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* timer.h: Definitions for the timer chips on the Sparc. |
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* |
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* Copyright (C) 1995 David S. Miller ([email protected]) |
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*/ |
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#ifndef _SPARC_TIMER_H |
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#define _SPARC_TIMER_H |
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#include <linux/clocksource.h> |
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#include <linux/irqreturn.h> |
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#include <asm-generic/percpu.h> |
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#include <asm/cpu_type.h> /* For SUN4M_NCPUS */ |
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#define SBUS_CLOCK_RATE 2000000 /* 2MHz */ |
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#define TIMER_VALUE_SHIFT 9 |
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#define TIMER_VALUE_MASK 0x3fffff |
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#define TIMER_LIMIT_BIT (1 << 31) /* Bit 31 in Counter-Timer register */ |
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/* The counter timer register has the value offset by 9 bits. |
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* From sun4m manual: |
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* When a counter reaches the value in the corresponding limit register, |
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* the Limit bit is set and the counter is set to 500 nS (i.e. 0x00000200). |
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* |
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* To compensate for this add one to the value. |
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*/ |
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static inline unsigned int timer_value(unsigned int value) |
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{ |
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return (value + 1) << TIMER_VALUE_SHIFT; |
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} |
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extern volatile u32 __iomem *master_l10_counter; |
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irqreturn_t notrace timer_interrupt(int dummy, void *dev_id); |
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#ifdef CONFIG_SMP |
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DECLARE_PER_CPU(struct clock_event_device, sparc32_clockevent); |
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void register_percpu_ce(int cpu); |
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#endif |
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#endif /* !(_SPARC_TIMER_H) */
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