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242 lines
9.5 KiB
242 lines
9.5 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _SPARC64_CHAFSR_H |
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#define _SPARC64_CHAFSR_H |
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/* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */ |
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/* Comments indicate which processor variants on which the bit definition |
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* is valid. Codes are: |
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* ch --> cheetah |
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* ch+ --> cheetah plus |
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* jp --> jalapeno |
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*/ |
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/* All bits of this register except M_SYNDROME and E_SYNDROME are |
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* read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only. |
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*/ |
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/* Software bit set by linux trap handlers to indicate that the trap was |
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* signalled at %tl >= 1. |
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*/ |
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#define CHAFSR_TL1 (1UL << 63UL) /* n/a */ |
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/* Unmapped error from system bus for prefetch queue or |
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* store queue read operation |
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*/ |
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#define CHPAFSR_DTO (1UL << 59UL) /* ch+ */ |
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/* Bus error from system bus for prefetch queue or store queue |
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* read operation |
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*/ |
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#define CHPAFSR_DBERR (1UL << 58UL) /* ch+ */ |
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/* Hardware corrected E-cache Tag ECC error */ |
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#define CHPAFSR_THCE (1UL << 57UL) /* ch+ */ |
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/* System interface protocol error, hw timeout caused */ |
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#define JPAFSR_JETO (1UL << 57UL) /* jp */ |
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/* SW handled correctable E-cache Tag ECC error */ |
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#define CHPAFSR_TSCE (1UL << 56UL) /* ch+ */ |
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/* Parity error on system snoop results */ |
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#define JPAFSR_SCE (1UL << 56UL) /* jp */ |
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/* Uncorrectable E-cache Tag ECC error */ |
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#define CHPAFSR_TUE (1UL << 55UL) /* ch+ */ |
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/* System interface protocol error, illegal command detected */ |
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#define JPAFSR_JEIC (1UL << 55UL) /* jp */ |
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/* Uncorrectable system bus data ECC error due to prefetch |
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* or store fill request |
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*/ |
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#define CHPAFSR_DUE (1UL << 54UL) /* ch+ */ |
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/* System interface protocol error, illegal ADTYPE detected */ |
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#define JPAFSR_JEIT (1UL << 54UL) /* jp */ |
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/* Multiple errors of the same type have occurred. This bit is set when |
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* an uncorrectable error or a SW correctable error occurs and the status |
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* bit to report that error is already set. When multiple errors of |
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* different types are indicated by setting multiple status bits. |
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* |
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* This bit is not set if multiple HW corrected errors with the same |
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* status bit occur, only uncorrectable and SW correctable ones have |
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* this behavior. |
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* |
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* This bit is not set when multiple ECC errors happen within a single |
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* 64-byte system bus transaction. Only the first ECC error in a 16-byte |
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* subunit will be logged. All errors in subsequent 16-byte subunits |
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* from the same 64-byte transaction are ignored. |
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*/ |
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#define CHAFSR_ME (1UL << 53UL) /* ch,ch+,jp */ |
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/* Privileged state error has occurred. This is a capture of PSTATE.PRIV |
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* at the time the error is detected. |
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*/ |
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#define CHAFSR_PRIV (1UL << 52UL) /* ch,ch+,jp */ |
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/* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error |
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* bits and record the most recently detected errors. Bits accumulate |
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* errors that have been detected since the last write to clear the bit. |
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*/ |
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/* System interface protocol error. The processor asserts its' ERROR |
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* pin when this event occurs and it also logs a specific cause code |
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* into a JTAG scannable flop. |
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*/ |
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#define CHAFSR_PERR (1UL << 51UL) /* ch,ch+,jp */ |
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/* Internal processor error. The processor asserts its' ERROR |
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* pin when this event occurs and it also logs a specific cause code |
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* into a JTAG scannable flop. |
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*/ |
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#define CHAFSR_IERR (1UL << 50UL) /* ch,ch+,jp */ |
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/* System request parity error on incoming address */ |
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#define CHAFSR_ISAP (1UL << 49UL) /* ch,ch+,jp */ |
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/* HW Corrected system bus MTAG ECC error */ |
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#define CHAFSR_EMC (1UL << 48UL) /* ch,ch+ */ |
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/* Parity error on L2 cache tag SRAM */ |
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#define JPAFSR_ETP (1UL << 48UL) /* jp */ |
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/* Uncorrectable system bus MTAG ECC error */ |
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#define CHAFSR_EMU (1UL << 47UL) /* ch,ch+ */ |
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/* Out of range memory error has occurred */ |
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#define JPAFSR_OM (1UL << 47UL) /* jp */ |
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/* HW Corrected system bus data ECC error for read of interrupt vector */ |
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#define CHAFSR_IVC (1UL << 46UL) /* ch,ch+ */ |
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/* Error due to unsupported store */ |
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#define JPAFSR_UMS (1UL << 46UL) /* jp */ |
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/* Uncorrectable system bus data ECC error for read of interrupt vector */ |
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#define CHAFSR_IVU (1UL << 45UL) /* ch,ch+,jp */ |
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/* Unmapped error from system bus */ |
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#define CHAFSR_TO (1UL << 44UL) /* ch,ch+,jp */ |
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/* Bus error response from system bus */ |
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#define CHAFSR_BERR (1UL << 43UL) /* ch,ch+,jp */ |
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/* SW Correctable E-cache ECC error for instruction fetch or data access |
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* other than block load. |
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*/ |
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#define CHAFSR_UCC (1UL << 42UL) /* ch,ch+,jp */ |
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/* Uncorrectable E-cache ECC error for instruction fetch or data access |
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* other than block load. |
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*/ |
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#define CHAFSR_UCU (1UL << 41UL) /* ch,ch+,jp */ |
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/* Copyout HW Corrected ECC error */ |
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#define CHAFSR_CPC (1UL << 40UL) /* ch,ch+,jp */ |
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/* Copyout Uncorrectable ECC error */ |
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#define CHAFSR_CPU (1UL << 39UL) /* ch,ch+,jp */ |
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/* HW Corrected ECC error from E-cache for writeback */ |
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#define CHAFSR_WDC (1UL << 38UL) /* ch,ch+,jp */ |
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/* Uncorrectable ECC error from E-cache for writeback */ |
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#define CHAFSR_WDU (1UL << 37UL) /* ch,ch+,jp */ |
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/* HW Corrected ECC error from E-cache for store merge or block load */ |
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#define CHAFSR_EDC (1UL << 36UL) /* ch,ch+,jp */ |
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/* Uncorrectable ECC error from E-cache for store merge or block load */ |
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#define CHAFSR_EDU (1UL << 35UL) /* ch,ch+,jp */ |
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/* Uncorrectable system bus data ECC error for read of memory or I/O */ |
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#define CHAFSR_UE (1UL << 34UL) /* ch,ch+,jp */ |
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/* HW Corrected system bus data ECC error for read of memory or I/O */ |
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#define CHAFSR_CE (1UL << 33UL) /* ch,ch+,jp */ |
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/* Uncorrectable ECC error from remote cache/memory */ |
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#define JPAFSR_RUE (1UL << 32UL) /* jp */ |
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/* Correctable ECC error from remote cache/memory */ |
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#define JPAFSR_RCE (1UL << 31UL) /* jp */ |
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/* JBUS parity error on returned read data */ |
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#define JPAFSR_BP (1UL << 30UL) /* jp */ |
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/* JBUS parity error on data for writeback or block store */ |
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#define JPAFSR_WBP (1UL << 29UL) /* jp */ |
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/* Foreign read to DRAM incurring correctable ECC error */ |
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#define JPAFSR_FRC (1UL << 28UL) /* jp */ |
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/* Foreign read to DRAM incurring uncorrectable ECC error */ |
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#define JPAFSR_FRU (1UL << 27UL) /* jp */ |
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#define CHAFSR_ERRORS (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \ |
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CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \ |
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CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \ |
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CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \ |
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CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE) |
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#define CHPAFSR_ERRORS (CHPAFSR_DTO | CHPAFSR_DBERR | CHPAFSR_THCE | \ |
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CHPAFSR_TSCE | CHPAFSR_TUE | CHPAFSR_DUE | \ |
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CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \ |
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CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \ |
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CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \ |
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CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \ |
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CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE) |
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#define JPAFSR_ERRORS (JPAFSR_JETO | JPAFSR_SCE | JPAFSR_JEIC | \ |
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JPAFSR_JEIT | CHAFSR_PERR | CHAFSR_IERR | \ |
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CHAFSR_ISAP | JPAFSR_ETP | JPAFSR_OM | \ |
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JPAFSR_UMS | CHAFSR_IVU | CHAFSR_TO | \ |
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CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | \ |
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CHAFSR_CPC | CHAFSR_CPU | CHAFSR_WDC | \ |
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CHAFSR_WDU | CHAFSR_EDC | CHAFSR_EDU | \ |
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CHAFSR_UE | CHAFSR_CE | JPAFSR_RUE | \ |
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JPAFSR_RCE | JPAFSR_BP | JPAFSR_WBP | \ |
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JPAFSR_FRC | JPAFSR_FRU) |
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/* Active JBUS request signal when error occurred */ |
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#define JPAFSR_JBREQ (0x7UL << 24UL) /* jp */ |
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#define JPAFSR_JBREQ_SHIFT 24UL |
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/* L2 cache way information */ |
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#define JPAFSR_ETW (0x3UL << 22UL) /* jp */ |
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#define JPAFSR_ETW_SHIFT 22UL |
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/* System bus MTAG ECC syndrome. This field captures the status of the |
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* first occurrence of the highest-priority error according to the M_SYND |
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* overwrite policy. After the AFSR sticky bit, corresponding to the error |
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* for which the M_SYND is reported, is cleared, the contents of the M_SYND |
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* field will be unchanged by will be unfrozen for further error capture. |
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*/ |
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#define CHAFSR_M_SYNDROME (0xfUL << 16UL) /* ch,ch+,jp */ |
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#define CHAFSR_M_SYNDROME_SHIFT 16UL |
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/* Agenid Id of the foreign device causing the UE/CE errors */ |
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#define JPAFSR_AID (0x1fUL << 9UL) /* jp */ |
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#define JPAFSR_AID_SHIFT 9UL |
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/* System bus or E-cache data ECC syndrome. This field captures the status |
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* of the first occurrence of the highest-priority error according to the |
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* E_SYND overwrite policy. After the AFSR sticky bit, corresponding to the |
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* error for which the E_SYND is reported, is cleare, the contents of the E_SYND |
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* field will be unchanged but will be unfrozen for further error capture. |
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*/ |
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#define CHAFSR_E_SYNDROME (0x1ffUL << 0UL) /* ch,ch+,jp */ |
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#define CHAFSR_E_SYNDROME_SHIFT 0UL |
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/* The AFSR must be explicitly cleared by software, it is not cleared automatically |
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* by a read. Writes to bits <51:33> with bits set will clear the corresponding |
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* bits in the AFSR. Bits associated with disrupting traps must be cleared before |
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* interrupts are re-enabled to prevent multiple traps for the same error. I.e. |
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* PSTATE.IE and AFSR bits control delivery of disrupting traps. |
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* |
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* Since there is only one AFAR, when multiple events have been logged by the |
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* bits in the AFSR, at most one of these events will have its status captured |
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* in the AFAR. The highest priority of those event bits will get AFAR logging. |
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* The AFAR will be unlocked and available to capture the address of another event |
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* as soon as the one bit in AFSR that corresponds to the event logged in AFAR is |
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* cleared. For example, if AFSR.CE is detected, then AFSR.UE (which overwrites |
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* the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked |
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* and ready for another event, even though AFSR.CE is still set. The same rules |
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* also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR. |
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*/ |
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#endif /* _SPARC64_CHAFSR_H */
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