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60 lines
1.7 KiB
60 lines
1.7 KiB
/* |
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* arch/xtensa/platform/xtavnet/include/platform/hardware.h |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 2006 Tensilica Inc. |
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*/ |
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/* |
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* This file contains the hardware configuration of the XTAVNET boards. |
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*/ |
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#include <asm/types.h> |
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#ifndef __XTENSA_XTAVNET_HARDWARE_H |
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#define __XTENSA_XTAVNET_HARDWARE_H |
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/* Default assignment of LX60 devices to external interrupts. */ |
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#ifdef CONFIG_XTENSA_MX |
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#define DUART16552_INTNUM XCHAL_EXTINT3_NUM |
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#define OETH_IRQ XCHAL_EXTINT4_NUM |
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#define C67X00_IRQ XCHAL_EXTINT8_NUM |
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#else |
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#define DUART16552_INTNUM XCHAL_EXTINT0_NUM |
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#define OETH_IRQ XCHAL_EXTINT1_NUM |
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#define C67X00_IRQ XCHAL_EXTINT5_NUM |
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#endif |
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/* |
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* Device addresses and parameters. |
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*/ |
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/* UART */ |
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#define DUART16552_PADDR (XCHAL_KIO_PADDR + 0x0D050020) |
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/* Misc. */ |
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#define XTFPGA_FPGAREGS_VADDR IOADDR(0x0D020000) |
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/* Clock frequency in Hz (read-only): */ |
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#define XTFPGA_CLKFRQ_VADDR (XTFPGA_FPGAREGS_VADDR + 0x04) |
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/* Setting of 8 DIP switches: */ |
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#define DIP_SWITCHES_VADDR (XTFPGA_FPGAREGS_VADDR + 0x0C) |
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/* Software reset (write 0xdead): */ |
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#define XTFPGA_SWRST_VADDR (XTFPGA_FPGAREGS_VADDR + 0x10) |
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/* OpenCores Ethernet controller: */ |
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/* regs + RX/TX descriptors */ |
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#define OETH_REGS_PADDR (XCHAL_KIO_PADDR + 0x0D030000) |
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#define OETH_REGS_SIZE 0x1000 |
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#define OETH_SRAMBUFF_PADDR (XCHAL_KIO_PADDR + 0x0D800000) |
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/* 5*rx buffs + 5*tx buffs */ |
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#define OETH_SRAMBUFF_SIZE (5 * 0x600 + 5 * 0x600) |
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#define C67X00_PADDR (XCHAL_KIO_PADDR + 0x0D0D0000) |
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#define C67X00_SIZE 0x10 |
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#endif /* __XTENSA_XTAVNET_HARDWARE_H */
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