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546 lines
13 KiB
546 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* pci_common.c: PCI controller common support. |
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* |
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* Copyright (C) 1999, 2007 David S. Miller ([email protected]) |
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*/ |
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#include <linux/string.h> |
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#include <linux/slab.h> |
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#include <linux/pci.h> |
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#include <linux/device.h> |
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#include <linux/of_device.h> |
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#include <asm/prom.h> |
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#include <asm/oplib.h> |
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#include "pci_impl.h" |
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#include "pci_sun4v.h" |
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static int config_out_of_range(struct pci_pbm_info *pbm, |
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unsigned long bus, |
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unsigned long devfn, |
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unsigned long reg) |
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{ |
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if (bus < pbm->pci_first_busno || |
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bus > pbm->pci_last_busno) |
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return 1; |
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return 0; |
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} |
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static void *sun4u_config_mkaddr(struct pci_pbm_info *pbm, |
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unsigned long bus, |
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unsigned long devfn, |
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unsigned long reg) |
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{ |
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unsigned long rbits = pbm->config_space_reg_bits; |
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if (config_out_of_range(pbm, bus, devfn, reg)) |
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return NULL; |
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reg = (reg & ((1 << rbits) - 1)); |
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devfn <<= rbits; |
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bus <<= rbits + 8; |
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return (void *) (pbm->config_space | bus | devfn | reg); |
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} |
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/* At least on Sabre, it is necessary to access all PCI host controller |
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* registers at their natural size, otherwise zeros are returned. |
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* Strange but true, and I see no language in the UltraSPARC-IIi |
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* programmer's manual that mentions this even indirectly. |
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*/ |
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static int sun4u_read_pci_cfg_host(struct pci_pbm_info *pbm, |
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unsigned char bus, unsigned int devfn, |
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int where, int size, u32 *value) |
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{ |
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u32 tmp32, *addr; |
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u16 tmp16; |
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u8 tmp8; |
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addr = sun4u_config_mkaddr(pbm, bus, devfn, where); |
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if (!addr) |
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return PCIBIOS_SUCCESSFUL; |
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switch (size) { |
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case 1: |
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if (where < 8) { |
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unsigned long align = (unsigned long) addr; |
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align &= ~1; |
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pci_config_read16((u16 *)align, &tmp16); |
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if (where & 1) |
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*value = tmp16 >> 8; |
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else |
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*value = tmp16 & 0xff; |
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} else { |
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pci_config_read8((u8 *)addr, &tmp8); |
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*value = (u32) tmp8; |
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} |
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break; |
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case 2: |
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if (where < 8) { |
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pci_config_read16((u16 *)addr, &tmp16); |
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*value = (u32) tmp16; |
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} else { |
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pci_config_read8((u8 *)addr, &tmp8); |
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*value = (u32) tmp8; |
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pci_config_read8(((u8 *)addr) + 1, &tmp8); |
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*value |= ((u32) tmp8) << 8; |
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} |
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break; |
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case 4: |
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tmp32 = 0xffffffff; |
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sun4u_read_pci_cfg_host(pbm, bus, devfn, |
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where, 2, &tmp32); |
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*value = tmp32; |
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tmp32 = 0xffffffff; |
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sun4u_read_pci_cfg_host(pbm, bus, devfn, |
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where + 2, 2, &tmp32); |
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*value |= tmp32 << 16; |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int sun4u_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, |
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int where, int size, u32 *value) |
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{ |
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struct pci_pbm_info *pbm = bus_dev->sysdata; |
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unsigned char bus = bus_dev->number; |
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u32 *addr; |
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u16 tmp16; |
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u8 tmp8; |
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switch (size) { |
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case 1: |
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*value = 0xff; |
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break; |
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case 2: |
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*value = 0xffff; |
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break; |
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case 4: |
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*value = 0xffffffff; |
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break; |
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} |
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if (!bus_dev->number && !PCI_SLOT(devfn)) |
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return sun4u_read_pci_cfg_host(pbm, bus, devfn, where, |
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size, value); |
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addr = sun4u_config_mkaddr(pbm, bus, devfn, where); |
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if (!addr) |
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return PCIBIOS_SUCCESSFUL; |
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switch (size) { |
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case 1: |
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pci_config_read8((u8 *)addr, &tmp8); |
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*value = (u32) tmp8; |
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break; |
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case 2: |
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if (where & 0x01) { |
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printk("pci_read_config_word: misaligned reg [%x]\n", |
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where); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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pci_config_read16((u16 *)addr, &tmp16); |
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*value = (u32) tmp16; |
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break; |
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case 4: |
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if (where & 0x03) { |
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printk("pci_read_config_dword: misaligned reg [%x]\n", |
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where); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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pci_config_read32(addr, value); |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int sun4u_write_pci_cfg_host(struct pci_pbm_info *pbm, |
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unsigned char bus, unsigned int devfn, |
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int where, int size, u32 value) |
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{ |
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u32 *addr; |
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addr = sun4u_config_mkaddr(pbm, bus, devfn, where); |
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if (!addr) |
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return PCIBIOS_SUCCESSFUL; |
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switch (size) { |
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case 1: |
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if (where < 8) { |
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unsigned long align = (unsigned long) addr; |
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u16 tmp16; |
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align &= ~1; |
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pci_config_read16((u16 *)align, &tmp16); |
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if (where & 1) { |
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tmp16 &= 0x00ff; |
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tmp16 |= value << 8; |
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} else { |
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tmp16 &= 0xff00; |
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tmp16 |= value; |
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} |
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pci_config_write16((u16 *)align, tmp16); |
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} else |
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pci_config_write8((u8 *)addr, value); |
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break; |
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case 2: |
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if (where < 8) { |
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pci_config_write16((u16 *)addr, value); |
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} else { |
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pci_config_write8((u8 *)addr, value & 0xff); |
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pci_config_write8(((u8 *)addr) + 1, value >> 8); |
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} |
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break; |
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case 4: |
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sun4u_write_pci_cfg_host(pbm, bus, devfn, |
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where, 2, value & 0xffff); |
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sun4u_write_pci_cfg_host(pbm, bus, devfn, |
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where + 2, 2, value >> 16); |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int sun4u_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, |
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int where, int size, u32 value) |
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{ |
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struct pci_pbm_info *pbm = bus_dev->sysdata; |
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unsigned char bus = bus_dev->number; |
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u32 *addr; |
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if (!bus_dev->number && !PCI_SLOT(devfn)) |
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return sun4u_write_pci_cfg_host(pbm, bus, devfn, where, |
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size, value); |
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addr = sun4u_config_mkaddr(pbm, bus, devfn, where); |
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if (!addr) |
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return PCIBIOS_SUCCESSFUL; |
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switch (size) { |
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case 1: |
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pci_config_write8((u8 *)addr, value); |
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break; |
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case 2: |
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if (where & 0x01) { |
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printk("pci_write_config_word: misaligned reg [%x]\n", |
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where); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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pci_config_write16((u16 *)addr, value); |
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break; |
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case 4: |
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if (where & 0x03) { |
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printk("pci_write_config_dword: misaligned reg [%x]\n", |
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where); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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pci_config_write32(addr, value); |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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struct pci_ops sun4u_pci_ops = { |
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.read = sun4u_read_pci_cfg, |
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.write = sun4u_write_pci_cfg, |
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}; |
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static int sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, |
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int where, int size, u32 *value) |
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{ |
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struct pci_pbm_info *pbm = bus_dev->sysdata; |
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u32 devhandle = pbm->devhandle; |
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unsigned int bus = bus_dev->number; |
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unsigned int device = PCI_SLOT(devfn); |
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unsigned int func = PCI_FUNC(devfn); |
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unsigned long ret; |
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if (config_out_of_range(pbm, bus, devfn, where)) { |
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ret = ~0UL; |
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} else { |
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ret = pci_sun4v_config_get(devhandle, |
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HV_PCI_DEVICE_BUILD(bus, device, func), |
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where, size); |
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} |
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switch (size) { |
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case 1: |
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*value = ret & 0xff; |
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break; |
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case 2: |
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*value = ret & 0xffff; |
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break; |
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case 4: |
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*value = ret & 0xffffffff; |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, |
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int where, int size, u32 value) |
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{ |
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struct pci_pbm_info *pbm = bus_dev->sysdata; |
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u32 devhandle = pbm->devhandle; |
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unsigned int bus = bus_dev->number; |
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unsigned int device = PCI_SLOT(devfn); |
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unsigned int func = PCI_FUNC(devfn); |
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if (config_out_of_range(pbm, bus, devfn, where)) { |
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/* Do nothing. */ |
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} else { |
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/* We don't check for hypervisor errors here, but perhaps |
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* we should and influence our return value depending upon |
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* what kind of error is thrown. |
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*/ |
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pci_sun4v_config_put(devhandle, |
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HV_PCI_DEVICE_BUILD(bus, device, func), |
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where, size, value); |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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struct pci_ops sun4v_pci_ops = { |
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.read = sun4v_read_pci_cfg, |
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.write = sun4v_write_pci_cfg, |
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}; |
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void pci_get_pbm_props(struct pci_pbm_info *pbm) |
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{ |
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const u32 *val = of_get_property(pbm->op->dev.of_node, "bus-range", NULL); |
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pbm->pci_first_busno = val[0]; |
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pbm->pci_last_busno = val[1]; |
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val = of_get_property(pbm->op->dev.of_node, "ino-bitmap", NULL); |
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if (val) { |
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pbm->ino_bitmap = (((u64)val[1] << 32UL) | |
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((u64)val[0] << 0UL)); |
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} |
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} |
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static void pci_register_iommu_region(struct pci_pbm_info *pbm) |
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{ |
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const u32 *vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", |
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NULL); |
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if (vdma) { |
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struct resource *rp = kzalloc(sizeof(*rp), GFP_KERNEL); |
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if (!rp) { |
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pr_info("%s: Cannot allocate IOMMU resource.\n", |
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pbm->name); |
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return; |
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} |
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rp->name = "IOMMU"; |
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rp->start = pbm->mem_space.start + (unsigned long) vdma[0]; |
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rp->end = rp->start + (unsigned long) vdma[1] - 1UL; |
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rp->flags = IORESOURCE_BUSY; |
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if (request_resource(&pbm->mem_space, rp)) { |
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pr_info("%s: Unable to request IOMMU resource.\n", |
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pbm->name); |
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kfree(rp); |
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} |
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} |
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} |
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void pci_determine_mem_io_space(struct pci_pbm_info *pbm) |
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{ |
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const struct linux_prom_pci_ranges *pbm_ranges; |
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int i, saw_mem, saw_io; |
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int num_pbm_ranges; |
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/* Corresponding generic code in of_pci_get_host_bridge_resources() */ |
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saw_mem = saw_io = 0; |
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pbm_ranges = of_get_property(pbm->op->dev.of_node, "ranges", &i); |
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if (!pbm_ranges) { |
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prom_printf("PCI: Fatal error, missing PBM ranges property " |
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" for %s\n", |
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pbm->name); |
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prom_halt(); |
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} |
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num_pbm_ranges = i / sizeof(*pbm_ranges); |
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memset(&pbm->mem64_space, 0, sizeof(struct resource)); |
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for (i = 0; i < num_pbm_ranges; i++) { |
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const struct linux_prom_pci_ranges *pr = &pbm_ranges[i]; |
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unsigned long a, size, region_a; |
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u32 parent_phys_hi, parent_phys_lo; |
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u32 child_phys_mid, child_phys_lo; |
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u32 size_hi, size_lo; |
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int type; |
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parent_phys_hi = pr->parent_phys_hi; |
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parent_phys_lo = pr->parent_phys_lo; |
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child_phys_mid = pr->child_phys_mid; |
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child_phys_lo = pr->child_phys_lo; |
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if (tlb_type == hypervisor) |
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parent_phys_hi &= 0x0fffffff; |
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size_hi = pr->size_hi; |
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size_lo = pr->size_lo; |
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type = (pr->child_phys_hi >> 24) & 0x3; |
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a = (((unsigned long)parent_phys_hi << 32UL) | |
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((unsigned long)parent_phys_lo << 0UL)); |
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region_a = (((unsigned long)child_phys_mid << 32UL) | |
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((unsigned long)child_phys_lo << 0UL)); |
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size = (((unsigned long)size_hi << 32UL) | |
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((unsigned long)size_lo << 0UL)); |
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switch (type) { |
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case 0: |
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/* PCI config space, 16MB */ |
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pbm->config_space = a; |
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break; |
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case 1: |
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/* 16-bit IO space, 16MB */ |
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pbm->io_space.start = a; |
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pbm->io_space.end = a + size - 1UL; |
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pbm->io_space.flags = IORESOURCE_IO; |
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pbm->io_offset = a - region_a; |
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saw_io = 1; |
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break; |
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case 2: |
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/* 32-bit MEM space, 2GB */ |
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pbm->mem_space.start = a; |
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pbm->mem_space.end = a + size - 1UL; |
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pbm->mem_space.flags = IORESOURCE_MEM; |
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pbm->mem_offset = a - region_a; |
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saw_mem = 1; |
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break; |
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case 3: |
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/* 64-bit MEM handling */ |
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pbm->mem64_space.start = a; |
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pbm->mem64_space.end = a + size - 1UL; |
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pbm->mem64_space.flags = IORESOURCE_MEM; |
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pbm->mem64_offset = a - region_a; |
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saw_mem = 1; |
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break; |
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default: |
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break; |
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} |
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} |
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if (!saw_io || !saw_mem) { |
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prom_printf("%s: Fatal error, missing %s PBM range.\n", |
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pbm->name, |
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(!saw_io ? "IO" : "MEM")); |
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prom_halt(); |
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} |
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if (pbm->io_space.flags) |
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printk("%s: PCI IO %pR offset %llx\n", |
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pbm->name, &pbm->io_space, pbm->io_offset); |
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if (pbm->mem_space.flags) |
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printk("%s: PCI MEM %pR offset %llx\n", |
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pbm->name, &pbm->mem_space, pbm->mem_offset); |
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if (pbm->mem64_space.flags && pbm->mem_space.flags) { |
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if (pbm->mem64_space.start <= pbm->mem_space.end) |
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pbm->mem64_space.start = pbm->mem_space.end + 1; |
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if (pbm->mem64_space.start > pbm->mem64_space.end) |
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pbm->mem64_space.flags = 0; |
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} |
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if (pbm->mem64_space.flags) |
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printk("%s: PCI MEM64 %pR offset %llx\n", |
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pbm->name, &pbm->mem64_space, pbm->mem64_offset); |
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pbm->io_space.name = pbm->mem_space.name = pbm->name; |
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pbm->mem64_space.name = pbm->name; |
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request_resource(&ioport_resource, &pbm->io_space); |
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request_resource(&iomem_resource, &pbm->mem_space); |
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if (pbm->mem64_space.flags) |
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request_resource(&iomem_resource, &pbm->mem64_space); |
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pci_register_iommu_region(pbm); |
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} |
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/* Generic helper routines for PCI error reporting. */ |
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void pci_scan_for_target_abort(struct pci_pbm_info *pbm, |
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struct pci_bus *pbus) |
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{ |
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struct pci_dev *pdev; |
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struct pci_bus *bus; |
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list_for_each_entry(pdev, &pbus->devices, bus_list) { |
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u16 status, error_bits; |
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pci_read_config_word(pdev, PCI_STATUS, &status); |
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error_bits = |
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(status & (PCI_STATUS_SIG_TARGET_ABORT | |
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PCI_STATUS_REC_TARGET_ABORT)); |
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if (error_bits) { |
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pci_write_config_word(pdev, PCI_STATUS, error_bits); |
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pci_info(pdev, "%s: Device saw Target Abort [%016x]\n", |
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pbm->name, status); |
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} |
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} |
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list_for_each_entry(bus, &pbus->children, node) |
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pci_scan_for_target_abort(pbm, bus); |
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} |
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void pci_scan_for_master_abort(struct pci_pbm_info *pbm, |
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struct pci_bus *pbus) |
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{ |
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struct pci_dev *pdev; |
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struct pci_bus *bus; |
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list_for_each_entry(pdev, &pbus->devices, bus_list) { |
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u16 status, error_bits; |
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pci_read_config_word(pdev, PCI_STATUS, &status); |
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error_bits = |
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(status & (PCI_STATUS_REC_MASTER_ABORT)); |
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if (error_bits) { |
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pci_write_config_word(pdev, PCI_STATUS, error_bits); |
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pci_info(pdev, "%s: Device received Master Abort " |
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"[%016x]\n", pbm->name, status); |
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} |
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} |
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list_for_each_entry(bus, &pbus->children, node) |
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pci_scan_for_master_abort(pbm, bus); |
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} |
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void pci_scan_for_parity_error(struct pci_pbm_info *pbm, |
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struct pci_bus *pbus) |
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{ |
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struct pci_dev *pdev; |
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struct pci_bus *bus; |
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list_for_each_entry(pdev, &pbus->devices, bus_list) { |
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u16 status, error_bits; |
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pci_read_config_word(pdev, PCI_STATUS, &status); |
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error_bits = |
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(status & (PCI_STATUS_PARITY | |
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PCI_STATUS_DETECTED_PARITY)); |
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if (error_bits) { |
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pci_write_config_word(pdev, PCI_STATUS, error_bits); |
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pci_info(pdev, "%s: Device saw Parity Error [%016x]\n", |
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pbm->name, status); |
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} |
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} |
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list_for_each_entry(bus, &pbus->children, node) |
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pci_scan_for_parity_error(pbm, bus); |
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}
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