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511 lines
14 KiB
511 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2009 Daniel Hellstrom ([email protected]) Aeroflex Gaisler AB |
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* Copyright (C) 2009 Konrad Eisele ([email protected]) Aeroflex Gaisler AB |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/errno.h> |
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#include <linux/mutex.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/interrupt.h> |
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#include <linux/of_device.h> |
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#include <linux/clocksource.h> |
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#include <linux/clockchips.h> |
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#include <asm/oplib.h> |
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#include <asm/timer.h> |
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#include <asm/prom.h> |
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#include <asm/leon.h> |
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#include <asm/leon_amba.h> |
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#include <asm/traps.h> |
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#include <asm/cacheflush.h> |
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#include <asm/smp.h> |
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#include <asm/setup.h> |
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#include "kernel.h" |
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#include "prom.h" |
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#include "irq.h" |
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struct leon3_irqctrl_regs_map *leon3_irqctrl_regs; /* interrupt controller base address */ |
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struct leon3_gptimer_regs_map *leon3_gptimer_regs; /* timer controller base address */ |
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int leondebug_irq_disable; |
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int leon_debug_irqout; |
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static volatile u32 dummy_master_l10_counter; |
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unsigned long amba_system_id; |
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static DEFINE_SPINLOCK(leon_irq_lock); |
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static unsigned long leon3_gptimer_idx; /* Timer Index (0..6) within Timer Core */ |
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static unsigned long leon3_gptimer_ackmask; /* For clearing pending bit */ |
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unsigned long leon3_gptimer_irq; /* interrupt controller irq number */ |
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unsigned int sparc_leon_eirq; |
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#define LEON_IMASK(cpu) (&leon3_irqctrl_regs->mask[cpu]) |
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#define LEON_IACK (&leon3_irqctrl_regs->iclear) |
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#define LEON_DO_ACK_HW 1 |
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/* Return the last ACKed IRQ by the Extended IRQ controller. It has already |
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* been (automatically) ACKed when the CPU takes the trap. |
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*/ |
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static inline unsigned int leon_eirq_get(int cpu) |
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{ |
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return LEON3_BYPASS_LOAD_PA(&leon3_irqctrl_regs->intid[cpu]) & 0x1f; |
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} |
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/* Handle one or multiple IRQs from the extended interrupt controller */ |
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static void leon_handle_ext_irq(struct irq_desc *desc) |
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{ |
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unsigned int eirq; |
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struct irq_bucket *p; |
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int cpu = sparc_leon3_cpuid(); |
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eirq = leon_eirq_get(cpu); |
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p = irq_map[eirq]; |
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if ((eirq & 0x10) && p && p->irq) /* bit4 tells if IRQ happened */ |
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generic_handle_irq(p->irq); |
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} |
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/* The extended IRQ controller has been found, this function registers it */ |
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static void leon_eirq_setup(unsigned int eirq) |
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{ |
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unsigned long mask, oldmask; |
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unsigned int veirq; |
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if (eirq < 1 || eirq > 0xf) { |
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printk(KERN_ERR "LEON EXT IRQ NUMBER BAD: %d\n", eirq); |
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return; |
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} |
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veirq = leon_build_device_irq(eirq, leon_handle_ext_irq, "extirq", 0); |
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/* |
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* Unmask the Extended IRQ, the IRQs routed through the Ext-IRQ |
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* controller have a mask-bit of their own, so this is safe. |
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*/ |
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irq_link(veirq); |
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mask = 1 << eirq; |
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oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(boot_cpu_id)); |
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LEON3_BYPASS_STORE_PA(LEON_IMASK(boot_cpu_id), (oldmask | mask)); |
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sparc_leon_eirq = eirq; |
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} |
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unsigned long leon_get_irqmask(unsigned int irq) |
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{ |
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unsigned long mask; |
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if (!irq || ((irq > 0xf) && !sparc_leon_eirq) |
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|| ((irq > 0x1f) && sparc_leon_eirq)) { |
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printk(KERN_ERR |
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"leon_get_irqmask: false irq number: %d\n", irq); |
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mask = 0; |
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} else { |
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mask = LEON_HARD_INT(irq); |
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} |
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return mask; |
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} |
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#ifdef CONFIG_SMP |
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static int irq_choose_cpu(const struct cpumask *affinity) |
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{ |
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cpumask_t mask; |
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cpumask_and(&mask, cpu_online_mask, affinity); |
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if (cpumask_equal(&mask, cpu_online_mask) || cpumask_empty(&mask)) |
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return boot_cpu_id; |
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else |
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return cpumask_first(&mask); |
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} |
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#else |
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#define irq_choose_cpu(affinity) boot_cpu_id |
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#endif |
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static int leon_set_affinity(struct irq_data *data, const struct cpumask *dest, |
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bool force) |
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{ |
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unsigned long mask, oldmask, flags; |
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int oldcpu, newcpu; |
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mask = (unsigned long)data->chip_data; |
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oldcpu = irq_choose_cpu(irq_data_get_affinity_mask(data)); |
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newcpu = irq_choose_cpu(dest); |
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if (oldcpu == newcpu) |
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goto out; |
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/* unmask on old CPU first before enabling on the selected CPU */ |
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spin_lock_irqsave(&leon_irq_lock, flags); |
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oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(oldcpu)); |
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LEON3_BYPASS_STORE_PA(LEON_IMASK(oldcpu), (oldmask & ~mask)); |
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oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(newcpu)); |
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LEON3_BYPASS_STORE_PA(LEON_IMASK(newcpu), (oldmask | mask)); |
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spin_unlock_irqrestore(&leon_irq_lock, flags); |
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out: |
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return IRQ_SET_MASK_OK; |
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} |
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static void leon_unmask_irq(struct irq_data *data) |
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{ |
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unsigned long mask, oldmask, flags; |
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int cpu; |
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mask = (unsigned long)data->chip_data; |
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cpu = irq_choose_cpu(irq_data_get_affinity_mask(data)); |
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spin_lock_irqsave(&leon_irq_lock, flags); |
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oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(cpu)); |
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LEON3_BYPASS_STORE_PA(LEON_IMASK(cpu), (oldmask | mask)); |
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spin_unlock_irqrestore(&leon_irq_lock, flags); |
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} |
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static void leon_mask_irq(struct irq_data *data) |
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{ |
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unsigned long mask, oldmask, flags; |
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int cpu; |
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mask = (unsigned long)data->chip_data; |
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cpu = irq_choose_cpu(irq_data_get_affinity_mask(data)); |
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spin_lock_irqsave(&leon_irq_lock, flags); |
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oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(cpu)); |
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LEON3_BYPASS_STORE_PA(LEON_IMASK(cpu), (oldmask & ~mask)); |
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spin_unlock_irqrestore(&leon_irq_lock, flags); |
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} |
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static unsigned int leon_startup_irq(struct irq_data *data) |
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{ |
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irq_link(data->irq); |
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leon_unmask_irq(data); |
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return 0; |
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} |
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static void leon_shutdown_irq(struct irq_data *data) |
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{ |
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leon_mask_irq(data); |
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irq_unlink(data->irq); |
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} |
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/* Used by external level sensitive IRQ handlers on the LEON: ACK IRQ ctrl */ |
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static void leon_eoi_irq(struct irq_data *data) |
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{ |
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unsigned long mask = (unsigned long)data->chip_data; |
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if (mask & LEON_DO_ACK_HW) |
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LEON3_BYPASS_STORE_PA(LEON_IACK, mask & ~LEON_DO_ACK_HW); |
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} |
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static struct irq_chip leon_irq = { |
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.name = "leon", |
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.irq_startup = leon_startup_irq, |
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.irq_shutdown = leon_shutdown_irq, |
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.irq_mask = leon_mask_irq, |
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.irq_unmask = leon_unmask_irq, |
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.irq_eoi = leon_eoi_irq, |
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.irq_set_affinity = leon_set_affinity, |
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}; |
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/* |
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* Build a LEON IRQ for the edge triggered LEON IRQ controller: |
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* Edge (normal) IRQ - handle_simple_irq, ack=DON'T-CARE, never ack |
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* Level IRQ (PCI|Level-GPIO) - handle_fasteoi_irq, ack=1, ack after ISR |
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* Per-CPU Edge - handle_percpu_irq, ack=0 |
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*/ |
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unsigned int leon_build_device_irq(unsigned int real_irq, |
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irq_flow_handler_t flow_handler, |
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const char *name, int do_ack) |
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{ |
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unsigned int irq; |
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unsigned long mask; |
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struct irq_desc *desc; |
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irq = 0; |
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mask = leon_get_irqmask(real_irq); |
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if (mask == 0) |
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goto out; |
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irq = irq_alloc(real_irq, real_irq); |
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if (irq == 0) |
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goto out; |
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if (do_ack) |
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mask |= LEON_DO_ACK_HW; |
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desc = irq_to_desc(irq); |
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if (!desc || !desc->handle_irq || desc->handle_irq == handle_bad_irq) { |
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irq_set_chip_and_handler_name(irq, &leon_irq, |
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flow_handler, name); |
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irq_set_chip_data(irq, (void *)mask); |
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} |
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out: |
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return irq; |
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} |
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static unsigned int _leon_build_device_irq(struct platform_device *op, |
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unsigned int real_irq) |
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{ |
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return leon_build_device_irq(real_irq, handle_simple_irq, "edge", 0); |
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} |
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void leon_update_virq_handling(unsigned int virq, |
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irq_flow_handler_t flow_handler, |
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const char *name, int do_ack) |
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{ |
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unsigned long mask = (unsigned long)irq_get_chip_data(virq); |
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mask &= ~LEON_DO_ACK_HW; |
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if (do_ack) |
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mask |= LEON_DO_ACK_HW; |
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irq_set_chip_and_handler_name(virq, &leon_irq, |
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flow_handler, name); |
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irq_set_chip_data(virq, (void *)mask); |
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} |
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static u32 leon_cycles_offset(void) |
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{ |
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u32 rld, val, ctrl, off; |
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rld = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].rld); |
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val = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].val); |
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ctrl = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl); |
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if (LEON3_GPTIMER_CTRL_ISPENDING(ctrl)) { |
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val = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].val); |
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off = 2 * rld - val; |
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} else { |
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off = rld - val; |
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} |
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return off; |
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} |
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#ifdef CONFIG_SMP |
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/* smp clockevent irq */ |
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static irqreturn_t leon_percpu_timer_ce_interrupt(int irq, void *unused) |
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{ |
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struct clock_event_device *ce; |
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int cpu = smp_processor_id(); |
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leon_clear_profile_irq(cpu); |
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if (cpu == boot_cpu_id) |
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timer_interrupt(irq, NULL); |
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ce = &per_cpu(sparc32_clockevent, cpu); |
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irq_enter(); |
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if (ce->event_handler) |
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ce->event_handler(ce); |
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irq_exit(); |
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return IRQ_HANDLED; |
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} |
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#endif /* CONFIG_SMP */ |
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void __init leon_init_timers(void) |
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{ |
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int irq, eirq; |
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struct device_node *rootnp, *np, *nnp; |
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struct property *pp; |
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int len; |
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int icsel; |
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int ampopts; |
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int err; |
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u32 config; |
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u32 ctrl; |
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sparc_config.get_cycles_offset = leon_cycles_offset; |
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sparc_config.cs_period = 1000000 / HZ; |
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sparc_config.features |= FEAT_L10_CLOCKSOURCE; |
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#ifndef CONFIG_SMP |
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sparc_config.features |= FEAT_L10_CLOCKEVENT; |
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#endif |
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leondebug_irq_disable = 0; |
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leon_debug_irqout = 0; |
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master_l10_counter = (u32 __iomem *)&dummy_master_l10_counter; |
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dummy_master_l10_counter = 0; |
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rootnp = of_find_node_by_path("/ambapp0"); |
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if (!rootnp) |
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goto bad; |
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/* Find System ID: GRLIB build ID and optional CHIP ID */ |
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pp = of_find_property(rootnp, "systemid", &len); |
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if (pp) |
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amba_system_id = *(unsigned long *)pp->value; |
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/* Find IRQMP IRQ Controller Registers base adr otherwise bail out */ |
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np = of_find_node_by_name(rootnp, "GAISLER_IRQMP"); |
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if (!np) { |
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np = of_find_node_by_name(rootnp, "01_00d"); |
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if (!np) |
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goto bad; |
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} |
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pp = of_find_property(np, "reg", &len); |
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if (!pp) |
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goto bad; |
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leon3_irqctrl_regs = *(struct leon3_irqctrl_regs_map **)pp->value; |
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/* Find GPTIMER Timer Registers base address otherwise bail out. */ |
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nnp = rootnp; |
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retry: |
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np = of_find_node_by_name(nnp, "GAISLER_GPTIMER"); |
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if (!np) { |
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np = of_find_node_by_name(nnp, "01_011"); |
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if (!np) |
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goto bad; |
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} |
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ampopts = 0; |
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pp = of_find_property(np, "ampopts", &len); |
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if (pp) { |
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ampopts = *(int *)pp->value; |
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if (ampopts == 0) { |
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/* Skip this instance, resource already |
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* allocated by other OS */ |
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nnp = np; |
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goto retry; |
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} |
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} |
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/* Select Timer-Instance on Timer Core. Default is zero */ |
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leon3_gptimer_idx = ampopts & 0x7; |
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pp = of_find_property(np, "reg", &len); |
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if (pp) |
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leon3_gptimer_regs = *(struct leon3_gptimer_regs_map **) |
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pp->value; |
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pp = of_find_property(np, "interrupts", &len); |
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if (pp) |
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leon3_gptimer_irq = *(unsigned int *)pp->value; |
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if (!(leon3_gptimer_regs && leon3_irqctrl_regs && leon3_gptimer_irq)) |
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goto bad; |
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ctrl = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl); |
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LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, |
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ctrl | LEON3_GPTIMER_CTRL_PENDING); |
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ctrl = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl); |
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if ((ctrl & LEON3_GPTIMER_CTRL_PENDING) != 0) |
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leon3_gptimer_ackmask = ~LEON3_GPTIMER_CTRL_PENDING; |
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else |
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leon3_gptimer_ackmask = ~0; |
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LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].val, 0); |
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LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].rld, |
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(((1000000 / HZ) - 1))); |
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LEON3_BYPASS_STORE_PA( |
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&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, 0); |
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/* |
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* The IRQ controller may (if implemented) consist of multiple |
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* IRQ controllers, each mapped on a 4Kb boundary. |
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* Each CPU may be routed to different IRQCTRLs, however |
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* we assume that all CPUs (in SMP system) is routed to the |
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* same IRQ Controller, and for non-SMP only one IRQCTRL is |
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* accessed anyway. |
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* In AMP systems, Linux must run on CPU0 for the time being. |
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*/ |
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icsel = LEON3_BYPASS_LOAD_PA(&leon3_irqctrl_regs->icsel[boot_cpu_id/8]); |
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icsel = (icsel >> ((7 - (boot_cpu_id&0x7)) * 4)) & 0xf; |
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leon3_irqctrl_regs += icsel; |
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/* Mask all IRQs on boot-cpu IRQ controller */ |
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LEON3_BYPASS_STORE_PA(&leon3_irqctrl_regs->mask[boot_cpu_id], 0); |
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/* Probe extended IRQ controller */ |
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eirq = (LEON3_BYPASS_LOAD_PA(&leon3_irqctrl_regs->mpstatus) |
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>> 16) & 0xf; |
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if (eirq != 0) |
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leon_eirq_setup(eirq); |
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#ifdef CONFIG_SMP |
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{ |
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unsigned long flags; |
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/* |
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* In SMP, sun4m adds a IPI handler to IRQ trap handler that |
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* LEON never must take, sun4d and LEON overwrites the branch |
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* with a NOP. |
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*/ |
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local_irq_save(flags); |
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patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */ |
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local_ops->cache_all(); |
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local_irq_restore(flags); |
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} |
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#endif |
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config = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->config); |
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if (config & (1 << LEON3_GPTIMER_SEPIRQ)) |
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leon3_gptimer_irq += leon3_gptimer_idx; |
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else if ((config & LEON3_GPTIMER_TIMERS) > 1) |
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pr_warn("GPTIMER uses shared irqs, using other timers of the same core will fail.\n"); |
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#ifdef CONFIG_SMP |
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/* Install per-cpu IRQ handler for broadcasted ticker */ |
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irq = leon_build_device_irq(leon3_gptimer_irq, handle_percpu_irq, |
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"per-cpu", 0); |
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err = request_irq(irq, leon_percpu_timer_ce_interrupt, |
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IRQF_PERCPU | IRQF_TIMER, "timer", NULL); |
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#else |
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irq = _leon_build_device_irq(NULL, leon3_gptimer_irq); |
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err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL); |
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#endif |
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if (err) { |
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pr_err("Unable to attach timer IRQ%d\n", irq); |
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prom_halt(); |
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} |
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LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, |
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LEON3_GPTIMER_EN | |
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LEON3_GPTIMER_RL | |
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LEON3_GPTIMER_LD | |
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LEON3_GPTIMER_IRQEN); |
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return; |
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bad: |
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printk(KERN_ERR "No Timer/irqctrl found\n"); |
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BUG(); |
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return; |
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} |
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static void leon_clear_clock_irq(void) |
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{ |
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u32 ctrl; |
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ctrl = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl); |
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LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, |
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ctrl & leon3_gptimer_ackmask); |
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} |
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static void leon_load_profile_irq(int cpu, unsigned int limit) |
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{ |
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} |
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#ifdef CONFIG_SMP |
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void leon_clear_profile_irq(int cpu) |
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{ |
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} |
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void leon_enable_irq_cpu(unsigned int irq_nr, unsigned int cpu) |
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{ |
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unsigned long mask, flags, *addr; |
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mask = leon_get_irqmask(irq_nr); |
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spin_lock_irqsave(&leon_irq_lock, flags); |
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addr = (unsigned long *)LEON_IMASK(cpu); |
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LEON3_BYPASS_STORE_PA(addr, (LEON3_BYPASS_LOAD_PA(addr) | mask)); |
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spin_unlock_irqrestore(&leon_irq_lock, flags); |
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} |
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#endif |
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void __init leon_init_IRQ(void) |
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{ |
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sparc_config.init_timers = leon_init_timers; |
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sparc_config.build_device_irq = _leon_build_device_irq; |
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sparc_config.clock_rate = 1000000; |
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sparc_config.clear_clock_irq = leon_clear_clock_irq; |
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sparc_config.load_profile_irq = leon_load_profile_irq; |
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}
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