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262 lines
6.4 KiB
262 lines
6.4 KiB
# SPDX-License-Identifier: GPL-2.0 |
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menu "Memory management options" |
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config MMU |
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bool "Support for memory management hardware" |
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depends on !CPU_SH2 |
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default y |
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help |
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Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to |
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boot on these systems, this option must not be set. |
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On other systems (such as the SH-3 and 4) where an MMU exists, |
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turning this off will boot the kernel on these machines with the |
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MMU implicitly switched off. |
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config PAGE_OFFSET |
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hex |
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default "0x80000000" if MMU |
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default "0x00000000" |
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config FORCE_MAX_ZONEORDER |
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int "Maximum zone order" |
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range 9 64 if PAGE_SIZE_16KB |
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default "9" if PAGE_SIZE_16KB |
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range 7 64 if PAGE_SIZE_64KB |
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default "7" if PAGE_SIZE_64KB |
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range 11 64 |
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default "14" if !MMU |
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default "11" |
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help |
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The kernel memory allocator divides physically contiguous memory |
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blocks into "zones", where each zone is a power of two number of |
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pages. This option selects the largest power of two that the kernel |
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keeps in the memory allocator. If you need to allocate very large |
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blocks of physically contiguous memory, then you may need to |
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increase this value. |
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This config option is actually maximum order plus one. For example, |
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a value of 11 means that the largest free memory block is 2^10 pages. |
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The page size is not necessarily 4KB. Keep this in mind when |
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choosing a value for this option. |
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config MEMORY_START |
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hex "Physical memory start address" |
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default "0x08000000" |
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help |
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Computers built with Hitachi SuperH processors always |
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map the ROM starting at address zero. But the processor |
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does not specify the range that RAM takes. |
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The physical memory (RAM) start address will be automatically |
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set to 08000000. Other platforms, such as the Solution Engine |
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boards typically map RAM at 0C000000. |
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Tweak this only when porting to a new machine which does not |
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already have a defconfig. Changing it from the known correct |
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value on any of the known systems will only lead to disaster. |
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config MEMORY_SIZE |
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hex "Physical memory size" |
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default "0x04000000" |
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help |
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This sets the default memory size assumed by your SH kernel. It can |
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be overridden as normal by the 'mem=' argument on the kernel command |
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line. If unsure, consult your board specifications or just leave it |
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as 0x04000000 which was the default value before this became |
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configurable. |
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# Physical addressing modes |
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config 29BIT |
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def_bool !32BIT |
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select UNCACHED_MAPPING |
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config 32BIT |
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bool |
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default !MMU |
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config PMB |
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bool "Support 32-bit physical addressing through PMB" |
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depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP |
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select 32BIT |
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select UNCACHED_MAPPING |
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help |
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If you say Y here, physical addressing will be extended to |
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32-bits through the SH-4A PMB. If this is not set, legacy |
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29-bit physical addressing will be used. |
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config X2TLB |
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def_bool y |
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depends on (CPU_SHX2 || CPU_SHX3) && MMU |
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config VSYSCALL |
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bool "Support vsyscall page" |
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depends on MMU && (CPU_SH3 || CPU_SH4) |
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default y |
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help |
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This will enable support for the kernel mapping a vDSO page |
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in process space, and subsequently handing down the entry point |
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to the libc through the ELF auxiliary vector. |
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From the kernel side this is used for the signal trampoline. |
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For systems with an MMU that can afford to give up a page, |
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(the default value) say Y. |
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config NUMA |
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bool "Non-Uniform Memory Access (NUMA) Support" |
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depends on MMU && SYS_SUPPORTS_NUMA |
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select ARCH_WANT_NUMA_VARIABLE_LOCALITY |
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default n |
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help |
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Some SH systems have many various memories scattered around |
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the address space, each with varying latencies. This enables |
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support for these blocks by binding them to nodes and allowing |
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memory policies to be used for prioritizing and controlling |
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allocation behaviour. |
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config NODES_SHIFT |
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int |
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default "3" if CPU_SUBTYPE_SHX3 |
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default "1" |
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depends on NEED_MULTIPLE_NODES |
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config ARCH_FLATMEM_ENABLE |
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def_bool y |
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depends on !NUMA |
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config ARCH_SPARSEMEM_ENABLE |
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def_bool y |
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select SPARSEMEM_STATIC |
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config ARCH_SPARSEMEM_DEFAULT |
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def_bool y |
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config ARCH_SELECT_MEMORY_MODEL |
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def_bool y |
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config ARCH_ENABLE_MEMORY_HOTPLUG |
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def_bool y |
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depends on SPARSEMEM && MMU |
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config ARCH_ENABLE_MEMORY_HOTREMOVE |
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def_bool y |
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depends on SPARSEMEM && MMU |
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config ARCH_MEMORY_PROBE |
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def_bool y |
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depends on MEMORY_HOTPLUG |
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config IOREMAP_FIXED |
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def_bool y |
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depends on X2TLB |
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config UNCACHED_MAPPING |
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bool |
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config HAVE_SRAM_POOL |
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bool |
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select GENERIC_ALLOCATOR |
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choice |
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prompt "Kernel page size" |
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default PAGE_SIZE_4KB |
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config PAGE_SIZE_4KB |
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bool "4kB" |
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help |
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This is the default page size used by all SuperH CPUs. |
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config PAGE_SIZE_8KB |
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bool "8kB" |
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depends on !MMU || X2TLB |
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help |
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This enables 8kB pages as supported by SH-X2 and later MMUs. |
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config PAGE_SIZE_16KB |
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bool "16kB" |
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depends on !MMU |
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help |
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This enables 16kB pages on MMU-less SH systems. |
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config PAGE_SIZE_64KB |
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bool "64kB" |
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depends on !MMU || CPU_SH4 |
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help |
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This enables support for 64kB pages, possible on all SH-4 |
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CPUs and later. |
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endchoice |
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choice |
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prompt "HugeTLB page size" |
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depends on HUGETLB_PAGE |
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default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB |
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default HUGETLB_PAGE_SIZE_64K |
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config HUGETLB_PAGE_SIZE_64K |
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bool "64kB" |
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depends on !PAGE_SIZE_64KB |
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config HUGETLB_PAGE_SIZE_256K |
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bool "256kB" |
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depends on X2TLB |
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config HUGETLB_PAGE_SIZE_1MB |
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bool "1MB" |
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config HUGETLB_PAGE_SIZE_4MB |
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bool "4MB" |
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depends on X2TLB |
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config HUGETLB_PAGE_SIZE_64MB |
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bool "64MB" |
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depends on X2TLB |
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endchoice |
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config SCHED_MC |
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bool "Multi-core scheduler support" |
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depends on SMP |
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default y |
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help |
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Multi-core scheduler support improves the CPU scheduler's decision |
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making when dealing with multi-core CPU chips at a cost of slightly |
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increased overhead in some places. If unsure say N here. |
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endmenu |
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menu "Cache configuration" |
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config SH7705_CACHE_32KB |
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bool "Enable 32KB cache size for SH7705" |
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depends on CPU_SUBTYPE_SH7705 |
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default y |
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choice |
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prompt "Cache mode" |
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default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 |
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default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) |
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config CACHE_WRITEBACK |
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bool "Write-back" |
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config CACHE_WRITETHROUGH |
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bool "Write-through" |
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help |
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Selecting this option will configure the caches in write-through |
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mode, as opposed to the default write-back configuration. |
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Since there's sill some aliasing issues on SH-4, this option will |
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unfortunately still require the majority of flushing functions to |
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be implemented to deal with aliasing. |
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If unsure, say N. |
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config CACHE_OFF |
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bool "Off" |
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endchoice |
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endmenu
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