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317 lines
7.9 KiB
317 lines
7.9 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2011-2013 Freescale Semiconductor, Inc. |
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* Copyright 2011 Linaro Ltd. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/irqchip.h> |
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#include <linux/of_platform.h> |
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#include <linux/pci.h> |
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#include <linux/phy.h> |
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#include <linux/regmap.h> |
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#include <linux/micrel_phy.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> |
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#include <asm/mach/arch.h> |
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#include <asm/mach/map.h> |
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#include "common.h" |
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#include "cpuidle.h" |
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#include "hardware.h" |
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/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ |
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static int ksz9021rn_phy_fixup(struct phy_device *phydev) |
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{ |
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if (IS_BUILTIN(CONFIG_PHYLIB)) { |
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/* min rx data delay */ |
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phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, |
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0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW); |
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phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); |
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/* max rx/tx clock delay, min rx/tx control delay */ |
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phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, |
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0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); |
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phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); |
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phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, |
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MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); |
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} |
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return 0; |
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} |
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static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) |
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{ |
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phy_write(dev, 0x0d, device); |
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phy_write(dev, 0x0e, reg); |
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phy_write(dev, 0x0d, (1 << 14) | device); |
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phy_write(dev, 0x0e, val); |
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} |
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static int ksz9031rn_phy_fixup(struct phy_device *dev) |
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{ |
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/* |
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* min rx data delay, max rx/tx clock delay, |
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* min rx/tx control delay |
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*/ |
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mmd_write_reg(dev, 2, 4, 0); |
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mmd_write_reg(dev, 2, 5, 0); |
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mmd_write_reg(dev, 2, 8, 0x003ff); |
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return 0; |
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} |
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/* |
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* fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High |
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* as they are used for slots1-7 PERST# |
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*/ |
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static void ventana_pciesw_early_fixup(struct pci_dev *dev) |
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{ |
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u32 dw; |
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if (!of_machine_is_compatible("gw,ventana")) |
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return; |
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if (dev->devfn != 0) |
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return; |
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pci_read_config_dword(dev, 0x62c, &dw); |
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dw |= 0xaaa8; // GPIO1-7 outputs |
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pci_write_config_dword(dev, 0x62c, dw); |
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pci_read_config_dword(dev, 0x644, &dw); |
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dw |= 0xfe; // GPIO1-7 output high |
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pci_write_config_dword(dev, 0x644, dw); |
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msleep(100); |
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} |
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup); |
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup); |
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup); |
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static int ar8031_phy_fixup(struct phy_device *dev) |
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{ |
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u16 val; |
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/* To enable AR8031 output a 125MHz clk from CLK_25M */ |
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phy_write(dev, 0xd, 0x7); |
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phy_write(dev, 0xe, 0x8016); |
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phy_write(dev, 0xd, 0x4007); |
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val = phy_read(dev, 0xe); |
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val &= 0xffe3; |
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val |= 0x18; |
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phy_write(dev, 0xe, val); |
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/* introduce tx clock delay */ |
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phy_write(dev, 0x1d, 0x5); |
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val = phy_read(dev, 0x1e); |
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val |= 0x0100; |
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phy_write(dev, 0x1e, val); |
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return 0; |
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} |
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#define PHY_ID_AR8031 0x004dd074 |
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static int ar8035_phy_fixup(struct phy_device *dev) |
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{ |
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u16 val; |
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/* Ar803x phy SmartEEE feature cause link status generates glitch, |
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* which cause ethernet link down/up issue, so disable SmartEEE |
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*/ |
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phy_write(dev, 0xd, 0x3); |
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phy_write(dev, 0xe, 0x805d); |
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phy_write(dev, 0xd, 0x4003); |
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val = phy_read(dev, 0xe); |
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phy_write(dev, 0xe, val & ~(1 << 8)); |
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/* |
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* Enable 125MHz clock from CLK_25M on the AR8031. This |
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* is fed in to the IMX6 on the ENET_REF_CLK (V22) pad. |
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* Also, introduce a tx clock delay. |
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* |
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* This is the same as is the AR8031 fixup. |
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*/ |
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ar8031_phy_fixup(dev); |
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/*check phy power*/ |
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val = phy_read(dev, 0x0); |
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if (val & BMCR_PDOWN) |
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phy_write(dev, 0x0, val & ~BMCR_PDOWN); |
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return 0; |
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} |
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#define PHY_ID_AR8035 0x004dd072 |
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static void __init imx6q_enet_phy_init(void) |
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{ |
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if (IS_BUILTIN(CONFIG_PHYLIB)) { |
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phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, |
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ksz9021rn_phy_fixup); |
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phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, |
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ksz9031rn_phy_fixup); |
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phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef, |
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ar8031_phy_fixup); |
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phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef, |
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ar8035_phy_fixup); |
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} |
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} |
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static void __init imx6q_1588_init(void) |
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{ |
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struct device_node *np; |
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struct clk *ptp_clk; |
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struct clk *enet_ref; |
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struct regmap *gpr; |
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u32 clksel; |
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec"); |
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if (!np) { |
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pr_warn("%s: failed to find fec node\n", __func__); |
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return; |
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} |
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ptp_clk = of_clk_get(np, 2); |
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if (IS_ERR(ptp_clk)) { |
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pr_warn("%s: failed to get ptp clock\n", __func__); |
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goto put_node; |
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} |
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enet_ref = clk_get_sys(NULL, "enet_ref"); |
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if (IS_ERR(enet_ref)) { |
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pr_warn("%s: failed to get enet clock\n", __func__); |
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goto put_ptp_clk; |
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} |
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/* |
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* If enet_ref from ANATOP/CCM is the PTP clock source, we need to |
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* set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad |
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* (external OSC), and we need to clear the bit. |
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*/ |
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clksel = clk_is_match(ptp_clk, enet_ref) ? |
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IMX6Q_GPR1_ENET_CLK_SEL_ANATOP : |
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IMX6Q_GPR1_ENET_CLK_SEL_PAD; |
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gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); |
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if (!IS_ERR(gpr)) |
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regmap_update_bits(gpr, IOMUXC_GPR1, |
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IMX6Q_GPR1_ENET_CLK_SEL_MASK, |
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clksel); |
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else |
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pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); |
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clk_put(enet_ref); |
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put_ptp_clk: |
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clk_put(ptp_clk); |
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put_node: |
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of_node_put(np); |
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} |
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static void __init imx6q_axi_init(void) |
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{ |
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struct regmap *gpr; |
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unsigned int mask; |
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gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); |
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if (!IS_ERR(gpr)) { |
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/* |
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* Enable the cacheable attribute of VPU and IPU |
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* AXI transactions. |
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*/ |
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mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL | |
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IMX6Q_GPR4_VPU_RD_CACHE_SEL | |
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IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | |
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IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK | |
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IMX6Q_GPR4_IPU_WR_CACHE_CTL | |
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IMX6Q_GPR4_IPU_RD_CACHE_CTL; |
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regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask); |
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/* Increase IPU read QoS priority */ |
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regmap_update_bits(gpr, IOMUXC_GPR6, |
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IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK | |
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IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK, |
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(0xf << 16) | (0x7 << 20)); |
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regmap_update_bits(gpr, IOMUXC_GPR7, |
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IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK | |
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IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK, |
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(0xf << 16) | (0x7 << 20)); |
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} else { |
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pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); |
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} |
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} |
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static void __init imx6q_init_machine(void) |
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{ |
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if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) |
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/* |
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* SoCs that identify as i.MX6Q >= rev 2.0 are really i.MX6QP. |
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* Quirk: i.MX6QP revision = i.MX6Q revision - (1, 0), |
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* e.g. i.MX6QP rev 1.1 identifies as i.MX6Q rev 2.1. |
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*/ |
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imx_print_silicon_rev("i.MX6QP", imx_get_soc_revision() - 0x10); |
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else |
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imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", |
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imx_get_soc_revision()); |
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imx6q_enet_phy_init(); |
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of_platform_default_populate(NULL, NULL, NULL); |
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imx_anatop_init(); |
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cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init(); |
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imx6q_1588_init(); |
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imx6q_axi_init(); |
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} |
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static void __init imx6q_init_late(void) |
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{ |
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/* |
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* WAIT mode is broken on imx6 Dual/Quad revision 1.0 and 1.1 so |
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* there is no point to run cpuidle on them. |
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* |
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* It does work on imx6 Solo/DualLite starting from 1.1 |
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*/ |
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if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) || |
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(cpu_is_imx6dl() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_0)) |
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imx6q_cpuidle_init(); |
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if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) |
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platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); |
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} |
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static void __init imx6q_map_io(void) |
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{ |
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debug_ll_io_init(); |
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imx_scu_map_io(); |
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} |
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static void __init imx6q_init_irq(void) |
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{ |
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imx_gpc_check_dt(); |
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imx_init_revision_from_anatop(); |
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imx_init_l2cache(); |
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imx_src_init(); |
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irqchip_init(); |
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imx6_pm_ccm_init("fsl,imx6q-ccm"); |
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} |
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static const char * const imx6q_dt_compat[] __initconst = { |
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"fsl,imx6dl", |
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"fsl,imx6q", |
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"fsl,imx6qp", |
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NULL, |
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}; |
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DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)") |
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.l2c_aux_val = 0, |
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.l2c_aux_mask = ~0, |
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.smp = smp_ops(imx_smp_ops), |
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.map_io = imx6q_map_io, |
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.init_irq = imx6q_init_irq, |
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.init_machine = imx6q_init_machine, |
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.init_late = imx6q_init_late, |
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.dt_compat = imx6q_dt_compat, |
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MACHINE_END
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