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199 lines
7.0 KiB
199 lines
7.0 KiB
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ |
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/* |
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* This file is provided under a dual BSD/GPLv2 license. When using or |
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* redistributing this file, you may do so under either license. |
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* |
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* Copyright(c) 2018 Intel Corporation. All rights reserved. |
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*/ |
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#ifndef __INCLUDE_SOUND_SOF_DAI_INTEL_H__ |
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#define __INCLUDE_SOUND_SOF_DAI_INTEL_H__ |
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#include <sound/sof/header.h> |
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/* ssc1: TINTE */ |
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#define SOF_DAI_INTEL_SSP_QUIRK_TINTE (1 << 0) |
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/* ssc1: PINTE */ |
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#define SOF_DAI_INTEL_SSP_QUIRK_PINTE (1 << 1) |
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/* ssc2: SMTATF */ |
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#define SOF_DAI_INTEL_SSP_QUIRK_SMTATF (1 << 2) |
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/* ssc2: MMRATF */ |
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#define SOF_DAI_INTEL_SSP_QUIRK_MMRATF (1 << 3) |
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/* ssc2: PSPSTWFDFD */ |
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#define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD (1 << 4) |
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/* ssc2: PSPSRWFDFD */ |
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#define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD (1 << 5) |
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/* ssc1: LBM */ |
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#define SOF_DAI_INTEL_SSP_QUIRK_LBM (1 << 6) |
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/* here is the possibility to define others aux macros */ |
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#define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX 38 |
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#define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX 31 |
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/* SSP clocks control settings |
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* |
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* Macros for clks_control field in sof_ipc_dai_ssp_params struct. |
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*/ |
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/* mclk 0 disable */ |
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#define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE BIT(0) |
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/* mclk 1 disable */ |
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#define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE BIT(1) |
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/* mclk keep active */ |
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#define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA BIT(2) |
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/* bclk keep active */ |
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#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA BIT(3) |
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/* fs keep active */ |
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#define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4) |
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/* bclk idle */ |
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#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5) |
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/* DMIC max. four controllers for eight microphone channels */ |
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#define SOF_DAI_INTEL_DMIC_NUM_CTRL 4 |
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/* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */ |
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struct sof_ipc_dai_ssp_params { |
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struct sof_ipc_hdr hdr; |
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uint16_t reserved1; |
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uint16_t mclk_id; |
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uint32_t mclk_rate; /* mclk frequency in Hz */ |
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uint32_t fsync_rate; /* fsync frequency in Hz */ |
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uint32_t bclk_rate; /* bclk frequency in Hz */ |
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/* TDM */ |
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uint32_t tdm_slots; |
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uint32_t rx_slots; |
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uint32_t tx_slots; |
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/* data */ |
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uint32_t sample_valid_bits; |
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uint16_t tdm_slot_width; |
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uint16_t reserved2; /* alignment */ |
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/* MCLK */ |
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uint32_t mclk_direction; |
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uint16_t frame_pulse_width; |
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uint16_t tdm_per_slot_padding_flag; |
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uint32_t clks_control; |
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uint32_t quirks; |
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uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK |
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* will be driven, before sending data |
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*/ |
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} __packed; |
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/* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */ |
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struct sof_ipc_dai_hda_params { |
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struct sof_ipc_hdr hdr; |
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uint32_t link_dma_ch; |
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uint32_t rate; |
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uint32_t channels; |
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} __packed; |
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/* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */ |
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struct sof_ipc_dai_alh_params { |
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struct sof_ipc_hdr hdr; |
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uint32_t stream_id; |
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uint32_t rate; |
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uint32_t channels; |
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/* reserved for future use */ |
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uint32_t reserved[13]; |
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} __packed; |
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/* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */ |
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/* This struct is defined per 2ch PDM controller available in the platform. |
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* Normally it is sufficient to set the used microphone specific enables to 1 |
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* and keep other parameters as zero. The customizations are: |
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* |
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* 1. If a device mixes different microphones types with different polarity |
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* and/or the absolute polarity matters the PCM signal from a microphone |
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* can be inverted with the controls. |
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* |
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* 2. If the microphones in a stereo pair do not appear in captured stream |
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* in desired order due to board schematics choises they can be swapped with |
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* the clk_edge parameter. |
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* |
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* 3. If PDM bit errors are seen in capture (poor quality) the skew parameter |
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* that delays the sampling time of data by half cycles of DMIC source clock |
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* can be tried for improvement. However there is no guarantee for this to fix |
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* data integrity problems. |
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*/ |
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struct sof_ipc_dai_dmic_pdm_ctrl { |
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struct sof_ipc_hdr hdr; |
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uint16_t id; /**< PDM controller ID */ |
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uint16_t enable_mic_a; /**< Use A (left) channel mic (0 or 1)*/ |
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uint16_t enable_mic_b; /**< Use B (right) channel mic (0 or 1)*/ |
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uint16_t polarity_mic_a; /**< Optionally invert mic A signal (0 or 1) */ |
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uint16_t polarity_mic_b; /**< Optionally invert mic B signal (0 or 1) */ |
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uint16_t clk_edge; /**< Optionally swap data clock edge (0 or 1) */ |
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uint16_t skew; /**< Adjust PDM data sampling vs. clock (0..15) */ |
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uint16_t reserved[3]; /**< Make sure the total size is 4 bytes aligned */ |
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} __packed; |
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/* This struct contains the global settings for all 2ch PDM controllers. The |
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* version number used in configuration data is checked vs. version used by |
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* device driver src/drivers/dmic.c need to match. It is incremented from |
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* initial value 1 if updates done for the to driver would alter the operation |
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* of the microphone. |
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* |
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* Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max) |
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* parameters need to be set as defined in microphone data sheet. E.g. clock |
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* range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are |
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* multi-mode capable and there may be denied mic clock frequencies between |
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* the modes. In such case set the clock range limits of the desired mode to |
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* avoid the driver to set clock to an illegal rate. |
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* |
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* The duty cycle could be set to 48-52% if not known. Generally these |
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* parameters can be altered within data sheet specified limits to match |
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* required audio application performance power. |
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* |
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* The microphone clock needs to be usually about 50-80 times the used audio |
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* sample rate. With highest sample rates above 48 kHz this can relaxed |
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* somewhat. |
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* |
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* The parameter wake_up_time describes how long time the microphone needs |
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* for the data line to produce valid output from mic clock start. The driver |
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* will mute the captured audio for the given time. The min_clock_on_time |
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* parameter is used to prevent too short clock bursts to happen. The driver |
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* will keep the clock active after capture stop if this time is not yet |
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* met. The unit for both is microseconds (us). Exceed of 100 ms will be |
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* treated as an error. |
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*/ |
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struct sof_ipc_dai_dmic_params { |
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struct sof_ipc_hdr hdr; |
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uint32_t driver_ipc_version; /**< Version (1..N) */ |
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uint32_t pdmclk_min; /**< Minimum microphone clock in Hz (100000..N) */ |
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uint32_t pdmclk_max; /**< Maximum microphone clock in Hz (min...N) */ |
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uint32_t fifo_fs; /**< FIFO sample rate in Hz (8000..96000) */ |
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uint32_t reserved_1; /**< Reserved */ |
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uint16_t fifo_bits; /**< FIFO word length (16 or 32) */ |
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uint16_t fifo_bits_b; /**< Deprecated since firmware ABI 3.0.1 */ |
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uint16_t duty_min; /**< Min. mic clock duty cycle in % (20..80) */ |
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uint16_t duty_max; /**< Max. mic clock duty cycle in % (min..80) */ |
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uint32_t num_pdm_active; /**< Number of active pdm controllers. */ |
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/**< Range is 1..SOF_DAI_INTEL_DMIC_NUM_CTRL */ |
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uint32_t wake_up_time; /**< Time from clock start to data (us) */ |
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uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */ |
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uint32_t unmute_ramp_time; /**< Length of logarithmic gain ramp (ms) */ |
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/* reserved for future use */ |
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uint32_t reserved[5]; |
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/**< PDM controllers configuration */ |
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struct sof_ipc_dai_dmic_pdm_ctrl pdm[SOF_DAI_INTEL_DMIC_NUM_CTRL]; |
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} __packed; |
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#endif
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