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117 lines
2.6 KiB
117 lines
2.6 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* cisreg.h |
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* |
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* The initial developer of the original code is David A. Hinds |
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* <[email protected]>. Portions created by David A. Hinds |
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* are Copyright (C) 1999 David A. Hinds. All Rights Reserved. |
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* |
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* (C) 1999 David A. Hinds |
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*/ |
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#ifndef _LINUX_CISREG_H |
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#define _LINUX_CISREG_H |
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/* |
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* Offsets from ConfigBase for CIS registers |
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*/ |
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#define CISREG_COR 0x00 |
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#define CISREG_CCSR 0x02 |
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#define CISREG_PRR 0x04 |
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#define CISREG_SCR 0x06 |
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#define CISREG_ESR 0x08 |
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#define CISREG_IOBASE_0 0x0a |
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#define CISREG_IOBASE_1 0x0c |
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#define CISREG_IOBASE_2 0x0e |
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#define CISREG_IOBASE_3 0x10 |
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#define CISREG_IOSIZE 0x12 |
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/* |
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* Configuration Option Register |
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*/ |
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#define COR_CONFIG_MASK 0x3f |
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#define COR_MFC_CONFIG_MASK 0x38 |
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#define COR_FUNC_ENA 0x01 |
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#define COR_ADDR_DECODE 0x02 |
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#define COR_IREQ_ENA 0x04 |
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#define COR_LEVEL_REQ 0x40 |
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#define COR_SOFT_RESET 0x80 |
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/* |
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* Card Configuration and Status Register |
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*/ |
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#define CCSR_INTR_ACK 0x01 |
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#define CCSR_INTR_PENDING 0x02 |
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#define CCSR_POWER_DOWN 0x04 |
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#define CCSR_AUDIO_ENA 0x08 |
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#define CCSR_IOIS8 0x20 |
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#define CCSR_SIGCHG_ENA 0x40 |
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#define CCSR_CHANGED 0x80 |
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/* |
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* Pin Replacement Register |
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*/ |
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#define PRR_WP_STATUS 0x01 |
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#define PRR_READY_STATUS 0x02 |
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#define PRR_BVD2_STATUS 0x04 |
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#define PRR_BVD1_STATUS 0x08 |
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#define PRR_WP_EVENT 0x10 |
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#define PRR_READY_EVENT 0x20 |
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#define PRR_BVD2_EVENT 0x40 |
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#define PRR_BVD1_EVENT 0x80 |
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/* |
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* Socket and Copy Register |
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*/ |
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#define SCR_SOCKET_NUM 0x0f |
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#define SCR_COPY_NUM 0x70 |
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/* |
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* Extended Status Register |
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*/ |
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#define ESR_REQ_ATTN_ENA 0x01 |
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#define ESR_REQ_ATTN 0x10 |
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/* |
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* CardBus Function Status Registers |
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*/ |
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#define CBFN_EVENT 0x00 |
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#define CBFN_MASK 0x04 |
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#define CBFN_STATE 0x08 |
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#define CBFN_FORCE 0x0c |
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/* |
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* These apply to all the CardBus function registers |
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*/ |
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#define CBFN_WP 0x0001 |
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#define CBFN_READY 0x0002 |
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#define CBFN_BVD2 0x0004 |
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#define CBFN_BVD1 0x0008 |
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#define CBFN_GWAKE 0x0010 |
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#define CBFN_INTR 0x8000 |
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/* |
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* Extra bits in the Function Event Mask Register |
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*/ |
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#define FEMR_BAM_ENA 0x0020 |
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#define FEMR_PWM_ENA 0x0040 |
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#define FEMR_WKUP_MASK 0x4000 |
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/* |
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* Indirect Addressing Registers for Zoomed Video: these are addresses |
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* in common memory space |
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*/ |
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#define CISREG_ICTRL0 0x02 /* control registers */ |
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#define CISREG_ICTRL1 0x03 |
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#define CISREG_IADDR0 0x04 /* address registers */ |
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#define CISREG_IADDR1 0x05 |
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#define CISREG_IADDR2 0x06 |
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#define CISREG_IADDR3 0x07 |
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#define CISREG_IDATA0 0x08 /* data registers */ |
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#define CISREG_IDATA1 0x09 |
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#define ICTRL0_COMMON 0x01 |
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#define ICTRL0_AUTOINC 0x02 |
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#define ICTRL0_BYTEGRAN 0x04 |
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#endif /* _LINUX_CISREG_H */
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