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244 lines
5.5 KiB
244 lines
5.5 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* PIC32 watchdog driver |
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* |
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* Joshua Henderson <[email protected]> |
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* Copyright (c) 2016, Microchip Technology Inc. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/device.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm.h> |
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#include <linux/watchdog.h> |
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#include <asm/mach-pic32/pic32.h> |
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/* Watchdog Timer Registers */ |
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#define WDTCON_REG 0x00 |
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/* Watchdog Timer Control Register fields */ |
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#define WDTCON_WIN_EN BIT(0) |
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#define WDTCON_RMCS_MASK 0x0003 |
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#define WDTCON_RMCS_SHIFT 0x0006 |
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#define WDTCON_RMPS_MASK 0x001F |
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#define WDTCON_RMPS_SHIFT 0x0008 |
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#define WDTCON_ON BIT(15) |
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#define WDTCON_CLR_KEY 0x5743 |
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/* Reset Control Register fields for watchdog */ |
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#define RESETCON_TIMEOUT_IDLE BIT(2) |
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#define RESETCON_TIMEOUT_SLEEP BIT(3) |
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#define RESETCON_WDT_TIMEOUT BIT(4) |
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struct pic32_wdt { |
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void __iomem *regs; |
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void __iomem *rst_base; |
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struct clk *clk; |
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}; |
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static inline bool pic32_wdt_is_win_enabled(struct pic32_wdt *wdt) |
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{ |
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return !!(readl(wdt->regs + WDTCON_REG) & WDTCON_WIN_EN); |
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} |
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static inline u32 pic32_wdt_get_post_scaler(struct pic32_wdt *wdt) |
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{ |
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u32 v = readl(wdt->regs + WDTCON_REG); |
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return (v >> WDTCON_RMPS_SHIFT) & WDTCON_RMPS_MASK; |
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} |
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static inline u32 pic32_wdt_get_clk_id(struct pic32_wdt *wdt) |
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{ |
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u32 v = readl(wdt->regs + WDTCON_REG); |
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return (v >> WDTCON_RMCS_SHIFT) & WDTCON_RMCS_MASK; |
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} |
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static int pic32_wdt_bootstatus(struct pic32_wdt *wdt) |
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{ |
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u32 v = readl(wdt->rst_base); |
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writel(RESETCON_WDT_TIMEOUT, PIC32_CLR(wdt->rst_base)); |
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return v & RESETCON_WDT_TIMEOUT; |
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} |
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static u32 pic32_wdt_get_timeout_secs(struct pic32_wdt *wdt, struct device *dev) |
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{ |
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unsigned long rate; |
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u32 period, ps, terminal; |
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rate = clk_get_rate(wdt->clk); |
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dev_dbg(dev, "wdt: clk_id %d, clk_rate %lu (prescale)\n", |
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pic32_wdt_get_clk_id(wdt), rate); |
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/* default, prescaler of 32 (i.e. div-by-32) is implicit. */ |
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rate >>= 5; |
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if (!rate) |
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return 0; |
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/* calculate terminal count from postscaler. */ |
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ps = pic32_wdt_get_post_scaler(wdt); |
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terminal = BIT(ps); |
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/* find time taken (in secs) to reach terminal count */ |
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period = terminal / rate; |
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dev_dbg(dev, |
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"wdt: clk_rate %lu (postscale) / terminal %d, timeout %dsec\n", |
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rate, terminal, period); |
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return period; |
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} |
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static void pic32_wdt_keepalive(struct pic32_wdt *wdt) |
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{ |
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/* write key through single half-word */ |
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writew(WDTCON_CLR_KEY, wdt->regs + WDTCON_REG + 2); |
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} |
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static int pic32_wdt_start(struct watchdog_device *wdd) |
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{ |
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struct pic32_wdt *wdt = watchdog_get_drvdata(wdd); |
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writel(WDTCON_ON, PIC32_SET(wdt->regs + WDTCON_REG)); |
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pic32_wdt_keepalive(wdt); |
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return 0; |
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} |
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static int pic32_wdt_stop(struct watchdog_device *wdd) |
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{ |
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struct pic32_wdt *wdt = watchdog_get_drvdata(wdd); |
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writel(WDTCON_ON, PIC32_CLR(wdt->regs + WDTCON_REG)); |
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/* |
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* Cannot touch registers in the CPU cycle following clearing the |
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* ON bit. |
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*/ |
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nop(); |
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return 0; |
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} |
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static int pic32_wdt_ping(struct watchdog_device *wdd) |
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{ |
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struct pic32_wdt *wdt = watchdog_get_drvdata(wdd); |
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pic32_wdt_keepalive(wdt); |
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return 0; |
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} |
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static const struct watchdog_ops pic32_wdt_fops = { |
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.owner = THIS_MODULE, |
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.start = pic32_wdt_start, |
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.stop = pic32_wdt_stop, |
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.ping = pic32_wdt_ping, |
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}; |
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static const struct watchdog_info pic32_wdt_ident = { |
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.options = WDIOF_KEEPALIVEPING | |
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WDIOF_MAGICCLOSE | WDIOF_CARDRESET, |
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.identity = "PIC32 Watchdog", |
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}; |
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static struct watchdog_device pic32_wdd = { |
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.info = &pic32_wdt_ident, |
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.ops = &pic32_wdt_fops, |
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}; |
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static const struct of_device_id pic32_wdt_dt_ids[] = { |
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{ .compatible = "microchip,pic32mzda-wdt", }, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, pic32_wdt_dt_ids); |
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static void pic32_clk_disable_unprepare(void *data) |
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{ |
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clk_disable_unprepare(data); |
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} |
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static int pic32_wdt_drv_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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int ret; |
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struct watchdog_device *wdd = &pic32_wdd; |
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struct pic32_wdt *wdt; |
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wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
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if (!wdt) |
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return -ENOMEM; |
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wdt->regs = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(wdt->regs)) |
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return PTR_ERR(wdt->regs); |
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wdt->rst_base = devm_ioremap(dev, PIC32_BASE_RESET, 0x10); |
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if (!wdt->rst_base) |
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return -ENOMEM; |
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wdt->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(wdt->clk)) { |
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dev_err(dev, "clk not found\n"); |
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return PTR_ERR(wdt->clk); |
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} |
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ret = clk_prepare_enable(wdt->clk); |
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if (ret) { |
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dev_err(dev, "clk enable failed\n"); |
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return ret; |
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} |
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ret = devm_add_action_or_reset(dev, pic32_clk_disable_unprepare, |
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wdt->clk); |
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if (ret) |
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return ret; |
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if (pic32_wdt_is_win_enabled(wdt)) { |
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dev_err(dev, "windowed-clear mode is not supported.\n"); |
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return -ENODEV; |
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} |
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wdd->timeout = pic32_wdt_get_timeout_secs(wdt, dev); |
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if (!wdd->timeout) { |
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dev_err(dev, "failed to read watchdog register timeout\n"); |
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return -EINVAL; |
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} |
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dev_info(dev, "timeout %d\n", wdd->timeout); |
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wdd->bootstatus = pic32_wdt_bootstatus(wdt) ? WDIOF_CARDRESET : 0; |
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watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT); |
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watchdog_set_drvdata(wdd, wdt); |
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ret = devm_watchdog_register_device(dev, wdd); |
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if (ret) |
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return ret; |
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platform_set_drvdata(pdev, wdd); |
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return 0; |
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} |
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static struct platform_driver pic32_wdt_driver = { |
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.probe = pic32_wdt_drv_probe, |
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.driver = { |
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.name = "pic32-wdt", |
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.of_match_table = of_match_ptr(pic32_wdt_dt_ids), |
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} |
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}; |
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module_platform_driver(pic32_wdt_driver); |
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MODULE_AUTHOR("Joshua Henderson <[email protected]>"); |
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MODULE_DESCRIPTION("Microchip PIC32 Watchdog Timer"); |
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MODULE_LICENSE("GPL");
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