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496 lines
13 KiB
496 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/** |
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* dwc3-pci.c - PCI Specific glue layer |
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* |
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com |
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* |
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* Authors: Felipe Balbi <[email protected]>, |
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* Sebastian Andrzej Siewior <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/slab.h> |
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#include <linux/pci.h> |
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#include <linux/workqueue.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/platform_device.h> |
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#include <linux/gpio/consumer.h> |
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#include <linux/gpio/machine.h> |
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#include <linux/acpi.h> |
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#include <linux/delay.h> |
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#define PCI_DEVICE_ID_INTEL_BYT 0x0f37 |
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#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e |
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#define PCI_DEVICE_ID_INTEL_BSW 0x22b7 |
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#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 |
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#define PCI_DEVICE_ID_INTEL_SPTH 0xa130 |
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#define PCI_DEVICE_ID_INTEL_BXT 0x0aaa |
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#define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa |
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#define PCI_DEVICE_ID_INTEL_APL 0x5aaa |
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#define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 |
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#define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee |
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#define PCI_DEVICE_ID_INTEL_CMLH 0x06ee |
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#define PCI_DEVICE_ID_INTEL_GLK 0x31aa |
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#define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee |
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#define PCI_DEVICE_ID_INTEL_CNPH 0xa36e |
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#define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 |
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#define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee |
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#define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e |
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#define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee |
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#define PCI_DEVICE_ID_INTEL_TGPH 0x43ee |
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#define PCI_DEVICE_ID_INTEL_JSP 0x4dee |
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#define PCI_DEVICE_ID_INTEL_ADLP 0x51ee |
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#define PCI_DEVICE_ID_INTEL_ADLM 0x54ee |
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#define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1 |
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#define PCI_DEVICE_ID_INTEL_TGL 0x9a15 |
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#define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" |
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#define PCI_INTEL_BXT_FUNC_PMU_PWR 4 |
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#define PCI_INTEL_BXT_STATE_D0 0 |
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#define PCI_INTEL_BXT_STATE_D3 3 |
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#define GP_RWBAR 1 |
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#define GP_RWREG1 0xa0 |
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#define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) |
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/** |
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* struct dwc3_pci - Driver private structure |
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* @dwc3: child dwc3 platform_device |
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* @pci: our link to PCI bus |
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* @guid: _DSM GUID |
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* @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM |
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* @wakeup_work: work for asynchronous resume |
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*/ |
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struct dwc3_pci { |
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struct platform_device *dwc3; |
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struct pci_dev *pci; |
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guid_t guid; |
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unsigned int has_dsm_for_pm:1; |
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struct work_struct wakeup_work; |
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}; |
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static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; |
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static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; |
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static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { |
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{ "reset-gpios", &reset_gpios, 1 }, |
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{ "cs-gpios", &cs_gpios, 1 }, |
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{ }, |
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}; |
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static struct gpiod_lookup_table platform_bytcr_gpios = { |
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.dev_id = "0000:00:16.0", |
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.table = { |
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GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH), |
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GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH), |
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{} |
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}, |
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}; |
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static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) |
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{ |
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void __iomem *reg; |
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u32 value; |
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reg = pcim_iomap(pci, GP_RWBAR, 0); |
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if (!reg) |
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return -ENOMEM; |
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value = readl(reg + GP_RWREG1); |
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if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) |
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goto unmap; /* ULPI refclk already enabled */ |
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value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; |
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writel(value, reg + GP_RWREG1); |
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/* This comes from the Intel Android x86 tree w/o any explanation */ |
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msleep(100); |
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unmap: |
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pcim_iounmap(pci, reg); |
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return 0; |
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} |
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static const struct property_entry dwc3_pci_intel_properties[] = { |
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PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), |
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PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), |
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{} |
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}; |
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static const struct property_entry dwc3_pci_mrfld_properties[] = { |
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PROPERTY_ENTRY_STRING("dr_mode", "otg"), |
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PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), |
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PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), |
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PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), |
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PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"), |
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PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), |
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{} |
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}; |
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static const struct property_entry dwc3_pci_amd_properties[] = { |
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PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), |
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PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), |
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PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), |
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PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), |
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PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), |
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PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), |
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PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), |
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PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), |
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PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), |
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PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), |
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PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), |
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/* FIXME these quirks should be removed when AMD NL tapes out */ |
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PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), |
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PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), |
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PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), |
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PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), |
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{} |
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}; |
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static const struct software_node dwc3_pci_intel_swnode = { |
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.properties = dwc3_pci_intel_properties, |
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}; |
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static const struct software_node dwc3_pci_intel_mrfld_swnode = { |
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.properties = dwc3_pci_mrfld_properties, |
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}; |
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static const struct software_node dwc3_pci_amd_swnode = { |
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.properties = dwc3_pci_amd_properties, |
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}; |
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static int dwc3_pci_quirks(struct dwc3_pci *dwc) |
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{ |
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struct pci_dev *pdev = dwc->pci; |
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if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
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if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || |
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pdev->device == PCI_DEVICE_ID_INTEL_BXT_M || |
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pdev->device == PCI_DEVICE_ID_INTEL_EHLLP) { |
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guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); |
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dwc->has_dsm_for_pm = true; |
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} |
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if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { |
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struct gpio_desc *gpio; |
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int ret; |
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/* On BYT the FW does not always enable the refclock */ |
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ret = dwc3_byt_enable_ulpi_refclock(pdev); |
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if (ret) |
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return ret; |
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ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, |
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acpi_dwc3_byt_gpios); |
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if (ret) |
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dev_dbg(&pdev->dev, "failed to add mapping table\n"); |
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/* |
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* A lot of BYT devices lack ACPI resource entries for |
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* the GPIOs, add a fallback mapping to the reference |
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* design GPIOs which all boards seem to use. |
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*/ |
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gpiod_add_lookup_table(&platform_bytcr_gpios); |
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/* |
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* These GPIOs will turn on the USB2 PHY. Note that we have to |
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* put the gpio descriptors again here because the phy driver |
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* might want to grab them, too. |
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*/ |
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gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); |
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if (IS_ERR(gpio)) |
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return PTR_ERR(gpio); |
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gpiod_set_value_cansleep(gpio, 1); |
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gpiod_put(gpio); |
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gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); |
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if (IS_ERR(gpio)) |
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return PTR_ERR(gpio); |
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if (gpio) { |
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gpiod_set_value_cansleep(gpio, 1); |
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gpiod_put(gpio); |
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usleep_range(10000, 11000); |
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} |
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} |
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} |
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return 0; |
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} |
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#ifdef CONFIG_PM |
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static void dwc3_pci_resume_work(struct work_struct *work) |
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{ |
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struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); |
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struct platform_device *dwc3 = dwc->dwc3; |
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int ret; |
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ret = pm_runtime_get_sync(&dwc3->dev); |
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if (ret) { |
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pm_runtime_put_sync_autosuspend(&dwc3->dev); |
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return; |
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} |
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pm_runtime_mark_last_busy(&dwc3->dev); |
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pm_runtime_put_sync_autosuspend(&dwc3->dev); |
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} |
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#endif |
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static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) |
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{ |
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struct dwc3_pci *dwc; |
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struct resource res[2]; |
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int ret; |
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struct device *dev = &pci->dev; |
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ret = pcim_enable_device(pci); |
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if (ret) { |
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dev_err(dev, "failed to enable pci device\n"); |
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return -ENODEV; |
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} |
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pci_set_master(pci); |
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dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); |
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if (!dwc) |
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return -ENOMEM; |
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dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); |
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if (!dwc->dwc3) |
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return -ENOMEM; |
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memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); |
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res[0].start = pci_resource_start(pci, 0); |
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res[0].end = pci_resource_end(pci, 0); |
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res[0].name = "dwc_usb3"; |
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res[0].flags = IORESOURCE_MEM; |
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res[1].start = pci->irq; |
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res[1].name = "dwc_usb3"; |
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res[1].flags = IORESOURCE_IRQ; |
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ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); |
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if (ret) { |
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dev_err(dev, "couldn't add resources to dwc3 device\n"); |
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goto err; |
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} |
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dwc->pci = pci; |
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dwc->dwc3->dev.parent = dev; |
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ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); |
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ret = device_add_software_node(&dwc->dwc3->dev, (void *)id->driver_data); |
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if (ret < 0) |
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goto err; |
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ret = dwc3_pci_quirks(dwc); |
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if (ret) |
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goto err; |
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ret = platform_device_add(dwc->dwc3); |
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if (ret) { |
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dev_err(dev, "failed to register dwc3 device\n"); |
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goto err; |
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} |
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device_init_wakeup(dev, true); |
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pci_set_drvdata(pci, dwc); |
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pm_runtime_put(dev); |
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#ifdef CONFIG_PM |
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INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); |
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#endif |
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return 0; |
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err: |
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device_remove_software_node(&dwc->dwc3->dev); |
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platform_device_put(dwc->dwc3); |
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return ret; |
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} |
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static void dwc3_pci_remove(struct pci_dev *pci) |
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{ |
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struct dwc3_pci *dwc = pci_get_drvdata(pci); |
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struct pci_dev *pdev = dwc->pci; |
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if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) |
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gpiod_remove_lookup_table(&platform_bytcr_gpios); |
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#ifdef CONFIG_PM |
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cancel_work_sync(&dwc->wakeup_work); |
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#endif |
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device_init_wakeup(&pci->dev, false); |
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pm_runtime_get(&pci->dev); |
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device_remove_software_node(&dwc->dwc3->dev); |
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platform_device_unregister(dwc->dwc3); |
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} |
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static const struct pci_device_id dwc3_pci_id_table[] = { |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD), |
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(kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLM), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL), |
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(kernel_ulong_t) &dwc3_pci_intel_swnode, }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), |
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(kernel_ulong_t) &dwc3_pci_amd_swnode, }, |
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{ } /* Terminating Entry */ |
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}; |
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MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); |
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#if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) |
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static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) |
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{ |
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union acpi_object *obj; |
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union acpi_object tmp; |
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union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); |
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if (!dwc->has_dsm_for_pm) |
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return 0; |
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tmp.type = ACPI_TYPE_INTEGER; |
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tmp.integer.value = param; |
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obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, |
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1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); |
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if (!obj) { |
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dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); |
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return -EIO; |
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} |
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ACPI_FREE(obj); |
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return 0; |
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} |
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#endif /* CONFIG_PM || CONFIG_PM_SLEEP */ |
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#ifdef CONFIG_PM |
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static int dwc3_pci_runtime_suspend(struct device *dev) |
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{ |
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struct dwc3_pci *dwc = dev_get_drvdata(dev); |
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if (device_can_wakeup(dev)) |
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return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); |
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return -EBUSY; |
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} |
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static int dwc3_pci_runtime_resume(struct device *dev) |
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{ |
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struct dwc3_pci *dwc = dev_get_drvdata(dev); |
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int ret; |
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ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); |
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if (ret) |
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return ret; |
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queue_work(pm_wq, &dwc->wakeup_work); |
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return 0; |
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} |
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#endif /* CONFIG_PM */ |
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#ifdef CONFIG_PM_SLEEP |
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static int dwc3_pci_suspend(struct device *dev) |
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{ |
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struct dwc3_pci *dwc = dev_get_drvdata(dev); |
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return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); |
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} |
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static int dwc3_pci_resume(struct device *dev) |
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{ |
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struct dwc3_pci *dwc = dev_get_drvdata(dev); |
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return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); |
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} |
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#endif /* CONFIG_PM_SLEEP */ |
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static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { |
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SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) |
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SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, |
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NULL) |
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}; |
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static struct pci_driver dwc3_pci_driver = { |
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.name = "dwc3-pci", |
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.id_table = dwc3_pci_id_table, |
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.probe = dwc3_pci_probe, |
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.remove = dwc3_pci_remove, |
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.driver = { |
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.pm = &dwc3_pci_dev_pm_ops, |
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} |
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}; |
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MODULE_AUTHOR("Felipe Balbi <[email protected]>"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); |
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module_pci_driver(dwc3_pci_driver);
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