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797 lines
18 KiB
797 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Actions Semi Owl family serial console |
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* |
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* Copyright 2013 Actions Semi Inc. |
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* Author: Actions Semi, Inc. |
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* |
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* Copyright (c) 2016-2017 Andreas Färber |
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*/ |
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#include <linux/clk.h> |
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#include <linux/console.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/serial.h> |
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#include <linux/serial_core.h> |
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#include <linux/tty.h> |
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#include <linux/tty_flip.h> |
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#define OWL_UART_PORT_NUM 7 |
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#define OWL_UART_DEV_NAME "ttyOWL" |
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#define OWL_UART_CTL 0x000 |
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#define OWL_UART_RXDAT 0x004 |
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#define OWL_UART_TXDAT 0x008 |
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#define OWL_UART_STAT 0x00c |
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#define OWL_UART_CTL_DWLS_MASK GENMASK(1, 0) |
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#define OWL_UART_CTL_DWLS_5BITS (0x0 << 0) |
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#define OWL_UART_CTL_DWLS_6BITS (0x1 << 0) |
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#define OWL_UART_CTL_DWLS_7BITS (0x2 << 0) |
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#define OWL_UART_CTL_DWLS_8BITS (0x3 << 0) |
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#define OWL_UART_CTL_STPS_2BITS BIT(2) |
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#define OWL_UART_CTL_PRS_MASK GENMASK(6, 4) |
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#define OWL_UART_CTL_PRS_NONE (0x0 << 4) |
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#define OWL_UART_CTL_PRS_ODD (0x4 << 4) |
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#define OWL_UART_CTL_PRS_MARK (0x5 << 4) |
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#define OWL_UART_CTL_PRS_EVEN (0x6 << 4) |
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#define OWL_UART_CTL_PRS_SPACE (0x7 << 4) |
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#define OWL_UART_CTL_AFE BIT(12) |
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#define OWL_UART_CTL_TRFS_TX BIT(14) |
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#define OWL_UART_CTL_EN BIT(15) |
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#define OWL_UART_CTL_RXDE BIT(16) |
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#define OWL_UART_CTL_TXDE BIT(17) |
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#define OWL_UART_CTL_RXIE BIT(18) |
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#define OWL_UART_CTL_TXIE BIT(19) |
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#define OWL_UART_CTL_LBEN BIT(20) |
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#define OWL_UART_STAT_RIP BIT(0) |
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#define OWL_UART_STAT_TIP BIT(1) |
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#define OWL_UART_STAT_RXER BIT(2) |
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#define OWL_UART_STAT_TFER BIT(3) |
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#define OWL_UART_STAT_RXST BIT(4) |
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#define OWL_UART_STAT_RFEM BIT(5) |
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#define OWL_UART_STAT_TFFU BIT(6) |
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#define OWL_UART_STAT_CTSS BIT(7) |
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#define OWL_UART_STAT_RTSS BIT(8) |
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#define OWL_UART_STAT_TFES BIT(10) |
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#define OWL_UART_STAT_TRFL_MASK GENMASK(16, 11) |
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#define OWL_UART_STAT_UTBB BIT(17) |
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#define OWL_UART_POLL_USEC 5 |
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#define OWL_UART_TIMEOUT_USEC 10000 |
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static struct uart_driver owl_uart_driver; |
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struct owl_uart_info { |
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unsigned int tx_fifosize; |
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}; |
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struct owl_uart_port { |
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struct uart_port port; |
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struct clk *clk; |
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}; |
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#define to_owl_uart_port(prt) container_of(prt, struct owl_uart_port, prt) |
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static struct owl_uart_port *owl_uart_ports[OWL_UART_PORT_NUM]; |
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static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off) |
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{ |
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writel(val, port->membase + off); |
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} |
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static inline u32 owl_uart_read(struct uart_port *port, unsigned int off) |
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{ |
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return readl(port->membase + off); |
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} |
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static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
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{ |
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u32 ctl; |
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ctl = owl_uart_read(port, OWL_UART_CTL); |
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if (mctrl & TIOCM_LOOP) |
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ctl |= OWL_UART_CTL_LBEN; |
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else |
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ctl &= ~OWL_UART_CTL_LBEN; |
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owl_uart_write(port, ctl, OWL_UART_CTL); |
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} |
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static unsigned int owl_uart_get_mctrl(struct uart_port *port) |
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{ |
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unsigned int mctrl = TIOCM_CAR | TIOCM_DSR; |
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u32 stat, ctl; |
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ctl = owl_uart_read(port, OWL_UART_CTL); |
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stat = owl_uart_read(port, OWL_UART_STAT); |
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if (stat & OWL_UART_STAT_RTSS) |
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mctrl |= TIOCM_RTS; |
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if ((stat & OWL_UART_STAT_CTSS) || !(ctl & OWL_UART_CTL_AFE)) |
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mctrl |= TIOCM_CTS; |
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return mctrl; |
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} |
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static unsigned int owl_uart_tx_empty(struct uart_port *port) |
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{ |
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unsigned long flags; |
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u32 val; |
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unsigned int ret; |
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spin_lock_irqsave(&port->lock, flags); |
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val = owl_uart_read(port, OWL_UART_STAT); |
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ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0; |
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spin_unlock_irqrestore(&port->lock, flags); |
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return ret; |
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} |
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static void owl_uart_stop_rx(struct uart_port *port) |
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{ |
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u32 val; |
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val = owl_uart_read(port, OWL_UART_CTL); |
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val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE); |
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owl_uart_write(port, val, OWL_UART_CTL); |
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val = owl_uart_read(port, OWL_UART_STAT); |
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val |= OWL_UART_STAT_RIP; |
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owl_uart_write(port, val, OWL_UART_STAT); |
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} |
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static void owl_uart_stop_tx(struct uart_port *port) |
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{ |
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u32 val; |
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val = owl_uart_read(port, OWL_UART_CTL); |
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val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE); |
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owl_uart_write(port, val, OWL_UART_CTL); |
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val = owl_uart_read(port, OWL_UART_STAT); |
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val |= OWL_UART_STAT_TIP; |
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owl_uart_write(port, val, OWL_UART_STAT); |
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} |
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static void owl_uart_start_tx(struct uart_port *port) |
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{ |
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u32 val; |
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if (uart_tx_stopped(port)) { |
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owl_uart_stop_tx(port); |
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return; |
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} |
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val = owl_uart_read(port, OWL_UART_STAT); |
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val |= OWL_UART_STAT_TIP; |
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owl_uart_write(port, val, OWL_UART_STAT); |
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val = owl_uart_read(port, OWL_UART_CTL); |
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val |= OWL_UART_CTL_TXIE; |
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owl_uart_write(port, val, OWL_UART_CTL); |
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} |
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static void owl_uart_send_chars(struct uart_port *port) |
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{ |
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struct circ_buf *xmit = &port->state->xmit; |
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unsigned int ch; |
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if (uart_tx_stopped(port)) |
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return; |
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if (port->x_char) { |
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while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) |
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cpu_relax(); |
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owl_uart_write(port, port->x_char, OWL_UART_TXDAT); |
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port->icount.tx++; |
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port->x_char = 0; |
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} |
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while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) { |
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if (uart_circ_empty(xmit)) |
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break; |
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ch = xmit->buf[xmit->tail]; |
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owl_uart_write(port, ch, OWL_UART_TXDAT); |
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xmit->tail = (xmit->tail + 1) & (SERIAL_XMIT_SIZE - 1); |
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port->icount.tx++; |
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} |
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
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uart_write_wakeup(port); |
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if (uart_circ_empty(xmit)) |
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owl_uart_stop_tx(port); |
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} |
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static void owl_uart_receive_chars(struct uart_port *port) |
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{ |
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u32 stat, val; |
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val = owl_uart_read(port, OWL_UART_CTL); |
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val &= ~OWL_UART_CTL_TRFS_TX; |
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owl_uart_write(port, val, OWL_UART_CTL); |
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stat = owl_uart_read(port, OWL_UART_STAT); |
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while (!(stat & OWL_UART_STAT_RFEM)) { |
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char flag = TTY_NORMAL; |
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if (stat & OWL_UART_STAT_RXER) |
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port->icount.overrun++; |
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if (stat & OWL_UART_STAT_RXST) { |
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/* We are not able to distinguish the error type. */ |
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port->icount.brk++; |
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port->icount.frame++; |
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stat &= port->read_status_mask; |
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if (stat & OWL_UART_STAT_RXST) |
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flag = TTY_PARITY; |
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} else |
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port->icount.rx++; |
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val = owl_uart_read(port, OWL_UART_RXDAT); |
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val &= 0xff; |
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if ((stat & port->ignore_status_mask) == 0) |
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tty_insert_flip_char(&port->state->port, val, flag); |
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stat = owl_uart_read(port, OWL_UART_STAT); |
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} |
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spin_unlock(&port->lock); |
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tty_flip_buffer_push(&port->state->port); |
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spin_lock(&port->lock); |
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} |
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static irqreturn_t owl_uart_irq(int irq, void *dev_id) |
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{ |
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struct uart_port *port = dev_id; |
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unsigned long flags; |
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u32 stat; |
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spin_lock_irqsave(&port->lock, flags); |
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stat = owl_uart_read(port, OWL_UART_STAT); |
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if (stat & OWL_UART_STAT_RIP) |
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owl_uart_receive_chars(port); |
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if (stat & OWL_UART_STAT_TIP) |
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owl_uart_send_chars(port); |
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stat = owl_uart_read(port, OWL_UART_STAT); |
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stat |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP; |
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owl_uart_write(port, stat, OWL_UART_STAT); |
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spin_unlock_irqrestore(&port->lock, flags); |
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return IRQ_HANDLED; |
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} |
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static void owl_uart_shutdown(struct uart_port *port) |
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{ |
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u32 val; |
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unsigned long flags; |
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spin_lock_irqsave(&port->lock, flags); |
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val = owl_uart_read(port, OWL_UART_CTL); |
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val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_RXIE |
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| OWL_UART_CTL_TXDE | OWL_UART_CTL_RXDE | OWL_UART_CTL_EN); |
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owl_uart_write(port, val, OWL_UART_CTL); |
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spin_unlock_irqrestore(&port->lock, flags); |
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free_irq(port->irq, port); |
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} |
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static int owl_uart_startup(struct uart_port *port) |
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{ |
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u32 val; |
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unsigned long flags; |
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int ret; |
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ret = request_irq(port->irq, owl_uart_irq, IRQF_TRIGGER_HIGH, |
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"owl-uart", port); |
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if (ret) |
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return ret; |
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spin_lock_irqsave(&port->lock, flags); |
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val = owl_uart_read(port, OWL_UART_STAT); |
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val |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP |
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| OWL_UART_STAT_RXER | OWL_UART_STAT_TFER | OWL_UART_STAT_RXST; |
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owl_uart_write(port, val, OWL_UART_STAT); |
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val = owl_uart_read(port, OWL_UART_CTL); |
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val |= OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE; |
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val |= OWL_UART_CTL_EN; |
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owl_uart_write(port, val, OWL_UART_CTL); |
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spin_unlock_irqrestore(&port->lock, flags); |
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return 0; |
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} |
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static void owl_uart_change_baudrate(struct owl_uart_port *owl_port, |
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unsigned long baud) |
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{ |
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clk_set_rate(owl_port->clk, baud * 8); |
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} |
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static void owl_uart_set_termios(struct uart_port *port, |
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struct ktermios *termios, |
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struct ktermios *old) |
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{ |
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struct owl_uart_port *owl_port = to_owl_uart_port(port); |
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unsigned int baud; |
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u32 ctl; |
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unsigned long flags; |
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spin_lock_irqsave(&port->lock, flags); |
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ctl = owl_uart_read(port, OWL_UART_CTL); |
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ctl &= ~OWL_UART_CTL_DWLS_MASK; |
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switch (termios->c_cflag & CSIZE) { |
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case CS5: |
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ctl |= OWL_UART_CTL_DWLS_5BITS; |
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break; |
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case CS6: |
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ctl |= OWL_UART_CTL_DWLS_6BITS; |
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break; |
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case CS7: |
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ctl |= OWL_UART_CTL_DWLS_7BITS; |
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break; |
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case CS8: |
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default: |
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ctl |= OWL_UART_CTL_DWLS_8BITS; |
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break; |
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} |
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if (termios->c_cflag & CSTOPB) |
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ctl |= OWL_UART_CTL_STPS_2BITS; |
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else |
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ctl &= ~OWL_UART_CTL_STPS_2BITS; |
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ctl &= ~OWL_UART_CTL_PRS_MASK; |
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if (termios->c_cflag & PARENB) { |
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if (termios->c_cflag & CMSPAR) { |
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if (termios->c_cflag & PARODD) |
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ctl |= OWL_UART_CTL_PRS_MARK; |
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else |
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ctl |= OWL_UART_CTL_PRS_SPACE; |
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} else if (termios->c_cflag & PARODD) |
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ctl |= OWL_UART_CTL_PRS_ODD; |
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else |
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ctl |= OWL_UART_CTL_PRS_EVEN; |
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} else |
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ctl |= OWL_UART_CTL_PRS_NONE; |
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if (termios->c_cflag & CRTSCTS) |
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ctl |= OWL_UART_CTL_AFE; |
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else |
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ctl &= ~OWL_UART_CTL_AFE; |
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owl_uart_write(port, ctl, OWL_UART_CTL); |
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baud = uart_get_baud_rate(port, termios, old, 9600, 3200000); |
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owl_uart_change_baudrate(owl_port, baud); |
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/* Don't rewrite B0 */ |
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if (tty_termios_baud_rate(termios)) |
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tty_termios_encode_baud_rate(termios, baud, baud); |
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port->read_status_mask |= OWL_UART_STAT_RXER; |
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if (termios->c_iflag & INPCK) |
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port->read_status_mask |= OWL_UART_STAT_RXST; |
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uart_update_timeout(port, termios->c_cflag, baud); |
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spin_unlock_irqrestore(&port->lock, flags); |
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} |
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static void owl_uart_release_port(struct uart_port *port) |
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{ |
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struct platform_device *pdev = to_platform_device(port->dev); |
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struct resource *res; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!res) |
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return; |
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if (port->flags & UPF_IOREMAP) { |
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devm_release_mem_region(port->dev, port->mapbase, |
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resource_size(res)); |
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devm_iounmap(port->dev, port->membase); |
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port->membase = NULL; |
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} |
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} |
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static int owl_uart_request_port(struct uart_port *port) |
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{ |
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struct platform_device *pdev = to_platform_device(port->dev); |
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struct resource *res; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!res) |
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return -ENXIO; |
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if (!devm_request_mem_region(port->dev, port->mapbase, |
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resource_size(res), dev_name(port->dev))) |
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return -EBUSY; |
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if (port->flags & UPF_IOREMAP) { |
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port->membase = devm_ioremap(port->dev, port->mapbase, |
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resource_size(res)); |
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if (!port->membase) |
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return -EBUSY; |
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} |
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return 0; |
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} |
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static const char *owl_uart_type(struct uart_port *port) |
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{ |
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return (port->type == PORT_OWL) ? "owl-uart" : NULL; |
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} |
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static int owl_uart_verify_port(struct uart_port *port, |
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struct serial_struct *ser) |
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{ |
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if (port->type != PORT_OWL) |
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return -EINVAL; |
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if (port->irq != ser->irq) |
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return -EINVAL; |
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return 0; |
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} |
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static void owl_uart_config_port(struct uart_port *port, int flags) |
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{ |
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if (flags & UART_CONFIG_TYPE) { |
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port->type = PORT_OWL; |
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owl_uart_request_port(port); |
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} |
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} |
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#ifdef CONFIG_CONSOLE_POLL |
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static int owl_uart_poll_get_char(struct uart_port *port) |
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{ |
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if (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_RFEM) |
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return NO_POLL_CHAR; |
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return owl_uart_read(port, OWL_UART_RXDAT); |
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} |
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static void owl_uart_poll_put_char(struct uart_port *port, unsigned char ch) |
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{ |
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u32 reg; |
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int ret; |
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/* Wait while FIFO is full or timeout */ |
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ret = readl_poll_timeout_atomic(port->membase + OWL_UART_STAT, reg, |
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!(reg & OWL_UART_STAT_TFFU), |
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OWL_UART_POLL_USEC, |
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OWL_UART_TIMEOUT_USEC); |
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if (ret == -ETIMEDOUT) { |
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dev_err(port->dev, "Timeout waiting while UART TX FULL\n"); |
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return; |
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} |
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owl_uart_write(port, ch, OWL_UART_TXDAT); |
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} |
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#endif /* CONFIG_CONSOLE_POLL */ |
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static const struct uart_ops owl_uart_ops = { |
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.set_mctrl = owl_uart_set_mctrl, |
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.get_mctrl = owl_uart_get_mctrl, |
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.tx_empty = owl_uart_tx_empty, |
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.start_tx = owl_uart_start_tx, |
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.stop_rx = owl_uart_stop_rx, |
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.stop_tx = owl_uart_stop_tx, |
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.startup = owl_uart_startup, |
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.shutdown = owl_uart_shutdown, |
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.set_termios = owl_uart_set_termios, |
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.type = owl_uart_type, |
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.config_port = owl_uart_config_port, |
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.request_port = owl_uart_request_port, |
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.release_port = owl_uart_release_port, |
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.verify_port = owl_uart_verify_port, |
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#ifdef CONFIG_CONSOLE_POLL |
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.poll_get_char = owl_uart_poll_get_char, |
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.poll_put_char = owl_uart_poll_put_char, |
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#endif |
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}; |
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#ifdef CONFIG_SERIAL_OWL_CONSOLE |
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static void owl_console_putchar(struct uart_port *port, int ch) |
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{ |
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if (!port->membase) |
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return; |
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while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU) |
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cpu_relax(); |
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owl_uart_write(port, ch, OWL_UART_TXDAT); |
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} |
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static void owl_uart_port_write(struct uart_port *port, const char *s, |
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u_int count) |
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{ |
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u32 old_ctl, val; |
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unsigned long flags; |
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int locked; |
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local_irq_save(flags); |
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if (port->sysrq) |
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locked = 0; |
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else if (oops_in_progress) |
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locked = spin_trylock(&port->lock); |
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else { |
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spin_lock(&port->lock); |
|
locked = 1; |
|
} |
|
|
|
old_ctl = owl_uart_read(port, OWL_UART_CTL); |
|
val = old_ctl | OWL_UART_CTL_TRFS_TX; |
|
/* disable IRQ */ |
|
val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE); |
|
owl_uart_write(port, val, OWL_UART_CTL); |
|
|
|
uart_console_write(port, s, count, owl_console_putchar); |
|
|
|
/* wait until all contents have been sent out */ |
|
while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK) |
|
cpu_relax(); |
|
|
|
/* clear IRQ pending */ |
|
val = owl_uart_read(port, OWL_UART_STAT); |
|
val |= OWL_UART_STAT_TIP | OWL_UART_STAT_RIP; |
|
owl_uart_write(port, val, OWL_UART_STAT); |
|
|
|
owl_uart_write(port, old_ctl, OWL_UART_CTL); |
|
|
|
if (locked) |
|
spin_unlock(&port->lock); |
|
|
|
local_irq_restore(flags); |
|
} |
|
|
|
static void owl_uart_console_write(struct console *co, const char *s, |
|
u_int count) |
|
{ |
|
struct owl_uart_port *owl_port; |
|
|
|
owl_port = owl_uart_ports[co->index]; |
|
if (!owl_port) |
|
return; |
|
|
|
owl_uart_port_write(&owl_port->port, s, count); |
|
} |
|
|
|
static int owl_uart_console_setup(struct console *co, char *options) |
|
{ |
|
struct owl_uart_port *owl_port; |
|
int baud = 115200; |
|
int bits = 8; |
|
int parity = 'n'; |
|
int flow = 'n'; |
|
|
|
if (co->index < 0 || co->index >= OWL_UART_PORT_NUM) |
|
return -EINVAL; |
|
|
|
owl_port = owl_uart_ports[co->index]; |
|
if (!owl_port || !owl_port->port.membase) |
|
return -ENODEV; |
|
|
|
if (options) |
|
uart_parse_options(options, &baud, &parity, &bits, &flow); |
|
|
|
return uart_set_options(&owl_port->port, co, baud, parity, bits, flow); |
|
} |
|
|
|
static struct console owl_uart_console = { |
|
.name = OWL_UART_DEV_NAME, |
|
.write = owl_uart_console_write, |
|
.device = uart_console_device, |
|
.setup = owl_uart_console_setup, |
|
.flags = CON_PRINTBUFFER, |
|
.index = -1, |
|
.data = &owl_uart_driver, |
|
}; |
|
|
|
static int __init owl_uart_console_init(void) |
|
{ |
|
register_console(&owl_uart_console); |
|
|
|
return 0; |
|
} |
|
console_initcall(owl_uart_console_init); |
|
|
|
static void owl_uart_early_console_write(struct console *co, |
|
const char *s, |
|
u_int count) |
|
{ |
|
struct earlycon_device *dev = co->data; |
|
|
|
owl_uart_port_write(&dev->port, s, count); |
|
} |
|
|
|
static int __init |
|
owl_uart_early_console_setup(struct earlycon_device *device, const char *opt) |
|
{ |
|
if (!device->port.membase) |
|
return -ENODEV; |
|
|
|
device->con->write = owl_uart_early_console_write; |
|
|
|
return 0; |
|
} |
|
OF_EARLYCON_DECLARE(owl, "actions,owl-uart", |
|
owl_uart_early_console_setup); |
|
|
|
#define OWL_UART_CONSOLE (&owl_uart_console) |
|
#else |
|
#define OWL_UART_CONSOLE NULL |
|
#endif |
|
|
|
static struct uart_driver owl_uart_driver = { |
|
.owner = THIS_MODULE, |
|
.driver_name = "owl-uart", |
|
.dev_name = OWL_UART_DEV_NAME, |
|
.nr = OWL_UART_PORT_NUM, |
|
.cons = OWL_UART_CONSOLE, |
|
}; |
|
|
|
static const struct owl_uart_info owl_s500_info = { |
|
.tx_fifosize = 16, |
|
}; |
|
|
|
static const struct owl_uart_info owl_s900_info = { |
|
.tx_fifosize = 32, |
|
}; |
|
|
|
static const struct of_device_id owl_uart_dt_matches[] = { |
|
{ .compatible = "actions,s500-uart", .data = &owl_s500_info }, |
|
{ .compatible = "actions,s900-uart", .data = &owl_s900_info }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, owl_uart_dt_matches); |
|
|
|
static int owl_uart_probe(struct platform_device *pdev) |
|
{ |
|
const struct of_device_id *match; |
|
const struct owl_uart_info *info = NULL; |
|
struct resource *res_mem; |
|
struct owl_uart_port *owl_port; |
|
int ret, irq; |
|
|
|
if (pdev->dev.of_node) { |
|
pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); |
|
match = of_match_node(owl_uart_dt_matches, pdev->dev.of_node); |
|
if (match) |
|
info = match->data; |
|
} |
|
|
|
if (pdev->id < 0 || pdev->id >= OWL_UART_PORT_NUM) { |
|
dev_err(&pdev->dev, "id %d out of range\n", pdev->id); |
|
return -EINVAL; |
|
} |
|
|
|
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
if (!res_mem) { |
|
dev_err(&pdev->dev, "could not get mem\n"); |
|
return -ENODEV; |
|
} |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) |
|
return irq; |
|
|
|
if (owl_uart_ports[pdev->id]) { |
|
dev_err(&pdev->dev, "port %d already allocated\n", pdev->id); |
|
return -EBUSY; |
|
} |
|
|
|
owl_port = devm_kzalloc(&pdev->dev, sizeof(*owl_port), GFP_KERNEL); |
|
if (!owl_port) |
|
return -ENOMEM; |
|
|
|
owl_port->clk = devm_clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(owl_port->clk)) { |
|
dev_err(&pdev->dev, "could not get clk\n"); |
|
return PTR_ERR(owl_port->clk); |
|
} |
|
|
|
ret = clk_prepare_enable(owl_port->clk); |
|
if (ret) { |
|
dev_err(&pdev->dev, "could not enable clk\n"); |
|
return ret; |
|
} |
|
|
|
owl_port->port.dev = &pdev->dev; |
|
owl_port->port.line = pdev->id; |
|
owl_port->port.type = PORT_OWL; |
|
owl_port->port.iotype = UPIO_MEM; |
|
owl_port->port.mapbase = res_mem->start; |
|
owl_port->port.irq = irq; |
|
owl_port->port.uartclk = clk_get_rate(owl_port->clk); |
|
if (owl_port->port.uartclk == 0) { |
|
dev_err(&pdev->dev, "clock rate is zero\n"); |
|
return -EINVAL; |
|
} |
|
owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY; |
|
owl_port->port.x_char = 0; |
|
owl_port->port.fifosize = (info) ? info->tx_fifosize : 16; |
|
owl_port->port.ops = &owl_uart_ops; |
|
|
|
owl_uart_ports[pdev->id] = owl_port; |
|
platform_set_drvdata(pdev, owl_port); |
|
|
|
ret = uart_add_one_port(&owl_uart_driver, &owl_port->port); |
|
if (ret) |
|
owl_uart_ports[pdev->id] = NULL; |
|
|
|
return ret; |
|
} |
|
|
|
static int owl_uart_remove(struct platform_device *pdev) |
|
{ |
|
struct owl_uart_port *owl_port = platform_get_drvdata(pdev); |
|
|
|
uart_remove_one_port(&owl_uart_driver, &owl_port->port); |
|
owl_uart_ports[pdev->id] = NULL; |
|
clk_disable_unprepare(owl_port->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver owl_uart_platform_driver = { |
|
.probe = owl_uart_probe, |
|
.remove = owl_uart_remove, |
|
.driver = { |
|
.name = "owl-uart", |
|
.of_match_table = owl_uart_dt_matches, |
|
}, |
|
}; |
|
|
|
static int __init owl_uart_init(void) |
|
{ |
|
int ret; |
|
|
|
ret = uart_register_driver(&owl_uart_driver); |
|
if (ret) |
|
return ret; |
|
|
|
ret = platform_driver_register(&owl_uart_platform_driver); |
|
if (ret) |
|
uart_unregister_driver(&owl_uart_driver); |
|
|
|
return ret; |
|
} |
|
|
|
static void __exit owl_uart_exit(void) |
|
{ |
|
platform_driver_unregister(&owl_uart_platform_driver); |
|
uart_unregister_driver(&owl_uart_driver); |
|
} |
|
|
|
module_init(owl_uart_init); |
|
module_exit(owl_uart_exit); |
|
|
|
MODULE_LICENSE("GPL");
|
|
|