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764 lines
19 KiB
764 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* High Speed Serial Ports on NXP LPC32xx SoC |
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* |
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* Authors: Kevin Wells <[email protected]> |
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* Roland Stigge <[email protected]> |
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* |
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* Copyright (C) 2010 NXP Semiconductors |
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* Copyright (C) 2012 Roland Stigge |
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*/ |
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|
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#include <linux/module.h> |
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#include <linux/ioport.h> |
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#include <linux/init.h> |
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#include <linux/console.h> |
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#include <linux/sysrq.h> |
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#include <linux/tty.h> |
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#include <linux/tty_flip.h> |
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#include <linux/serial_core.h> |
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#include <linux/serial.h> |
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#include <linux/platform_device.h> |
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#include <linux/delay.h> |
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#include <linux/nmi.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/of.h> |
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#include <linux/sizes.h> |
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#include <linux/soc/nxp/lpc32xx-misc.h> |
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|
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/* |
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* High Speed UART register offsets |
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*/ |
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#define LPC32XX_HSUART_FIFO(x) ((x) + 0x00) |
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#define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04) |
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#define LPC32XX_HSUART_IIR(x) ((x) + 0x08) |
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#define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C) |
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#define LPC32XX_HSUART_RATE(x) ((x) + 0x10) |
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#define LPC32XX_HSU_BREAK_DATA (1 << 10) |
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#define LPC32XX_HSU_ERROR_DATA (1 << 9) |
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#define LPC32XX_HSU_RX_EMPTY (1 << 8) |
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#define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF) |
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#define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF) |
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#define LPC32XX_HSU_TX_INT_SET (1 << 6) |
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#define LPC32XX_HSU_RX_OE_INT (1 << 5) |
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#define LPC32XX_HSU_BRK_INT (1 << 4) |
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#define LPC32XX_HSU_FE_INT (1 << 3) |
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#define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2) |
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#define LPC32XX_HSU_RX_TRIG_INT (1 << 1) |
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#define LPC32XX_HSU_TX_INT (1 << 0) |
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|
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#define LPC32XX_HSU_HRTS_INV (1 << 21) |
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#define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19) |
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#define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19) |
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#define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19) |
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#define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19) |
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#define LPC32XX_HSU_HRTS_EN (1 << 18) |
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#define LPC32XX_HSU_TMO_DISABLED (0x0 << 16) |
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#define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16) |
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#define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16) |
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#define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16) |
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#define LPC32XX_HSU_HCTS_INV (1 << 15) |
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#define LPC32XX_HSU_HCTS_EN (1 << 14) |
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#define LPC32XX_HSU_OFFSET(n) ((n) << 9) |
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#define LPC32XX_HSU_BREAK (1 << 8) |
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#define LPC32XX_HSU_ERR_INT_EN (1 << 7) |
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#define LPC32XX_HSU_RX_INT_EN (1 << 6) |
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#define LPC32XX_HSU_TX_INT_EN (1 << 5) |
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#define LPC32XX_HSU_RX_TL1B (0x0 << 2) |
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#define LPC32XX_HSU_RX_TL4B (0x1 << 2) |
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#define LPC32XX_HSU_RX_TL8B (0x2 << 2) |
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#define LPC32XX_HSU_RX_TL16B (0x3 << 2) |
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#define LPC32XX_HSU_RX_TL32B (0x4 << 2) |
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#define LPC32XX_HSU_RX_TL48B (0x5 << 2) |
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#define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0) |
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#define LPC32XX_HSU_TX_TL0B (0x0 << 0) |
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#define LPC32XX_HSU_TX_TL4B (0x1 << 0) |
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#define LPC32XX_HSU_TX_TL8B (0x2 << 0) |
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#define LPC32XX_HSU_TX_TL16B (0x3 << 0) |
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|
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#define LPC32XX_MAIN_OSC_FREQ 13000000 |
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|
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#define MODNAME "lpc32xx_hsuart" |
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|
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struct lpc32xx_hsuart_port { |
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struct uart_port port; |
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}; |
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#define FIFO_READ_LIMIT 128 |
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#define MAX_PORTS 3 |
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#define LPC32XX_TTY_NAME "ttyTX" |
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static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS]; |
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#ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE |
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static void wait_for_xmit_empty(struct uart_port *port) |
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{ |
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unsigned int timeout = 10000; |
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do { |
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if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( |
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port->membase))) == 0) |
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break; |
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if (--timeout == 0) |
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break; |
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udelay(1); |
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} while (1); |
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} |
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static void wait_for_xmit_ready(struct uart_port *port) |
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{ |
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unsigned int timeout = 10000; |
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while (1) { |
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if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( |
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port->membase))) < 32) |
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break; |
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if (--timeout == 0) |
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break; |
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udelay(1); |
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} |
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} |
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static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch) |
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{ |
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wait_for_xmit_ready(port); |
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writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); |
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} |
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static void lpc32xx_hsuart_console_write(struct console *co, const char *s, |
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unsigned int count) |
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{ |
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struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index]; |
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unsigned long flags; |
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int locked = 1; |
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|
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touch_nmi_watchdog(); |
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local_irq_save(flags); |
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if (up->port.sysrq) |
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locked = 0; |
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else if (oops_in_progress) |
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locked = spin_trylock(&up->port.lock); |
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else |
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spin_lock(&up->port.lock); |
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uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar); |
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wait_for_xmit_empty(&up->port); |
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if (locked) |
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spin_unlock(&up->port.lock); |
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local_irq_restore(flags); |
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} |
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static int __init lpc32xx_hsuart_console_setup(struct console *co, |
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char *options) |
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{ |
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struct uart_port *port; |
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int baud = 115200; |
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int bits = 8; |
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int parity = 'n'; |
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int flow = 'n'; |
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if (co->index >= MAX_PORTS) |
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co->index = 0; |
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port = &lpc32xx_hs_ports[co->index].port; |
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if (!port->membase) |
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return -ENODEV; |
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if (options) |
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uart_parse_options(options, &baud, &parity, &bits, &flow); |
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lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ |
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return uart_set_options(port, co, baud, parity, bits, flow); |
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} |
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static struct uart_driver lpc32xx_hsuart_reg; |
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static struct console lpc32xx_hsuart_console = { |
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.name = LPC32XX_TTY_NAME, |
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.write = lpc32xx_hsuart_console_write, |
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.device = uart_console_device, |
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.setup = lpc32xx_hsuart_console_setup, |
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.flags = CON_PRINTBUFFER, |
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.index = -1, |
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.data = &lpc32xx_hsuart_reg, |
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}; |
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static int __init lpc32xx_hsuart_console_init(void) |
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{ |
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register_console(&lpc32xx_hsuart_console); |
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return 0; |
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} |
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console_initcall(lpc32xx_hsuart_console_init); |
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#define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console) |
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#else |
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#define LPC32XX_HSUART_CONSOLE NULL |
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#endif |
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static struct uart_driver lpc32xx_hs_reg = { |
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.owner = THIS_MODULE, |
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.driver_name = MODNAME, |
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.dev_name = LPC32XX_TTY_NAME, |
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.nr = MAX_PORTS, |
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.cons = LPC32XX_HSUART_CONSOLE, |
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}; |
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static int uarts_registered; |
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static unsigned int __serial_get_clock_div(unsigned long uartclk, |
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unsigned long rate) |
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{ |
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u32 div, goodrate, hsu_rate, l_hsu_rate, comprate; |
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u32 rate_diff; |
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/* Find the closest divider to get the desired clock rate */ |
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div = uartclk / rate; |
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goodrate = hsu_rate = (div / 14) - 1; |
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if (hsu_rate != 0) |
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hsu_rate--; |
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/* Tweak divider */ |
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l_hsu_rate = hsu_rate + 3; |
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rate_diff = 0xFFFFFFFF; |
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while (hsu_rate < l_hsu_rate) { |
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comprate = uartclk / ((hsu_rate + 1) * 14); |
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if (abs(comprate - rate) < rate_diff) { |
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goodrate = hsu_rate; |
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rate_diff = abs(comprate - rate); |
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} |
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hsu_rate++; |
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} |
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if (hsu_rate > 0xFF) |
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hsu_rate = 0xFF; |
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return goodrate; |
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} |
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static void __serial_uart_flush(struct uart_port *port) |
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{ |
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int cnt = 0; |
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while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && |
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(cnt++ < FIFO_READ_LIMIT)) |
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readl(LPC32XX_HSUART_FIFO(port->membase)); |
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} |
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static void __serial_lpc32xx_rx(struct uart_port *port) |
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{ |
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struct tty_port *tport = &port->state->port; |
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unsigned int tmp, flag; |
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/* Read data from FIFO and push into terminal */ |
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tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); |
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while (!(tmp & LPC32XX_HSU_RX_EMPTY)) { |
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flag = TTY_NORMAL; |
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port->icount.rx++; |
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if (tmp & LPC32XX_HSU_ERROR_DATA) { |
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/* Framing error */ |
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writel(LPC32XX_HSU_FE_INT, |
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LPC32XX_HSUART_IIR(port->membase)); |
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port->icount.frame++; |
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flag = TTY_FRAME; |
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tty_insert_flip_char(tport, 0, TTY_FRAME); |
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} |
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tty_insert_flip_char(tport, (tmp & 0xFF), flag); |
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tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); |
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} |
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spin_unlock(&port->lock); |
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tty_flip_buffer_push(tport); |
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spin_lock(&port->lock); |
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} |
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static void __serial_lpc32xx_tx(struct uart_port *port) |
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{ |
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struct circ_buf *xmit = &port->state->xmit; |
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unsigned int tmp; |
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if (port->x_char) { |
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writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); |
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port->icount.tx++; |
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port->x_char = 0; |
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return; |
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} |
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if (uart_circ_empty(xmit) || uart_tx_stopped(port)) |
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goto exit_tx; |
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/* Transfer data */ |
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while (LPC32XX_HSU_TX_LEV(readl( |
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LPC32XX_HSUART_LEVEL(port->membase))) < 64) { |
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writel((u32) xmit->buf[xmit->tail], |
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LPC32XX_HSUART_FIFO(port->membase)); |
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
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port->icount.tx++; |
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if (uart_circ_empty(xmit)) |
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break; |
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} |
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
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uart_write_wakeup(port); |
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exit_tx: |
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if (uart_circ_empty(xmit)) { |
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tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); |
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tmp &= ~LPC32XX_HSU_TX_INT_EN; |
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writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); |
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} |
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} |
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static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id) |
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{ |
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struct uart_port *port = dev_id; |
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struct tty_port *tport = &port->state->port; |
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u32 status; |
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spin_lock(&port->lock); |
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|
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/* Read UART status and clear latched interrupts */ |
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status = readl(LPC32XX_HSUART_IIR(port->membase)); |
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if (status & LPC32XX_HSU_BRK_INT) { |
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/* Break received */ |
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writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase)); |
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port->icount.brk++; |
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uart_handle_break(port); |
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} |
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/* Framing error */ |
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if (status & LPC32XX_HSU_FE_INT) |
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writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase)); |
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if (status & LPC32XX_HSU_RX_OE_INT) { |
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/* Receive FIFO overrun */ |
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writel(LPC32XX_HSU_RX_OE_INT, |
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LPC32XX_HSUART_IIR(port->membase)); |
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port->icount.overrun++; |
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tty_insert_flip_char(tport, 0, TTY_OVERRUN); |
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tty_schedule_flip(tport); |
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} |
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/* Data received? */ |
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if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) |
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__serial_lpc32xx_rx(port); |
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|
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/* Transmit data request? */ |
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if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) { |
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writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase)); |
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__serial_lpc32xx_tx(port); |
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} |
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spin_unlock(&port->lock); |
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return IRQ_HANDLED; |
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} |
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/* port->lock is not held. */ |
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static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port) |
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{ |
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unsigned int ret = 0; |
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if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0) |
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ret = TIOCSER_TEMT; |
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return ret; |
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} |
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/* port->lock held by caller. */ |
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static void serial_lpc32xx_set_mctrl(struct uart_port *port, |
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unsigned int mctrl) |
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{ |
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/* No signals are supported on HS UARTs */ |
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} |
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/* port->lock is held by caller and interrupts are disabled. */ |
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static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port) |
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{ |
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/* No signals are supported on HS UARTs */ |
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return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; |
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} |
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/* port->lock held by caller. */ |
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static void serial_lpc32xx_stop_tx(struct uart_port *port) |
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{ |
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u32 tmp; |
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tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); |
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tmp &= ~LPC32XX_HSU_TX_INT_EN; |
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writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); |
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} |
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|
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/* port->lock held by caller. */ |
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static void serial_lpc32xx_start_tx(struct uart_port *port) |
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{ |
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u32 tmp; |
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|
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__serial_lpc32xx_tx(port); |
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tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); |
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tmp |= LPC32XX_HSU_TX_INT_EN; |
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writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); |
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} |
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|
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/* port->lock held by caller. */ |
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static void serial_lpc32xx_stop_rx(struct uart_port *port) |
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{ |
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u32 tmp; |
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|
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tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); |
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tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); |
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writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); |
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|
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writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT | |
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LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase)); |
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} |
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|
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/* port->lock is not held. */ |
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static void serial_lpc32xx_break_ctl(struct uart_port *port, |
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int break_state) |
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{ |
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unsigned long flags; |
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u32 tmp; |
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|
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spin_lock_irqsave(&port->lock, flags); |
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tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); |
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if (break_state != 0) |
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tmp |= LPC32XX_HSU_BREAK; |
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else |
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tmp &= ~LPC32XX_HSU_BREAK; |
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writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); |
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spin_unlock_irqrestore(&port->lock, flags); |
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} |
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|
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/* port->lock is not held. */ |
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static int serial_lpc32xx_startup(struct uart_port *port) |
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{ |
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int retval; |
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unsigned long flags; |
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u32 tmp; |
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|
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spin_lock_irqsave(&port->lock, flags); |
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|
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__serial_uart_flush(port); |
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|
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writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | |
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LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), |
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LPC32XX_HSUART_IIR(port->membase)); |
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|
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writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); |
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|
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/* |
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* Set receiver timeout, HSU offset of 20, no break, no interrupts, |
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* and default FIFO trigger levels |
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*/ |
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tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | |
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LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; |
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writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); |
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|
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lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ |
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|
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spin_unlock_irqrestore(&port->lock, flags); |
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|
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retval = request_irq(port->irq, serial_lpc32xx_interrupt, |
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0, MODNAME, port); |
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if (!retval) |
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writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN), |
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LPC32XX_HSUART_CTRL(port->membase)); |
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|
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return retval; |
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} |
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|
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/* port->lock is not held. */ |
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static void serial_lpc32xx_shutdown(struct uart_port *port) |
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{ |
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u32 tmp; |
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unsigned long flags; |
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|
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spin_lock_irqsave(&port->lock, flags); |
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|
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tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | |
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LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; |
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writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); |
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|
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lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */ |
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|
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spin_unlock_irqrestore(&port->lock, flags); |
|
|
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free_irq(port->irq, port); |
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} |
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|
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/* port->lock is not held. */ |
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static void serial_lpc32xx_set_termios(struct uart_port *port, |
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struct ktermios *termios, |
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struct ktermios *old) |
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{ |
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unsigned long flags; |
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unsigned int baud, quot; |
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u32 tmp; |
|
|
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/* Always 8-bit, no parity, 1 stop bit */ |
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termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); |
|
termios->c_cflag |= CS8; |
|
|
|
termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS); |
|
|
|
baud = uart_get_baud_rate(port, termios, old, 0, |
|
port->uartclk / 14); |
|
|
|
quot = __serial_get_clock_div(port->uartclk, baud); |
|
|
|
spin_lock_irqsave(&port->lock, flags); |
|
|
|
/* Ignore characters? */ |
|
tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); |
|
if ((termios->c_cflag & CREAD) == 0) |
|
tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); |
|
else |
|
tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN; |
|
writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); |
|
|
|
writel(quot, LPC32XX_HSUART_RATE(port->membase)); |
|
|
|
uart_update_timeout(port, termios->c_cflag, baud); |
|
|
|
spin_unlock_irqrestore(&port->lock, flags); |
|
|
|
/* Don't rewrite B0 */ |
|
if (tty_termios_baud_rate(termios)) |
|
tty_termios_encode_baud_rate(termios, baud, baud); |
|
} |
|
|
|
static const char *serial_lpc32xx_type(struct uart_port *port) |
|
{ |
|
return MODNAME; |
|
} |
|
|
|
static void serial_lpc32xx_release_port(struct uart_port *port) |
|
{ |
|
if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { |
|
if (port->flags & UPF_IOREMAP) { |
|
iounmap(port->membase); |
|
port->membase = NULL; |
|
} |
|
|
|
release_mem_region(port->mapbase, SZ_4K); |
|
} |
|
} |
|
|
|
static int serial_lpc32xx_request_port(struct uart_port *port) |
|
{ |
|
int ret = -ENODEV; |
|
|
|
if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { |
|
ret = 0; |
|
|
|
if (!request_mem_region(port->mapbase, SZ_4K, MODNAME)) |
|
ret = -EBUSY; |
|
else if (port->flags & UPF_IOREMAP) { |
|
port->membase = ioremap(port->mapbase, SZ_4K); |
|
if (!port->membase) { |
|
release_mem_region(port->mapbase, SZ_4K); |
|
ret = -ENOMEM; |
|
} |
|
} |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static void serial_lpc32xx_config_port(struct uart_port *port, int uflags) |
|
{ |
|
int ret; |
|
|
|
ret = serial_lpc32xx_request_port(port); |
|
if (ret < 0) |
|
return; |
|
port->type = PORT_UART00; |
|
port->fifosize = 64; |
|
|
|
__serial_uart_flush(port); |
|
|
|
writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | |
|
LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), |
|
LPC32XX_HSUART_IIR(port->membase)); |
|
|
|
writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); |
|
|
|
/* Set receiver timeout, HSU offset of 20, no break, no interrupts, |
|
and default FIFO trigger levels */ |
|
writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | |
|
LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B, |
|
LPC32XX_HSUART_CTRL(port->membase)); |
|
} |
|
|
|
static int serial_lpc32xx_verify_port(struct uart_port *port, |
|
struct serial_struct *ser) |
|
{ |
|
int ret = 0; |
|
|
|
if (ser->type != PORT_UART00) |
|
ret = -EINVAL; |
|
|
|
return ret; |
|
} |
|
|
|
static const struct uart_ops serial_lpc32xx_pops = { |
|
.tx_empty = serial_lpc32xx_tx_empty, |
|
.set_mctrl = serial_lpc32xx_set_mctrl, |
|
.get_mctrl = serial_lpc32xx_get_mctrl, |
|
.stop_tx = serial_lpc32xx_stop_tx, |
|
.start_tx = serial_lpc32xx_start_tx, |
|
.stop_rx = serial_lpc32xx_stop_rx, |
|
.break_ctl = serial_lpc32xx_break_ctl, |
|
.startup = serial_lpc32xx_startup, |
|
.shutdown = serial_lpc32xx_shutdown, |
|
.set_termios = serial_lpc32xx_set_termios, |
|
.type = serial_lpc32xx_type, |
|
.release_port = serial_lpc32xx_release_port, |
|
.request_port = serial_lpc32xx_request_port, |
|
.config_port = serial_lpc32xx_config_port, |
|
.verify_port = serial_lpc32xx_verify_port, |
|
}; |
|
|
|
/* |
|
* Register a set of serial devices attached to a platform device |
|
*/ |
|
static int serial_hs_lpc32xx_probe(struct platform_device *pdev) |
|
{ |
|
struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered]; |
|
int ret = 0; |
|
struct resource *res; |
|
|
|
if (uarts_registered >= MAX_PORTS) { |
|
dev_err(&pdev->dev, |
|
"Error: Number of possible ports exceeded (%d)!\n", |
|
uarts_registered + 1); |
|
return -ENXIO; |
|
} |
|
|
|
memset(p, 0, sizeof(*p)); |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
if (!res) { |
|
dev_err(&pdev->dev, |
|
"Error getting mem resource for HS UART port %d\n", |
|
uarts_registered); |
|
return -ENXIO; |
|
} |
|
p->port.mapbase = res->start; |
|
p->port.membase = NULL; |
|
|
|
ret = platform_get_irq(pdev, 0); |
|
if (ret < 0) |
|
return ret; |
|
p->port.irq = ret; |
|
|
|
p->port.iotype = UPIO_MEM32; |
|
p->port.uartclk = LPC32XX_MAIN_OSC_FREQ; |
|
p->port.regshift = 2; |
|
p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP; |
|
p->port.dev = &pdev->dev; |
|
p->port.ops = &serial_lpc32xx_pops; |
|
p->port.line = uarts_registered++; |
|
spin_lock_init(&p->port.lock); |
|
|
|
/* send port to loopback mode by default */ |
|
lpc32xx_loopback_set(p->port.mapbase, 1); |
|
|
|
ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port); |
|
|
|
platform_set_drvdata(pdev, p); |
|
|
|
return ret; |
|
} |
|
|
|
/* |
|
* Remove serial ports registered against a platform device. |
|
*/ |
|
static int serial_hs_lpc32xx_remove(struct platform_device *pdev) |
|
{ |
|
struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); |
|
|
|
uart_remove_one_port(&lpc32xx_hs_reg, &p->port); |
|
|
|
return 0; |
|
} |
|
|
|
|
|
#ifdef CONFIG_PM |
|
static int serial_hs_lpc32xx_suspend(struct platform_device *pdev, |
|
pm_message_t state) |
|
{ |
|
struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); |
|
|
|
uart_suspend_port(&lpc32xx_hs_reg, &p->port); |
|
|
|
return 0; |
|
} |
|
|
|
static int serial_hs_lpc32xx_resume(struct platform_device *pdev) |
|
{ |
|
struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); |
|
|
|
uart_resume_port(&lpc32xx_hs_reg, &p->port); |
|
|
|
return 0; |
|
} |
|
#else |
|
#define serial_hs_lpc32xx_suspend NULL |
|
#define serial_hs_lpc32xx_resume NULL |
|
#endif |
|
|
|
static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = { |
|
{ .compatible = "nxp,lpc3220-hsuart" }, |
|
{ /* sentinel */ } |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids); |
|
|
|
static struct platform_driver serial_hs_lpc32xx_driver = { |
|
.probe = serial_hs_lpc32xx_probe, |
|
.remove = serial_hs_lpc32xx_remove, |
|
.suspend = serial_hs_lpc32xx_suspend, |
|
.resume = serial_hs_lpc32xx_resume, |
|
.driver = { |
|
.name = MODNAME, |
|
.of_match_table = serial_hs_lpc32xx_dt_ids, |
|
}, |
|
}; |
|
|
|
static int __init lpc32xx_hsuart_init(void) |
|
{ |
|
int ret; |
|
|
|
ret = uart_register_driver(&lpc32xx_hs_reg); |
|
if (ret) |
|
return ret; |
|
|
|
ret = platform_driver_register(&serial_hs_lpc32xx_driver); |
|
if (ret) |
|
uart_unregister_driver(&lpc32xx_hs_reg); |
|
|
|
return ret; |
|
} |
|
|
|
static void __exit lpc32xx_hsuart_exit(void) |
|
{ |
|
platform_driver_unregister(&serial_hs_lpc32xx_driver); |
|
uart_unregister_driver(&lpc32xx_hs_reg); |
|
} |
|
|
|
module_init(lpc32xx_hsuart_init); |
|
module_exit(lpc32xx_hsuart_exit); |
|
|
|
MODULE_AUTHOR("Kevin Wells <[email protected]>"); |
|
MODULE_AUTHOR("Roland Stigge <[email protected]>"); |
|
MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver"); |
|
MODULE_LICENSE("GPL");
|
|
|