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1223 lines
31 KiB
1223 lines
31 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Driver for Zilog serial chips found on SGI workstations and |
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* servers. This driver could actually be made more generic. |
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* |
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* This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the |
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* old drivers/sgi/char/sgiserial.c code which itself is based of the original |
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* drivers/sbus/char/zs.c code. A lot of code has been simply moved over |
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* directly from there but much has been rewritten. Credits therefore go out |
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* to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell |
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* for their work there. |
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* |
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* Copyright (C) 2002 Ralf Baechle ([email protected]) |
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* Copyright (C) 2002 David S. Miller ([email protected]) |
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*/ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/errno.h> |
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#include <linux/delay.h> |
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#include <linux/tty.h> |
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#include <linux/tty_flip.h> |
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#include <linux/major.h> |
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#include <linux/string.h> |
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#include <linux/ptrace.h> |
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#include <linux/ioport.h> |
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#include <linux/slab.h> |
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#include <linux/circ_buf.h> |
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#include <linux/serial.h> |
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#include <linux/sysrq.h> |
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#include <linux/console.h> |
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#include <linux/spinlock.h> |
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#include <linux/init.h> |
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|
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#include <asm/io.h> |
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#include <asm/irq.h> |
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#include <asm/sgialib.h> |
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#include <asm/sgi/ioc.h> |
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#include <asm/sgi/hpc3.h> |
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#include <asm/sgi/ip22.h> |
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|
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#include <linux/serial_core.h> |
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|
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#include "ip22zilog.h" |
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|
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/* |
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* On IP22 we need to delay after register accesses but we do not need to |
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* flush writes. |
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*/ |
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#define ZSDELAY() udelay(5) |
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#define ZSDELAY_LONG() udelay(20) |
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#define ZS_WSYNC(channel) do { } while (0) |
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|
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#define NUM_IP22ZILOG 1 |
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#define NUM_CHANNELS (NUM_IP22ZILOG * 2) |
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|
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#define ZS_CLOCK 3672000 /* Zilog input clock rate. */ |
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#define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */ |
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|
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/* |
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* We wrap our port structure around the generic uart_port. |
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*/ |
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struct uart_ip22zilog_port { |
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struct uart_port port; |
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|
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/* IRQ servicing chain. */ |
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struct uart_ip22zilog_port *next; |
|
|
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/* Current values of Zilog write registers. */ |
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unsigned char curregs[NUM_ZSREGS]; |
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|
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unsigned int flags; |
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#define IP22ZILOG_FLAG_IS_CONS 0x00000004 |
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#define IP22ZILOG_FLAG_IS_KGDB 0x00000008 |
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#define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010 |
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#define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020 |
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#define IP22ZILOG_FLAG_REGS_HELD 0x00000040 |
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#define IP22ZILOG_FLAG_TX_STOPPED 0x00000080 |
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#define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100 |
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#define IP22ZILOG_FLAG_RESET_DONE 0x00000200 |
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|
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unsigned int tty_break; |
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|
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unsigned char parity_mask; |
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unsigned char prev_status; |
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}; |
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|
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#define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase)) |
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#define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT)) |
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#define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \ |
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(UART_ZILOG(PORT)->curregs[REGNUM]) |
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#define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \ |
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((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL)) |
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#define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS) |
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#define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB) |
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#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS) |
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#define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A) |
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#define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD) |
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#define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED) |
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#define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE) |
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|
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/* Reading and writing Zilog8530 registers. The delays are to make this |
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* driver work on the IP22 which needs a settling delay after each chip |
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* register access, other machines handle this in hardware via auxiliary |
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* flip-flops which implement the settle time we do in software. |
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* |
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* The port lock must be held and local IRQs must be disabled |
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* when {read,write}_zsreg is invoked. |
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*/ |
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static unsigned char read_zsreg(struct zilog_channel *channel, |
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unsigned char reg) |
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{ |
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unsigned char retval; |
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|
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writeb(reg, &channel->control); |
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ZSDELAY(); |
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retval = readb(&channel->control); |
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ZSDELAY(); |
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|
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return retval; |
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} |
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|
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static void write_zsreg(struct zilog_channel *channel, |
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unsigned char reg, unsigned char value) |
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{ |
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writeb(reg, &channel->control); |
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ZSDELAY(); |
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writeb(value, &channel->control); |
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ZSDELAY(); |
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} |
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|
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static void ip22zilog_clear_fifo(struct zilog_channel *channel) |
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{ |
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int i; |
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|
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for (i = 0; i < 32; i++) { |
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unsigned char regval; |
|
|
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regval = readb(&channel->control); |
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ZSDELAY(); |
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if (regval & Rx_CH_AV) |
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break; |
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|
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regval = read_zsreg(channel, R1); |
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readb(&channel->data); |
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ZSDELAY(); |
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|
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if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) { |
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writeb(ERR_RES, &channel->control); |
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ZSDELAY(); |
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ZS_WSYNC(channel); |
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} |
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} |
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} |
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|
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/* This function must only be called when the TX is not busy. The UART |
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* port lock must be held and local interrupts disabled. |
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*/ |
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static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs) |
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{ |
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int i; |
|
|
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/* Let pending transmits finish. */ |
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for (i = 0; i < 1000; i++) { |
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unsigned char stat = read_zsreg(channel, R1); |
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if (stat & ALL_SNT) |
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break; |
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udelay(100); |
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} |
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|
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writeb(ERR_RES, &channel->control); |
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ZSDELAY(); |
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ZS_WSYNC(channel); |
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|
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ip22zilog_clear_fifo(channel); |
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|
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/* Disable all interrupts. */ |
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write_zsreg(channel, R1, |
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regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); |
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|
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/* Set parity, sync config, stop bits, and clock divisor. */ |
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write_zsreg(channel, R4, regs[R4]); |
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|
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/* Set misc. TX/RX control bits. */ |
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write_zsreg(channel, R10, regs[R10]); |
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|
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/* Set TX/RX controls sans the enable bits. */ |
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write_zsreg(channel, R3, regs[R3] & ~RxENAB); |
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write_zsreg(channel, R5, regs[R5] & ~TxENAB); |
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|
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/* Synchronous mode config. */ |
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write_zsreg(channel, R6, regs[R6]); |
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write_zsreg(channel, R7, regs[R7]); |
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|
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/* Don't mess with the interrupt vector (R2, unused by us) and |
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* master interrupt control (R9). We make sure this is setup |
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* properly at probe time then never touch it again. |
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*/ |
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|
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/* Disable baud generator. */ |
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write_zsreg(channel, R14, regs[R14] & ~BRENAB); |
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|
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/* Clock mode control. */ |
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write_zsreg(channel, R11, regs[R11]); |
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|
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/* Lower and upper byte of baud rate generator divisor. */ |
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write_zsreg(channel, R12, regs[R12]); |
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write_zsreg(channel, R13, regs[R13]); |
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|
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/* Now rewrite R14, with BRENAB (if set). */ |
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write_zsreg(channel, R14, regs[R14]); |
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|
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/* External status interrupt control. */ |
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write_zsreg(channel, R15, regs[R15]); |
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|
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/* Reset external status interrupts. */ |
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write_zsreg(channel, R0, RES_EXT_INT); |
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write_zsreg(channel, R0, RES_EXT_INT); |
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|
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/* Rewrite R3/R5, this time without enables masked. */ |
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write_zsreg(channel, R3, regs[R3]); |
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write_zsreg(channel, R5, regs[R5]); |
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|
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/* Rewrite R1, this time without IRQ enabled masked. */ |
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write_zsreg(channel, R1, regs[R1]); |
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} |
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|
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/* Reprogram the Zilog channel HW registers with the copies found in the |
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* software state struct. If the transmitter is busy, we defer this update |
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* until the next TX complete interrupt. Else, we do it right now. |
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* |
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* The UART port lock must be held and local interrupts disabled. |
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*/ |
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static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up, |
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struct zilog_channel *channel) |
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{ |
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if (!ZS_REGS_HELD(up)) { |
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if (ZS_TX_ACTIVE(up)) { |
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up->flags |= IP22ZILOG_FLAG_REGS_HELD; |
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} else { |
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__load_zsregs(channel, up->curregs); |
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} |
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} |
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} |
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|
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#define Rx_BRK 0x0100 /* BREAK event software flag. */ |
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#define Rx_SYS 0x0200 /* SysRq event software flag. */ |
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|
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static bool ip22zilog_receive_chars(struct uart_ip22zilog_port *up, |
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struct zilog_channel *channel) |
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{ |
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unsigned char ch, flag; |
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unsigned int r1; |
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bool push = up->port.state != NULL; |
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|
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for (;;) { |
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ch = readb(&channel->control); |
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ZSDELAY(); |
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if (!(ch & Rx_CH_AV)) |
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break; |
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|
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r1 = read_zsreg(channel, R1); |
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if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { |
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writeb(ERR_RES, &channel->control); |
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ZSDELAY(); |
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ZS_WSYNC(channel); |
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} |
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|
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ch = readb(&channel->data); |
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ZSDELAY(); |
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|
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ch &= up->parity_mask; |
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|
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/* Handle the null char got when BREAK is removed. */ |
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if (!ch) |
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r1 |= up->tty_break; |
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|
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/* A real serial line, record the character and status. */ |
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flag = TTY_NORMAL; |
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up->port.icount.rx++; |
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if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | Rx_SYS | Rx_BRK)) { |
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up->tty_break = 0; |
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|
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if (r1 & (Rx_SYS | Rx_BRK)) { |
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up->port.icount.brk++; |
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if (r1 & Rx_SYS) |
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continue; |
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r1 &= ~(PAR_ERR | CRC_ERR); |
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} |
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else if (r1 & PAR_ERR) |
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up->port.icount.parity++; |
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else if (r1 & CRC_ERR) |
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up->port.icount.frame++; |
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if (r1 & Rx_OVR) |
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up->port.icount.overrun++; |
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r1 &= up->port.read_status_mask; |
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if (r1 & Rx_BRK) |
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flag = TTY_BREAK; |
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else if (r1 & PAR_ERR) |
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flag = TTY_PARITY; |
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else if (r1 & CRC_ERR) |
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flag = TTY_FRAME; |
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} |
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|
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if (uart_handle_sysrq_char(&up->port, ch)) |
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continue; |
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|
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if (push) |
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uart_insert_char(&up->port, r1, Rx_OVR, ch, flag); |
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} |
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return push; |
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} |
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|
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static void ip22zilog_status_handle(struct uart_ip22zilog_port *up, |
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struct zilog_channel *channel) |
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{ |
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unsigned char status; |
|
|
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status = readb(&channel->control); |
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ZSDELAY(); |
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|
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writeb(RES_EXT_INT, &channel->control); |
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ZSDELAY(); |
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ZS_WSYNC(channel); |
|
|
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if (up->curregs[R15] & BRKIE) { |
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if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) { |
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if (uart_handle_break(&up->port)) |
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up->tty_break = Rx_SYS; |
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else |
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up->tty_break = Rx_BRK; |
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} |
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} |
|
|
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if (ZS_WANTS_MODEM_STATUS(up)) { |
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if (status & SYNC) |
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up->port.icount.dsr++; |
|
|
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/* The Zilog just gives us an interrupt when DCD/CTS/etc. change. |
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* But it does not tell us which bit has changed, we have to keep |
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* track of this ourselves. |
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*/ |
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if ((status ^ up->prev_status) ^ DCD) |
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uart_handle_dcd_change(&up->port, |
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(status & DCD)); |
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if ((status ^ up->prev_status) ^ CTS) |
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uart_handle_cts_change(&up->port, |
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(status & CTS)); |
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|
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wake_up_interruptible(&up->port.state->port.delta_msr_wait); |
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} |
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|
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up->prev_status = status; |
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} |
|
|
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static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up, |
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struct zilog_channel *channel) |
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{ |
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struct circ_buf *xmit; |
|
|
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if (ZS_IS_CONS(up)) { |
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unsigned char status = readb(&channel->control); |
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ZSDELAY(); |
|
|
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/* TX still busy? Just wait for the next TX done interrupt. |
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* |
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* It can occur because of how we do serial console writes. It would |
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* be nice to transmit console writes just like we normally would for |
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* a TTY line. (ie. buffered and TX interrupt driven). That is not |
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* easy because console writes cannot sleep. One solution might be |
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* to poll on enough port->xmit space becoming free. -DaveM |
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*/ |
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if (!(status & Tx_BUF_EMP)) |
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return; |
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} |
|
|
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up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE; |
|
|
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if (ZS_REGS_HELD(up)) { |
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__load_zsregs(channel, up->curregs); |
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up->flags &= ~IP22ZILOG_FLAG_REGS_HELD; |
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} |
|
|
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if (ZS_TX_STOPPED(up)) { |
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up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; |
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goto ack_tx_int; |
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} |
|
|
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if (up->port.x_char) { |
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up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; |
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writeb(up->port.x_char, &channel->data); |
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ZSDELAY(); |
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ZS_WSYNC(channel); |
|
|
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up->port.icount.tx++; |
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up->port.x_char = 0; |
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return; |
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} |
|
|
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if (up->port.state == NULL) |
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goto ack_tx_int; |
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xmit = &up->port.state->xmit; |
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if (uart_circ_empty(xmit)) |
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goto ack_tx_int; |
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if (uart_tx_stopped(&up->port)) |
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goto ack_tx_int; |
|
|
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up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; |
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writeb(xmit->buf[xmit->tail], &channel->data); |
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ZSDELAY(); |
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ZS_WSYNC(channel); |
|
|
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
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up->port.icount.tx++; |
|
|
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
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uart_write_wakeup(&up->port); |
|
|
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return; |
|
|
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ack_tx_int: |
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writeb(RES_Tx_P, &channel->control); |
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ZSDELAY(); |
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ZS_WSYNC(channel); |
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} |
|
|
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static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id) |
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{ |
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struct uart_ip22zilog_port *up = dev_id; |
|
|
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while (up) { |
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struct zilog_channel *channel |
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= ZILOG_CHANNEL_FROM_PORT(&up->port); |
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unsigned char r3; |
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bool push = false; |
|
|
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spin_lock(&up->port.lock); |
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r3 = read_zsreg(channel, R3); |
|
|
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/* Channel A */ |
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if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { |
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writeb(RES_H_IUS, &channel->control); |
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ZSDELAY(); |
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ZS_WSYNC(channel); |
|
|
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if (r3 & CHARxIP) |
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push = ip22zilog_receive_chars(up, channel); |
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if (r3 & CHAEXT) |
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ip22zilog_status_handle(up, channel); |
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if (r3 & CHATxIP) |
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ip22zilog_transmit_chars(up, channel); |
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} |
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spin_unlock(&up->port.lock); |
|
|
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if (push) |
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tty_flip_buffer_push(&up->port.state->port); |
|
|
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/* Channel B */ |
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up = up->next; |
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channel = ZILOG_CHANNEL_FROM_PORT(&up->port); |
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push = false; |
|
|
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spin_lock(&up->port.lock); |
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if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { |
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writeb(RES_H_IUS, &channel->control); |
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ZSDELAY(); |
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ZS_WSYNC(channel); |
|
|
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if (r3 & CHBRxIP) |
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push = ip22zilog_receive_chars(up, channel); |
|
if (r3 & CHBEXT) |
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ip22zilog_status_handle(up, channel); |
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if (r3 & CHBTxIP) |
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ip22zilog_transmit_chars(up, channel); |
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} |
|
spin_unlock(&up->port.lock); |
|
|
|
if (push) |
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tty_flip_buffer_push(&up->port.state->port); |
|
|
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up = up->next; |
|
} |
|
|
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return IRQ_HANDLED; |
|
} |
|
|
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/* A convenient way to quickly get R0 status. The caller must _not_ hold the |
|
* port lock, it is acquired here. |
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*/ |
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static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port) |
|
{ |
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struct zilog_channel *channel; |
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unsigned char status; |
|
|
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channel = ZILOG_CHANNEL_FROM_PORT(port); |
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status = readb(&channel->control); |
|
ZSDELAY(); |
|
|
|
return status; |
|
} |
|
|
|
/* The port lock is not held. */ |
|
static unsigned int ip22zilog_tx_empty(struct uart_port *port) |
|
{ |
|
unsigned long flags; |
|
unsigned char status; |
|
unsigned int ret; |
|
|
|
spin_lock_irqsave(&port->lock, flags); |
|
|
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status = ip22zilog_read_channel_status(port); |
|
|
|
spin_unlock_irqrestore(&port->lock, flags); |
|
|
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if (status & Tx_BUF_EMP) |
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ret = TIOCSER_TEMT; |
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else |
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ret = 0; |
|
|
|
return ret; |
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} |
|
|
|
/* The port lock is held and interrupts are disabled. */ |
|
static unsigned int ip22zilog_get_mctrl(struct uart_port *port) |
|
{ |
|
unsigned char status; |
|
unsigned int ret; |
|
|
|
status = ip22zilog_read_channel_status(port); |
|
|
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ret = 0; |
|
if (status & DCD) |
|
ret |= TIOCM_CAR; |
|
if (status & SYNC) |
|
ret |= TIOCM_DSR; |
|
if (status & CTS) |
|
ret |= TIOCM_CTS; |
|
|
|
return ret; |
|
} |
|
|
|
/* The port lock is held and interrupts are disabled. */ |
|
static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl) |
|
{ |
|
struct uart_ip22zilog_port *up = |
|
container_of(port, struct uart_ip22zilog_port, port); |
|
struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); |
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unsigned char set_bits, clear_bits; |
|
|
|
set_bits = clear_bits = 0; |
|
|
|
if (mctrl & TIOCM_RTS) |
|
set_bits |= RTS; |
|
else |
|
clear_bits |= RTS; |
|
if (mctrl & TIOCM_DTR) |
|
set_bits |= DTR; |
|
else |
|
clear_bits |= DTR; |
|
|
|
/* NOTE: Not subject to 'transmitter active' rule. */ |
|
up->curregs[R5] |= set_bits; |
|
up->curregs[R5] &= ~clear_bits; |
|
write_zsreg(channel, R5, up->curregs[R5]); |
|
} |
|
|
|
/* The port lock is held and interrupts are disabled. */ |
|
static void ip22zilog_stop_tx(struct uart_port *port) |
|
{ |
|
struct uart_ip22zilog_port *up = |
|
container_of(port, struct uart_ip22zilog_port, port); |
|
|
|
up->flags |= IP22ZILOG_FLAG_TX_STOPPED; |
|
} |
|
|
|
/* The port lock is held and interrupts are disabled. */ |
|
static void ip22zilog_start_tx(struct uart_port *port) |
|
{ |
|
struct uart_ip22zilog_port *up = |
|
container_of(port, struct uart_ip22zilog_port, port); |
|
struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); |
|
unsigned char status; |
|
|
|
up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; |
|
up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; |
|
|
|
status = readb(&channel->control); |
|
ZSDELAY(); |
|
|
|
/* TX busy? Just wait for the TX done interrupt. */ |
|
if (!(status & Tx_BUF_EMP)) |
|
return; |
|
|
|
/* Send the first character to jump-start the TX done |
|
* IRQ sending engine. |
|
*/ |
|
if (port->x_char) { |
|
writeb(port->x_char, &channel->data); |
|
ZSDELAY(); |
|
ZS_WSYNC(channel); |
|
|
|
port->icount.tx++; |
|
port->x_char = 0; |
|
} else { |
|
struct circ_buf *xmit = &port->state->xmit; |
|
|
|
if (uart_circ_empty(xmit)) |
|
return; |
|
writeb(xmit->buf[xmit->tail], &channel->data); |
|
ZSDELAY(); |
|
ZS_WSYNC(channel); |
|
|
|
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
|
port->icount.tx++; |
|
|
|
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
|
uart_write_wakeup(&up->port); |
|
} |
|
} |
|
|
|
/* The port lock is held and interrupts are disabled. */ |
|
static void ip22zilog_stop_rx(struct uart_port *port) |
|
{ |
|
struct uart_ip22zilog_port *up = UART_ZILOG(port); |
|
struct zilog_channel *channel; |
|
|
|
if (ZS_IS_CONS(up)) |
|
return; |
|
|
|
channel = ZILOG_CHANNEL_FROM_PORT(port); |
|
|
|
/* Disable all RX interrupts. */ |
|
up->curregs[R1] &= ~RxINT_MASK; |
|
ip22zilog_maybe_update_regs(up, channel); |
|
} |
|
|
|
/* The port lock is held. */ |
|
static void ip22zilog_enable_ms(struct uart_port *port) |
|
{ |
|
struct uart_ip22zilog_port *up = |
|
container_of(port, struct uart_ip22zilog_port, port); |
|
struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); |
|
unsigned char new_reg; |
|
|
|
new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE); |
|
if (new_reg != up->curregs[R15]) { |
|
up->curregs[R15] = new_reg; |
|
|
|
/* NOTE: Not subject to 'transmitter active' rule. */ |
|
write_zsreg(channel, R15, up->curregs[R15]); |
|
} |
|
} |
|
|
|
/* The port lock is not held. */ |
|
static void ip22zilog_break_ctl(struct uart_port *port, int break_state) |
|
{ |
|
struct uart_ip22zilog_port *up = |
|
container_of(port, struct uart_ip22zilog_port, port); |
|
struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); |
|
unsigned char set_bits, clear_bits, new_reg; |
|
unsigned long flags; |
|
|
|
set_bits = clear_bits = 0; |
|
|
|
if (break_state) |
|
set_bits |= SND_BRK; |
|
else |
|
clear_bits |= SND_BRK; |
|
|
|
spin_lock_irqsave(&port->lock, flags); |
|
|
|
new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; |
|
if (new_reg != up->curregs[R5]) { |
|
up->curregs[R5] = new_reg; |
|
|
|
/* NOTE: Not subject to 'transmitter active' rule. */ |
|
write_zsreg(channel, R5, up->curregs[R5]); |
|
} |
|
|
|
spin_unlock_irqrestore(&port->lock, flags); |
|
} |
|
|
|
static void __ip22zilog_reset(struct uart_ip22zilog_port *up) |
|
{ |
|
struct zilog_channel *channel; |
|
int i; |
|
|
|
if (up->flags & IP22ZILOG_FLAG_RESET_DONE) |
|
return; |
|
|
|
/* Let pending transmits finish. */ |
|
channel = ZILOG_CHANNEL_FROM_PORT(&up->port); |
|
for (i = 0; i < 1000; i++) { |
|
unsigned char stat = read_zsreg(channel, R1); |
|
if (stat & ALL_SNT) |
|
break; |
|
udelay(100); |
|
} |
|
|
|
if (!ZS_IS_CHANNEL_A(up)) { |
|
up++; |
|
channel = ZILOG_CHANNEL_FROM_PORT(&up->port); |
|
} |
|
write_zsreg(channel, R9, FHWRES); |
|
ZSDELAY_LONG(); |
|
(void) read_zsreg(channel, R0); |
|
|
|
up->flags |= IP22ZILOG_FLAG_RESET_DONE; |
|
up->next->flags |= IP22ZILOG_FLAG_RESET_DONE; |
|
} |
|
|
|
static void __ip22zilog_startup(struct uart_ip22zilog_port *up) |
|
{ |
|
struct zilog_channel *channel; |
|
|
|
channel = ZILOG_CHANNEL_FROM_PORT(&up->port); |
|
|
|
__ip22zilog_reset(up); |
|
|
|
__load_zsregs(channel, up->curregs); |
|
/* set master interrupt enable */ |
|
write_zsreg(channel, R9, up->curregs[R9]); |
|
up->prev_status = readb(&channel->control); |
|
|
|
/* Enable receiver and transmitter. */ |
|
up->curregs[R3] |= RxENAB; |
|
up->curregs[R5] |= TxENAB; |
|
|
|
up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; |
|
ip22zilog_maybe_update_regs(up, channel); |
|
} |
|
|
|
static int ip22zilog_startup(struct uart_port *port) |
|
{ |
|
struct uart_ip22zilog_port *up = UART_ZILOG(port); |
|
unsigned long flags; |
|
|
|
if (ZS_IS_CONS(up)) |
|
return 0; |
|
|
|
spin_lock_irqsave(&port->lock, flags); |
|
__ip22zilog_startup(up); |
|
spin_unlock_irqrestore(&port->lock, flags); |
|
return 0; |
|
} |
|
|
|
/* |
|
* The test for ZS_IS_CONS is explained by the following e-mail: |
|
***** |
|
* From: Russell King <[email protected]> |
|
* Date: Sun, 8 Dec 2002 10:18:38 +0000 |
|
* |
|
* On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote: |
|
* > I boot my 2.5 boxes using "console=ttyS0,9600" argument, |
|
* > and I noticed that something is not right with reference |
|
* > counting in this case. It seems that when the console |
|
* > is open by kernel initially, this is not accounted |
|
* > as an open, and uart_startup is not called. |
|
* |
|
* That is correct. We are unable to call uart_startup when the serial |
|
* console is initialised because it may need to allocate memory (as |
|
* request_irq does) and the memory allocators may not have been |
|
* initialised. |
|
* |
|
* 1. initialise the port into a state where it can send characters in the |
|
* console write method. |
|
* |
|
* 2. don't do the actual hardware shutdown in your shutdown() method (but |
|
* do the normal software shutdown - ie, free irqs etc) |
|
***** |
|
*/ |
|
static void ip22zilog_shutdown(struct uart_port *port) |
|
{ |
|
struct uart_ip22zilog_port *up = UART_ZILOG(port); |
|
struct zilog_channel *channel; |
|
unsigned long flags; |
|
|
|
if (ZS_IS_CONS(up)) |
|
return; |
|
|
|
spin_lock_irqsave(&port->lock, flags); |
|
|
|
channel = ZILOG_CHANNEL_FROM_PORT(port); |
|
|
|
/* Disable receiver and transmitter. */ |
|
up->curregs[R3] &= ~RxENAB; |
|
up->curregs[R5] &= ~TxENAB; |
|
|
|
/* Disable all interrupts and BRK assertion. */ |
|
up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); |
|
up->curregs[R5] &= ~SND_BRK; |
|
ip22zilog_maybe_update_regs(up, channel); |
|
|
|
spin_unlock_irqrestore(&port->lock, flags); |
|
} |
|
|
|
/* Shared by TTY driver and serial console setup. The port lock is held |
|
* and local interrupts are disabled. |
|
*/ |
|
static void |
|
ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag, |
|
unsigned int iflag, int brg) |
|
{ |
|
|
|
up->curregs[R10] = NRZ; |
|
up->curregs[R11] = TCBR | RCBR; |
|
|
|
/* Program BAUD and clock source. */ |
|
up->curregs[R4] &= ~XCLK_MASK; |
|
up->curregs[R4] |= X16CLK; |
|
up->curregs[R12] = brg & 0xff; |
|
up->curregs[R13] = (brg >> 8) & 0xff; |
|
up->curregs[R14] = BRENAB; |
|
|
|
/* Character size, stop bits, and parity. */ |
|
up->curregs[3] &= ~RxN_MASK; |
|
up->curregs[5] &= ~TxN_MASK; |
|
switch (cflag & CSIZE) { |
|
case CS5: |
|
up->curregs[3] |= Rx5; |
|
up->curregs[5] |= Tx5; |
|
up->parity_mask = 0x1f; |
|
break; |
|
case CS6: |
|
up->curregs[3] |= Rx6; |
|
up->curregs[5] |= Tx6; |
|
up->parity_mask = 0x3f; |
|
break; |
|
case CS7: |
|
up->curregs[3] |= Rx7; |
|
up->curregs[5] |= Tx7; |
|
up->parity_mask = 0x7f; |
|
break; |
|
case CS8: |
|
default: |
|
up->curregs[3] |= Rx8; |
|
up->curregs[5] |= Tx8; |
|
up->parity_mask = 0xff; |
|
break; |
|
} |
|
up->curregs[4] &= ~0x0c; |
|
if (cflag & CSTOPB) |
|
up->curregs[4] |= SB2; |
|
else |
|
up->curregs[4] |= SB1; |
|
if (cflag & PARENB) |
|
up->curregs[4] |= PAR_ENAB; |
|
else |
|
up->curregs[4] &= ~PAR_ENAB; |
|
if (!(cflag & PARODD)) |
|
up->curregs[4] |= PAR_EVEN; |
|
else |
|
up->curregs[4] &= ~PAR_EVEN; |
|
|
|
up->port.read_status_mask = Rx_OVR; |
|
if (iflag & INPCK) |
|
up->port.read_status_mask |= CRC_ERR | PAR_ERR; |
|
if (iflag & (IGNBRK | BRKINT | PARMRK)) |
|
up->port.read_status_mask |= BRK_ABRT; |
|
|
|
up->port.ignore_status_mask = 0; |
|
if (iflag & IGNPAR) |
|
up->port.ignore_status_mask |= CRC_ERR | PAR_ERR; |
|
if (iflag & IGNBRK) { |
|
up->port.ignore_status_mask |= BRK_ABRT; |
|
if (iflag & IGNPAR) |
|
up->port.ignore_status_mask |= Rx_OVR; |
|
} |
|
|
|
if ((cflag & CREAD) == 0) |
|
up->port.ignore_status_mask = 0xff; |
|
} |
|
|
|
/* The port lock is not held. */ |
|
static void |
|
ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios, |
|
struct ktermios *old) |
|
{ |
|
struct uart_ip22zilog_port *up = |
|
container_of(port, struct uart_ip22zilog_port, port); |
|
unsigned long flags; |
|
int baud, brg; |
|
|
|
baud = uart_get_baud_rate(port, termios, old, 1200, 76800); |
|
|
|
spin_lock_irqsave(&up->port.lock, flags); |
|
|
|
brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); |
|
|
|
ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg); |
|
|
|
if (UART_ENABLE_MS(&up->port, termios->c_cflag)) |
|
up->flags |= IP22ZILOG_FLAG_MODEM_STATUS; |
|
else |
|
up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS; |
|
|
|
ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port)); |
|
uart_update_timeout(port, termios->c_cflag, baud); |
|
|
|
spin_unlock_irqrestore(&up->port.lock, flags); |
|
} |
|
|
|
static const char *ip22zilog_type(struct uart_port *port) |
|
{ |
|
return "IP22-Zilog"; |
|
} |
|
|
|
/* We do not request/release mappings of the registers here, this |
|
* happens at early serial probe time. |
|
*/ |
|
static void ip22zilog_release_port(struct uart_port *port) |
|
{ |
|
} |
|
|
|
static int ip22zilog_request_port(struct uart_port *port) |
|
{ |
|
return 0; |
|
} |
|
|
|
/* These do not need to do anything interesting either. */ |
|
static void ip22zilog_config_port(struct uart_port *port, int flags) |
|
{ |
|
} |
|
|
|
/* We do not support letting the user mess with the divisor, IRQ, etc. */ |
|
static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser) |
|
{ |
|
return -EINVAL; |
|
} |
|
|
|
static const struct uart_ops ip22zilog_pops = { |
|
.tx_empty = ip22zilog_tx_empty, |
|
.set_mctrl = ip22zilog_set_mctrl, |
|
.get_mctrl = ip22zilog_get_mctrl, |
|
.stop_tx = ip22zilog_stop_tx, |
|
.start_tx = ip22zilog_start_tx, |
|
.stop_rx = ip22zilog_stop_rx, |
|
.enable_ms = ip22zilog_enable_ms, |
|
.break_ctl = ip22zilog_break_ctl, |
|
.startup = ip22zilog_startup, |
|
.shutdown = ip22zilog_shutdown, |
|
.set_termios = ip22zilog_set_termios, |
|
.type = ip22zilog_type, |
|
.release_port = ip22zilog_release_port, |
|
.request_port = ip22zilog_request_port, |
|
.config_port = ip22zilog_config_port, |
|
.verify_port = ip22zilog_verify_port, |
|
}; |
|
|
|
static struct uart_ip22zilog_port *ip22zilog_port_table; |
|
static struct zilog_layout **ip22zilog_chip_regs; |
|
|
|
static struct uart_ip22zilog_port *ip22zilog_irq_chain; |
|
static int zilog_irq = -1; |
|
|
|
static void * __init alloc_one_table(unsigned long size) |
|
{ |
|
return kzalloc(size, GFP_KERNEL); |
|
} |
|
|
|
static void __init ip22zilog_alloc_tables(void) |
|
{ |
|
ip22zilog_port_table = (struct uart_ip22zilog_port *) |
|
alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port)); |
|
ip22zilog_chip_regs = (struct zilog_layout **) |
|
alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *)); |
|
|
|
if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) { |
|
panic("IP22-Zilog: Cannot allocate IP22-Zilog tables."); |
|
} |
|
} |
|
|
|
/* Get the address of the registers for IP22-Zilog instance CHIP. */ |
|
static struct zilog_layout * __init get_zs(int chip) |
|
{ |
|
unsigned long base; |
|
|
|
if (chip < 0 || chip >= NUM_IP22ZILOG) { |
|
panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip); |
|
} |
|
|
|
/* Not probe-able, hard code it. */ |
|
base = (unsigned long) &sgioc->uart; |
|
|
|
zilog_irq = SGI_SERIAL_IRQ; |
|
request_mem_region(base, 8, "IP22-Zilog"); |
|
|
|
return (struct zilog_layout *) base; |
|
} |
|
|
|
#define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */ |
|
|
|
#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE |
|
static void ip22zilog_put_char(struct uart_port *port, int ch) |
|
{ |
|
struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); |
|
int loops = ZS_PUT_CHAR_MAX_DELAY; |
|
|
|
/* This is a timed polling loop so do not switch the explicit |
|
* udelay with ZSDELAY as that is a NOP on some platforms. -DaveM |
|
*/ |
|
do { |
|
unsigned char val = readb(&channel->control); |
|
if (val & Tx_BUF_EMP) { |
|
ZSDELAY(); |
|
break; |
|
} |
|
udelay(5); |
|
} while (--loops); |
|
|
|
writeb(ch, &channel->data); |
|
ZSDELAY(); |
|
ZS_WSYNC(channel); |
|
} |
|
|
|
static void |
|
ip22zilog_console_write(struct console *con, const char *s, unsigned int count) |
|
{ |
|
struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&up->port.lock, flags); |
|
uart_console_write(&up->port, s, count, ip22zilog_put_char); |
|
udelay(2); |
|
spin_unlock_irqrestore(&up->port.lock, flags); |
|
} |
|
|
|
static int __init ip22zilog_console_setup(struct console *con, char *options) |
|
{ |
|
struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; |
|
unsigned long flags; |
|
int baud = 9600, bits = 8; |
|
int parity = 'n'; |
|
int flow = 'n'; |
|
|
|
up->flags |= IP22ZILOG_FLAG_IS_CONS; |
|
|
|
printk(KERN_INFO "Console: ttyS%d (IP22-Zilog)\n", con->index); |
|
|
|
spin_lock_irqsave(&up->port.lock, flags); |
|
|
|
up->curregs[R15] |= BRKIE; |
|
|
|
__ip22zilog_startup(up); |
|
|
|
spin_unlock_irqrestore(&up->port.lock, flags); |
|
|
|
if (options) |
|
uart_parse_options(options, &baud, &parity, &bits, &flow); |
|
return uart_set_options(&up->port, con, baud, parity, bits, flow); |
|
} |
|
|
|
static struct uart_driver ip22zilog_reg; |
|
|
|
static struct console ip22zilog_console = { |
|
.name = "ttyS", |
|
.write = ip22zilog_console_write, |
|
.device = uart_console_device, |
|
.setup = ip22zilog_console_setup, |
|
.flags = CON_PRINTBUFFER, |
|
.index = -1, |
|
.data = &ip22zilog_reg, |
|
}; |
|
#endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */ |
|
|
|
static struct uart_driver ip22zilog_reg = { |
|
.owner = THIS_MODULE, |
|
.driver_name = "serial", |
|
.dev_name = "ttyS", |
|
.major = TTY_MAJOR, |
|
.minor = 64, |
|
.nr = NUM_CHANNELS, |
|
#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE |
|
.cons = &ip22zilog_console, |
|
#endif |
|
}; |
|
|
|
static void __init ip22zilog_prepare(void) |
|
{ |
|
unsigned char sysrq_on = IS_ENABLED(CONFIG_SERIAL_IP22_ZILOG_CONSOLE); |
|
struct uart_ip22zilog_port *up; |
|
struct zilog_layout *rp; |
|
int channel, chip; |
|
|
|
/* |
|
* Temporary fix. |
|
*/ |
|
for (channel = 0; channel < NUM_CHANNELS; channel++) |
|
spin_lock_init(&ip22zilog_port_table[channel].port.lock); |
|
|
|
ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1]; |
|
up = &ip22zilog_port_table[0]; |
|
for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--) |
|
up[channel].next = &up[channel - 1]; |
|
up[channel].next = NULL; |
|
|
|
for (chip = 0; chip < NUM_IP22ZILOG; chip++) { |
|
if (!ip22zilog_chip_regs[chip]) { |
|
ip22zilog_chip_regs[chip] = rp = get_zs(chip); |
|
|
|
up[(chip * 2) + 0].port.membase = (char *) &rp->channelB; |
|
up[(chip * 2) + 1].port.membase = (char *) &rp->channelA; |
|
|
|
/* In theory mapbase is the physical address ... */ |
|
up[(chip * 2) + 0].port.mapbase = |
|
(unsigned long) ioremap((unsigned long) &rp->channelB, 8); |
|
up[(chip * 2) + 1].port.mapbase = |
|
(unsigned long) ioremap((unsigned long) &rp->channelA, 8); |
|
} |
|
|
|
/* Channel A */ |
|
up[(chip * 2) + 0].port.iotype = UPIO_MEM; |
|
up[(chip * 2) + 0].port.irq = zilog_irq; |
|
up[(chip * 2) + 0].port.uartclk = ZS_CLOCK; |
|
up[(chip * 2) + 0].port.fifosize = 1; |
|
up[(chip * 2) + 0].port.has_sysrq = sysrq_on; |
|
up[(chip * 2) + 0].port.ops = &ip22zilog_pops; |
|
up[(chip * 2) + 0].port.type = PORT_IP22ZILOG; |
|
up[(chip * 2) + 0].port.flags = 0; |
|
up[(chip * 2) + 0].port.line = (chip * 2) + 0; |
|
up[(chip * 2) + 0].flags = 0; |
|
|
|
/* Channel B */ |
|
up[(chip * 2) + 1].port.iotype = UPIO_MEM; |
|
up[(chip * 2) + 1].port.irq = zilog_irq; |
|
up[(chip * 2) + 1].port.uartclk = ZS_CLOCK; |
|
up[(chip * 2) + 1].port.fifosize = 1; |
|
up[(chip * 2) + 1].port.has_sysrq = sysrq_on; |
|
up[(chip * 2) + 1].port.ops = &ip22zilog_pops; |
|
up[(chip * 2) + 1].port.type = PORT_IP22ZILOG; |
|
up[(chip * 2) + 1].port.line = (chip * 2) + 1; |
|
up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A; |
|
} |
|
|
|
for (channel = 0; channel < NUM_CHANNELS; channel++) { |
|
struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel]; |
|
int brg; |
|
|
|
/* Normal serial TTY. */ |
|
up->parity_mask = 0xff; |
|
up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; |
|
up->curregs[R4] = PAR_EVEN | X16CLK | SB1; |
|
up->curregs[R3] = RxENAB | Rx8; |
|
up->curregs[R5] = TxENAB | Tx8; |
|
up->curregs[R9] = NV | MIE; |
|
up->curregs[R10] = NRZ; |
|
up->curregs[R11] = TCBR | RCBR; |
|
brg = BPS_TO_BRG(9600, ZS_CLOCK / ZS_CLOCK_DIVISOR); |
|
up->curregs[R12] = (brg & 0xff); |
|
up->curregs[R13] = (brg >> 8) & 0xff; |
|
up->curregs[R14] = BRENAB; |
|
} |
|
} |
|
|
|
static int __init ip22zilog_ports_init(void) |
|
{ |
|
int ret; |
|
|
|
printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG); |
|
|
|
ip22zilog_prepare(); |
|
|
|
if (request_irq(zilog_irq, ip22zilog_interrupt, 0, |
|
"IP22-Zilog", ip22zilog_irq_chain)) { |
|
panic("IP22-Zilog: Unable to register zs interrupt handler.\n"); |
|
} |
|
|
|
ret = uart_register_driver(&ip22zilog_reg); |
|
if (ret == 0) { |
|
int i; |
|
|
|
for (i = 0; i < NUM_CHANNELS; i++) { |
|
struct uart_ip22zilog_port *up = &ip22zilog_port_table[i]; |
|
|
|
uart_add_one_port(&ip22zilog_reg, &up->port); |
|
} |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static int __init ip22zilog_init(void) |
|
{ |
|
/* IP22 Zilog setup is hard coded, no probing to do. */ |
|
ip22zilog_alloc_tables(); |
|
ip22zilog_ports_init(); |
|
|
|
return 0; |
|
} |
|
|
|
static void __exit ip22zilog_exit(void) |
|
{ |
|
int i; |
|
struct uart_ip22zilog_port *up; |
|
|
|
for (i = 0; i < NUM_CHANNELS; i++) { |
|
up = &ip22zilog_port_table[i]; |
|
|
|
uart_remove_one_port(&ip22zilog_reg, &up->port); |
|
} |
|
|
|
/* Free IO mem */ |
|
up = &ip22zilog_port_table[0]; |
|
for (i = 0; i < NUM_IP22ZILOG; i++) { |
|
if (up[(i * 2) + 0].port.mapbase) { |
|
iounmap((void*)up[(i * 2) + 0].port.mapbase); |
|
up[(i * 2) + 0].port.mapbase = 0; |
|
} |
|
if (up[(i * 2) + 1].port.mapbase) { |
|
iounmap((void*)up[(i * 2) + 1].port.mapbase); |
|
up[(i * 2) + 1].port.mapbase = 0; |
|
} |
|
} |
|
|
|
uart_unregister_driver(&ip22zilog_reg); |
|
} |
|
|
|
module_init(ip22zilog_init); |
|
module_exit(ip22zilog_exit); |
|
|
|
/* David wrote it but I'm to blame for the bugs ... */ |
|
MODULE_AUTHOR("Ralf Baechle <[email protected]>"); |
|
MODULE_DESCRIPTION("SGI Zilog serial port driver"); |
|
MODULE_LICENSE("GPL");
|
|
|