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153 lines
4.7 KiB
153 lines
4.7 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. |
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* |
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* This software is licensed under the terms of the GNU General Public |
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* License version 2, as published by the Free Software Foundation, and |
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* may be copied, distributed, and modified under those terms. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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*/ |
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#ifndef __DRIVERS_THERMAL_TEGRA_SOCTHERM_H |
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#define __DRIVERS_THERMAL_TEGRA_SOCTHERM_H |
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#define THERMCTL_LEVEL0_GROUP_CPU 0x0 |
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#define THERMCTL_LEVEL0_GROUP_GPU 0x4 |
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#define THERMCTL_LEVEL0_GROUP_MEM 0x8 |
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#define THERMCTL_LEVEL0_GROUP_TSENSE 0xc |
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#define SENSOR_CONFIG2 8 |
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#define SENSOR_CONFIG2_THERMA_MASK (0xffff << 16) |
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#define SENSOR_CONFIG2_THERMA_SHIFT 16 |
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#define SENSOR_CONFIG2_THERMB_MASK 0xffff |
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#define SENSOR_CONFIG2_THERMB_SHIFT 0 |
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#define THERMCTL_THERMTRIP_CTL 0x80 |
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/* BITs are defined in device file */ |
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#define THERMCTL_INTR_ENABLE 0x88 |
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#define THERMCTL_INTR_DISABLE 0x8c |
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#define TH_INTR_UP_DN_EN 0x3 |
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#define THERM_IRQ_MEM_MASK (TH_INTR_UP_DN_EN << 24) |
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#define THERM_IRQ_GPU_MASK (TH_INTR_UP_DN_EN << 16) |
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#define THERM_IRQ_CPU_MASK (TH_INTR_UP_DN_EN << 8) |
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#define THERM_IRQ_TSENSE_MASK (TH_INTR_UP_DN_EN << 0) |
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#define SENSOR_PDIV 0x1c0 |
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#define SENSOR_PDIV_CPU_MASK (0xf << 12) |
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#define SENSOR_PDIV_GPU_MASK (0xf << 8) |
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#define SENSOR_PDIV_MEM_MASK (0xf << 4) |
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#define SENSOR_PDIV_PLLX_MASK (0xf << 0) |
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#define SENSOR_HOTSPOT_OFF 0x1c4 |
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#define SENSOR_HOTSPOT_CPU_MASK (0xff << 16) |
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#define SENSOR_HOTSPOT_GPU_MASK (0xff << 8) |
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#define SENSOR_HOTSPOT_MEM_MASK (0xff << 0) |
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#define SENSOR_TEMP1 0x1c8 |
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#define SENSOR_TEMP1_CPU_TEMP_MASK (0xffff << 16) |
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#define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff |
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#define SENSOR_TEMP2 0x1cc |
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#define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16) |
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#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff |
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/** |
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* struct tegra_tsensor_group - SOC_THERM sensor group data |
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* @name: short name of the temperature sensor group |
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* @id: numeric ID of the temperature sensor group |
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* @sensor_temp_offset: offset of the SENSOR_TEMP* register |
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* @sensor_temp_mask: bit mask for this sensor group in SENSOR_TEMP* register |
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* @pdiv: the sensor count post-divider to use during runtime |
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* @pdiv_ate: the sensor count post-divider used during automated test |
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* @pdiv_mask: register bitfield mask for the PDIV field for this sensor |
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* @pllx_hotspot_diff: hotspot offset from the PLLX sensor, must be 0 for |
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PLLX sensor group |
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* @pllx_hotspot_mask: register bitfield mask for the HOTSPOT field |
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*/ |
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struct tegra_tsensor_group { |
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const char *name; |
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u8 id; |
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u16 sensor_temp_offset; |
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u32 sensor_temp_mask; |
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u32 pdiv, pdiv_ate, pdiv_mask; |
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u32 pllx_hotspot_diff, pllx_hotspot_mask; |
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u32 thermtrip_enable_mask; |
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u32 thermtrip_any_en_mask; |
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u32 thermtrip_threshold_mask; |
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u32 thermctl_isr_mask; |
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u16 thermctl_lvl0_offset; |
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u32 thermctl_lvl0_up_thresh_mask; |
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u32 thermctl_lvl0_dn_thresh_mask; |
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}; |
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struct tegra_tsensor_configuration { |
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u32 tall, tiddq_en, ten_count, pdiv, pdiv_ate, tsample, tsample_ate; |
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}; |
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struct tegra_tsensor { |
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const char *name; |
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const u32 base; |
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const struct tegra_tsensor_configuration *config; |
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const u32 calib_fuse_offset; |
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/* |
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* Correction values used to modify values read from |
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* calibration fuses |
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*/ |
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const s32 fuse_corr_alpha, fuse_corr_beta; |
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const struct tegra_tsensor_group *group; |
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}; |
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struct tsensor_group_thermtrips { |
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u8 id; |
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u32 temp; |
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}; |
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struct tegra_soctherm_fuse { |
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u32 fuse_base_cp_mask, fuse_base_cp_shift; |
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u32 fuse_base_ft_mask, fuse_base_ft_shift; |
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u32 fuse_shift_ft_mask, fuse_shift_ft_shift; |
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u32 fuse_spare_realignment; |
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}; |
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struct tsensor_shared_calib { |
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u32 base_cp, base_ft; |
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u32 actual_temp_cp, actual_temp_ft; |
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}; |
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struct tegra_soctherm_soc { |
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const struct tegra_tsensor *tsensors; |
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const unsigned int num_tsensors; |
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const struct tegra_tsensor_group **ttgs; |
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const unsigned int num_ttgs; |
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const struct tegra_soctherm_fuse *tfuse; |
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const int thresh_grain; |
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const unsigned int bptt; |
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const bool use_ccroc; |
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struct tsensor_group_thermtrips *thermtrips; |
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}; |
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int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse, |
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struct tsensor_shared_calib *shared); |
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int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor, |
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const struct tsensor_shared_calib *shared, |
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u32 *calib); |
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#ifdef CONFIG_ARCH_TEGRA_124_SOC |
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extern const struct tegra_soctherm_soc tegra124_soctherm; |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_132_SOC |
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extern const struct tegra_soctherm_soc tegra132_soctherm; |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_210_SOC |
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extern const struct tegra_soctherm_soc tegra210_soctherm; |
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#endif |
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#endif |
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