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736 lines
19 KiB
736 lines
19 KiB
/* |
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* Sonics Silicon Backplane |
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* Broadcom PCI-core driver |
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* |
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* Copyright 2005, Broadcom Corporation |
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* Copyright 2006, 2007, Michael Buesch <[email protected]> |
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* |
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* Licensed under the GNU/GPL. See COPYING for details. |
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*/ |
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|
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#include "ssb_private.h" |
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|
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#include <linux/ssb/ssb.h> |
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#include <linux/pci.h> |
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#include <linux/export.h> |
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#include <linux/delay.h> |
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#include <linux/ssb/ssb_embedded.h> |
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|
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static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address); |
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static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data); |
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static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address); |
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static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, |
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u8 address, u16 data); |
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|
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static inline |
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u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset) |
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{ |
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return ssb_read32(pc->dev, offset); |
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} |
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|
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static inline |
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void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value) |
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{ |
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ssb_write32(pc->dev, offset, value); |
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} |
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|
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static inline |
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u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset) |
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{ |
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return ssb_read16(pc->dev, offset); |
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} |
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|
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static inline |
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void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value) |
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{ |
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ssb_write16(pc->dev, offset, value); |
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} |
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|
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/************************************************** |
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* Code for hostmode operation. |
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**************************************************/ |
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|
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#ifdef CONFIG_SSB_PCICORE_HOSTMODE |
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|
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#include <asm/paccess.h> |
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/* Probe a 32bit value on the bus and catch bus exceptions. |
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* Returns nonzero on a bus exception. |
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* This is MIPS specific */ |
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#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr))) |
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|
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/* Assume one-hot slot wiring */ |
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#define SSB_PCI_SLOT_MAX 16 |
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|
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/* Global lock is OK, as we won't have more than one extpci anyway. */ |
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static DEFINE_SPINLOCK(cfgspace_lock); |
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/* Core to access the external PCI config space. Can only have one. */ |
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static struct ssb_pcicore *extpci_core; |
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|
|
|
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static u32 get_cfgspace_addr(struct ssb_pcicore *pc, |
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unsigned int bus, unsigned int dev, |
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unsigned int func, unsigned int off) |
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{ |
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u32 addr = 0; |
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u32 tmp; |
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|
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/* We do only have one cardbus device behind the bridge. */ |
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if (pc->cardbusmode && (dev > 1)) |
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goto out; |
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|
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if (bus == 0) { |
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/* Type 0 transaction */ |
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if (unlikely(dev >= SSB_PCI_SLOT_MAX)) |
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goto out; |
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/* Slide the window */ |
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tmp = SSB_PCICORE_SBTOPCI_CFG0; |
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tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK); |
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp); |
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/* Calculate the address */ |
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addr = SSB_PCI_CFG; |
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addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK); |
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addr |= (func << 8); |
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addr |= (off & ~3); |
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} else { |
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/* Type 1 transaction */ |
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, |
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SSB_PCICORE_SBTOPCI_CFG1); |
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/* Calculate the address */ |
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addr = SSB_PCI_CFG; |
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addr |= (bus << 16); |
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addr |= (dev << 11); |
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addr |= (func << 8); |
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addr |= (off & ~3); |
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} |
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out: |
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return addr; |
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} |
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|
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static int ssb_extpci_read_config(struct ssb_pcicore *pc, |
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unsigned int bus, unsigned int dev, |
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unsigned int func, unsigned int off, |
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void *buf, int len) |
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{ |
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int err = -EINVAL; |
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u32 addr, val; |
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void __iomem *mmio; |
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|
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WARN_ON(!pc->hostmode); |
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if (unlikely(len != 1 && len != 2 && len != 4)) |
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goto out; |
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addr = get_cfgspace_addr(pc, bus, dev, func, off); |
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if (unlikely(!addr)) |
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goto out; |
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err = -ENOMEM; |
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mmio = ioremap(addr, len); |
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if (!mmio) |
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goto out; |
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|
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if (mips_busprobe32(val, mmio)) { |
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val = 0xffffffff; |
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goto unmap; |
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} |
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val = readl(mmio); |
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val >>= (8 * (off & 3)); |
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|
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switch (len) { |
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case 1: |
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*((u8 *)buf) = (u8)val; |
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break; |
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case 2: |
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*((u16 *)buf) = (u16)val; |
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break; |
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case 4: |
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*((u32 *)buf) = (u32)val; |
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break; |
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} |
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err = 0; |
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unmap: |
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iounmap(mmio); |
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out: |
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return err; |
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} |
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static int ssb_extpci_write_config(struct ssb_pcicore *pc, |
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unsigned int bus, unsigned int dev, |
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unsigned int func, unsigned int off, |
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const void *buf, int len) |
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{ |
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int err = -EINVAL; |
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u32 addr, val = 0; |
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void __iomem *mmio; |
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|
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WARN_ON(!pc->hostmode); |
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if (unlikely(len != 1 && len != 2 && len != 4)) |
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goto out; |
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addr = get_cfgspace_addr(pc, bus, dev, func, off); |
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if (unlikely(!addr)) |
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goto out; |
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err = -ENOMEM; |
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mmio = ioremap(addr, len); |
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if (!mmio) |
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goto out; |
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|
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if (mips_busprobe32(val, mmio)) { |
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val = 0xffffffff; |
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goto unmap; |
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} |
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|
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switch (len) { |
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case 1: |
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val = readl(mmio); |
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val &= ~(0xFF << (8 * (off & 3))); |
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val |= *((const u8 *)buf) << (8 * (off & 3)); |
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break; |
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case 2: |
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val = readl(mmio); |
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val &= ~(0xFFFF << (8 * (off & 3))); |
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val |= *((const u16 *)buf) << (8 * (off & 3)); |
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break; |
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case 4: |
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val = *((const u32 *)buf); |
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break; |
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} |
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writel(val, mmio); |
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err = 0; |
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unmap: |
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iounmap(mmio); |
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out: |
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return err; |
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} |
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static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn, |
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int reg, int size, u32 *val) |
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{ |
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unsigned long flags; |
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int err; |
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spin_lock_irqsave(&cfgspace_lock, flags); |
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err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn), |
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PCI_FUNC(devfn), reg, val, size); |
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spin_unlock_irqrestore(&cfgspace_lock, flags); |
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return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; |
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} |
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static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn, |
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int reg, int size, u32 val) |
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{ |
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unsigned long flags; |
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int err; |
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spin_lock_irqsave(&cfgspace_lock, flags); |
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err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn), |
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PCI_FUNC(devfn), reg, &val, size); |
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spin_unlock_irqrestore(&cfgspace_lock, flags); |
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return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; |
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} |
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static struct pci_ops ssb_pcicore_pciops = { |
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.read = ssb_pcicore_read_config, |
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.write = ssb_pcicore_write_config, |
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}; |
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static struct resource ssb_pcicore_mem_resource = { |
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.name = "SSB PCIcore external memory", |
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.start = SSB_PCI_DMA, |
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.end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1, |
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.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED, |
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}; |
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static struct resource ssb_pcicore_io_resource = { |
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.name = "SSB PCIcore external I/O", |
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.start = 0x100, |
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.end = 0x7FF, |
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.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED, |
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}; |
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static struct pci_controller ssb_pcicore_controller = { |
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.pci_ops = &ssb_pcicore_pciops, |
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.io_resource = &ssb_pcicore_io_resource, |
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.mem_resource = &ssb_pcicore_mem_resource, |
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}; |
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|
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/* This function is called when doing a pci_enable_device(). |
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* We must first check if the device is a device on the PCI-core bridge. */ |
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int ssb_pcicore_plat_dev_init(struct pci_dev *d) |
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{ |
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if (d->bus->ops != &ssb_pcicore_pciops) { |
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/* This is not a device on the PCI-core bridge. */ |
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return -ENODEV; |
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} |
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dev_info(&d->dev, "PCI: Fixing up device %s\n", pci_name(d)); |
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/* Fix up interrupt lines */ |
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d->irq = ssb_mips_irq(extpci_core->dev) + 2; |
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pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); |
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return 0; |
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} |
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/* Early PCI fixup for a device on the PCI-core bridge. */ |
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static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev) |
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{ |
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u8 lat; |
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if (dev->bus->ops != &ssb_pcicore_pciops) { |
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/* This is not a device on the PCI-core bridge. */ |
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return; |
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} |
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if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0) |
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return; |
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dev_info(&dev->dev, "PCI: Fixing up bridge %s\n", pci_name(dev)); |
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/* Enable PCI bridge bus mastering and memory space */ |
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pci_set_master(dev); |
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if (pcibios_enable_device(dev, ~0) < 0) { |
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dev_err(&dev->dev, "PCI: SSB bridge enable failed\n"); |
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return; |
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} |
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/* Enable PCI bridge BAR1 prefetch and burst */ |
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pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3); |
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/* Make sure our latency is high enough to handle the devices behind us */ |
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lat = 168; |
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dev_info(&dev->dev, |
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"PCI: Fixing latency timer of device %s to %u\n", |
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pci_name(dev), lat); |
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
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} |
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DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge); |
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/* PCI device IRQ mapping. */ |
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int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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if (dev->bus->ops != &ssb_pcicore_pciops) { |
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/* This is not a device on the PCI-core bridge. */ |
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return -ENODEV; |
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} |
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return ssb_mips_irq(extpci_core->dev) + 2; |
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} |
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static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) |
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{ |
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u32 val; |
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if (WARN_ON(extpci_core)) |
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return; |
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extpci_core = pc; |
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dev_dbg(pc->dev->dev, "PCIcore in host mode found\n"); |
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/* Reset devices on the external PCI bus */ |
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val = SSB_PCICORE_CTL_RST_OE; |
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val |= SSB_PCICORE_CTL_CLK_OE; |
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pcicore_write32(pc, SSB_PCICORE_CTL, val); |
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val |= SSB_PCICORE_CTL_CLK; /* Clock on */ |
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pcicore_write32(pc, SSB_PCICORE_CTL, val); |
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udelay(150); /* Assertion time demanded by the PCI standard */ |
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val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */ |
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pcicore_write32(pc, SSB_PCICORE_CTL, val); |
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val = SSB_PCICORE_ARBCTL_INTERN; |
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pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); |
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udelay(1); /* Assertion time demanded by the PCI standard */ |
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if (pc->dev->bus->has_cardbus_slot) { |
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dev_dbg(pc->dev->dev, "CardBus slot detected\n"); |
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pc->cardbusmode = 1; |
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/* GPIO 1 resets the bridge */ |
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ssb_gpio_out(pc->dev->bus, 1, 1); |
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ssb_gpio_outen(pc->dev->bus, 1, 1); |
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pcicore_write16(pc, SSB_PCICORE_SPROM(0), |
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pcicore_read16(pc, SSB_PCICORE_SPROM(0)) |
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| 0x0400); |
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} |
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/* 64MB I/O window */ |
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI0, |
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SSB_PCICORE_SBTOPCI_IO); |
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/* 64MB config space */ |
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, |
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SSB_PCICORE_SBTOPCI_CFG0); |
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/* 1GB memory window */ |
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, |
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SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA); |
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/* |
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* Accessing PCI config without a proper delay after devices reset (not |
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* GPIO reset) was causing reboots on WRT300N v1.0 (BCM4704). |
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* Tested delay 850 us lowered reboot chance to 50-80%, 1000 us fixed it |
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* completely. Flushing all writes was also tested but with no luck. |
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* The same problem was reported for WRT350N v1 (BCM4705), so we just |
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* sleep here unconditionally. |
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*/ |
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usleep_range(1000, 2000); |
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|
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/* Enable PCI bridge BAR0 prefetch and burst */ |
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val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
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ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2); |
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/* Clear error conditions */ |
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val = 0; |
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ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2); |
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|
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/* Enable PCI interrupts */ |
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pcicore_write32(pc, SSB_PCICORE_IMASK, |
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SSB_PCICORE_IMASK_INTA); |
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|
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/* Ok, ready to run, register it to the system. |
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* The following needs change, if we want to port hostmode |
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* to non-MIPS platform. */ |
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ssb_pcicore_controller.io_map_base = (unsigned long)ioremap(SSB_PCI_MEM, 0x04000000); |
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set_io_port_base(ssb_pcicore_controller.io_map_base); |
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/* Give some time to the PCI controller to configure itself with the new |
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* values. Not waiting at this point causes crashes of the machine. */ |
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mdelay(10); |
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register_pci_controller(&ssb_pcicore_controller); |
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} |
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static int pcicore_is_in_hostmode(struct ssb_pcicore *pc) |
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{ |
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struct ssb_bus *bus = pc->dev->bus; |
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u16 chipid_top; |
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u32 tmp; |
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|
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chipid_top = (bus->chip_id & 0xFF00); |
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if (chipid_top != 0x4700 && |
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chipid_top != 0x5300) |
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return 0; |
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|
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if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI) |
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return 0; |
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|
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/* The 200-pin BCM4712 package does not bond out PCI. Even when |
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* PCI is bonded out, some boards may leave the pins floating. */ |
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if (bus->chip_id == 0x4712) { |
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if (bus->chip_package == SSB_CHIPPACK_BCM4712S) |
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return 0; |
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if (bus->chip_package == SSB_CHIPPACK_BCM4712M) |
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return 0; |
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} |
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if (bus->chip_id == 0x5350) |
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return 0; |
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|
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return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE))); |
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} |
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#endif /* CONFIG_SSB_PCICORE_HOSTMODE */ |
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|
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/************************************************** |
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* Workarounds. |
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**************************************************/ |
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|
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static void ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc) |
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{ |
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u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0)); |
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if (((tmp & 0xF000) >> 12) != pc->dev->core_index) { |
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tmp &= ~0xF000; |
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tmp |= (pc->dev->core_index << 12); |
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pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp); |
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} |
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} |
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|
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static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc) |
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{ |
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return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80; |
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} |
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|
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static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc) |
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{ |
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const u8 serdes_pll_device = 0x1D; |
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const u8 serdes_rx_device = 0x1F; |
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u16 tmp; |
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|
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ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */, |
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ssb_pcicore_polarity_workaround(pc)); |
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tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */); |
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if (tmp & 0x4000) |
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ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000); |
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} |
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|
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static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc) |
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{ |
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struct ssb_device *pdev = pc->dev; |
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struct ssb_bus *bus = pdev->bus; |
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u32 tmp; |
|
|
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tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); |
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tmp |= SSB_PCICORE_SBTOPCI_PREF; |
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tmp |= SSB_PCICORE_SBTOPCI_BURST; |
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); |
|
|
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if (pdev->id.revision < 5) { |
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tmp = ssb_read32(pdev, SSB_IMCFGLO); |
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tmp &= ~SSB_IMCFGLO_SERTO; |
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tmp |= 2; |
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tmp &= ~SSB_IMCFGLO_REQTO; |
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tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT; |
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ssb_write32(pdev, SSB_IMCFGLO, tmp); |
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ssb_commit_settings(bus); |
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} else if (pdev->id.revision >= 11) { |
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tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); |
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tmp |= SSB_PCICORE_SBTOPCI_MRM; |
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); |
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} |
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} |
|
|
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static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc) |
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{ |
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u32 tmp; |
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u8 rev = pc->dev->id.revision; |
|
|
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if (rev == 0 || rev == 1) { |
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/* TLP Workaround register. */ |
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tmp = ssb_pcie_read(pc, 0x4); |
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tmp |= 0x8; |
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ssb_pcie_write(pc, 0x4, tmp); |
|
} |
|
if (rev == 1) { |
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/* DLLP Link Control register. */ |
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tmp = ssb_pcie_read(pc, 0x100); |
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tmp |= 0x40; |
|
ssb_pcie_write(pc, 0x100, tmp); |
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} |
|
|
|
if (rev == 0) { |
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const u8 serdes_rx_device = 0x1F; |
|
|
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ssb_pcie_mdio_write(pc, serdes_rx_device, |
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2 /* Timer */, 0x8128); |
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ssb_pcie_mdio_write(pc, serdes_rx_device, |
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6 /* CDR */, 0x0100); |
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ssb_pcie_mdio_write(pc, serdes_rx_device, |
|
7 /* CDR BW */, 0x1466); |
|
} else if (rev == 3 || rev == 4 || rev == 5) { |
|
/* TODO: DLLP Power Management Threshold */ |
|
ssb_pcicore_serdes_workaround(pc); |
|
/* TODO: ASPM */ |
|
} else if (rev == 7) { |
|
/* TODO: No PLL down */ |
|
} |
|
|
|
if (rev >= 6) { |
|
/* Miscellaneous Configuration Fixup */ |
|
tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5)); |
|
if (!(tmp & 0x8000)) |
|
pcicore_write16(pc, SSB_PCICORE_SPROM(5), |
|
tmp | 0x8000); |
|
} |
|
} |
|
|
|
/************************************************** |
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* Generic and Clientmode operation code. |
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**************************************************/ |
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static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) |
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{ |
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struct ssb_device *pdev = pc->dev; |
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struct ssb_bus *bus = pdev->bus; |
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if (bus->bustype == SSB_BUSTYPE_PCI) |
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ssb_pcicore_fix_sprom_core_index(pc); |
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/* Disable PCI interrupts. */ |
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ssb_write32(pdev, SSB_INTVEC, 0); |
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/* Additional PCIe always once-executed workarounds */ |
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if (pc->dev->id.coreid == SSB_DEV_PCIE) { |
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ssb_pcicore_serdes_workaround(pc); |
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/* TODO: ASPM */ |
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/* TODO: Clock Request Update */ |
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} |
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} |
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void ssb_pcicore_init(struct ssb_pcicore *pc) |
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{ |
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struct ssb_device *dev = pc->dev; |
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if (!dev) |
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return; |
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if (!ssb_device_is_enabled(dev)) |
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ssb_device_enable(dev, 0); |
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#ifdef CONFIG_SSB_PCICORE_HOSTMODE |
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pc->hostmode = pcicore_is_in_hostmode(pc); |
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if (pc->hostmode) |
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ssb_pcicore_init_hostmode(pc); |
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#endif /* CONFIG_SSB_PCICORE_HOSTMODE */ |
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if (!pc->hostmode) |
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ssb_pcicore_init_clientmode(pc); |
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} |
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static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address) |
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{ |
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pcicore_write32(pc, 0x130, address); |
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return pcicore_read32(pc, 0x134); |
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} |
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static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data) |
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{ |
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pcicore_write32(pc, 0x130, address); |
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pcicore_write32(pc, 0x134, data); |
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} |
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static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy) |
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{ |
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const u16 mdio_control = 0x128; |
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const u16 mdio_data = 0x12C; |
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u32 v; |
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int i; |
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v = (1 << 30); /* Start of Transaction */ |
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v |= (1 << 28); /* Write Transaction */ |
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v |= (1 << 17); /* Turnaround */ |
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v |= (0x1F << 18); |
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v |= (phy << 4); |
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pcicore_write32(pc, mdio_data, v); |
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udelay(10); |
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for (i = 0; i < 200; i++) { |
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v = pcicore_read32(pc, mdio_control); |
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if (v & 0x100 /* Trans complete */) |
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break; |
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msleep(1); |
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} |
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} |
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static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address) |
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{ |
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const u16 mdio_control = 0x128; |
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const u16 mdio_data = 0x12C; |
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int max_retries = 10; |
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u16 ret = 0; |
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u32 v; |
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int i; |
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v = 0x80; /* Enable Preamble Sequence */ |
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v |= 0x2; /* MDIO Clock Divisor */ |
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pcicore_write32(pc, mdio_control, v); |
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if (pc->dev->id.revision >= 10) { |
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max_retries = 200; |
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ssb_pcie_mdio_set_phy(pc, device); |
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} |
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v = (1 << 30); /* Start of Transaction */ |
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v |= (1 << 29); /* Read Transaction */ |
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v |= (1 << 17); /* Turnaround */ |
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if (pc->dev->id.revision < 10) |
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v |= (u32)device << 22; |
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v |= (u32)address << 18; |
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pcicore_write32(pc, mdio_data, v); |
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/* Wait for the device to complete the transaction */ |
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udelay(10); |
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for (i = 0; i < max_retries; i++) { |
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v = pcicore_read32(pc, mdio_control); |
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if (v & 0x100 /* Trans complete */) { |
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udelay(10); |
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ret = pcicore_read32(pc, mdio_data); |
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break; |
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} |
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msleep(1); |
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} |
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pcicore_write32(pc, mdio_control, 0); |
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return ret; |
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} |
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static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, |
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u8 address, u16 data) |
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{ |
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const u16 mdio_control = 0x128; |
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const u16 mdio_data = 0x12C; |
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int max_retries = 10; |
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u32 v; |
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int i; |
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v = 0x80; /* Enable Preamble Sequence */ |
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v |= 0x2; /* MDIO Clock Divisor */ |
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pcicore_write32(pc, mdio_control, v); |
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if (pc->dev->id.revision >= 10) { |
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max_retries = 200; |
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ssb_pcie_mdio_set_phy(pc, device); |
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} |
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v = (1 << 30); /* Start of Transaction */ |
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v |= (1 << 28); /* Write Transaction */ |
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v |= (1 << 17); /* Turnaround */ |
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if (pc->dev->id.revision < 10) |
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v |= (u32)device << 22; |
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v |= (u32)address << 18; |
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v |= data; |
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pcicore_write32(pc, mdio_data, v); |
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/* Wait for the device to complete the transaction */ |
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udelay(10); |
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for (i = 0; i < max_retries; i++) { |
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v = pcicore_read32(pc, mdio_control); |
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if (v & 0x100 /* Trans complete */) |
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break; |
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msleep(1); |
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} |
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pcicore_write32(pc, mdio_control, 0); |
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} |
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int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, |
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struct ssb_device *dev) |
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{ |
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struct ssb_device *pdev = pc->dev; |
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struct ssb_bus *bus; |
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int err = 0; |
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u32 tmp; |
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if (dev->bus->bustype != SSB_BUSTYPE_PCI) { |
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/* This SSB device is not on a PCI host-bus. So the IRQs are |
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* not routed through the PCI core. |
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* So we must not enable routing through the PCI core. */ |
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goto out; |
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} |
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if (!pdev) |
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goto out; |
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bus = pdev->bus; |
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might_sleep_if(pdev->id.coreid != SSB_DEV_PCI); |
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/* Enable interrupts for this device. */ |
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if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) { |
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u32 coremask; |
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/* Calculate the "coremask" for the device. */ |
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coremask = (1 << dev->core_index); |
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WARN_ON(bus->bustype != SSB_BUSTYPE_PCI); |
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err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp); |
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if (err) |
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goto out; |
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tmp |= coremask << 8; |
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err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp); |
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if (err) |
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goto out; |
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} else { |
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u32 intvec; |
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intvec = ssb_read32(pdev, SSB_INTVEC); |
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tmp = ssb_read32(dev, SSB_TPSFLAG); |
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tmp &= SSB_TPSFLAG_BPFLAG; |
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intvec |= (1 << tmp); |
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ssb_write32(pdev, SSB_INTVEC, intvec); |
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} |
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/* Setup PCIcore operation. */ |
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if (pc->setup_done) |
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goto out; |
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if (pdev->id.coreid == SSB_DEV_PCI) { |
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ssb_pcicore_pci_setup_workarounds(pc); |
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} else { |
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WARN_ON(pdev->id.coreid != SSB_DEV_PCIE); |
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ssb_pcicore_pcie_setup_workarounds(pc); |
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} |
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pc->setup_done = 1; |
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out: |
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return err; |
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} |
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EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);
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