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551 lines
14 KiB
551 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2012 - 2014 Allwinner Tech |
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* Pan Nan <[email protected]> |
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* |
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* Copyright (C) 2014 Maxime Ripard |
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* Maxime Ripard <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/spi/spi.h> |
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#define SUN4I_FIFO_DEPTH 64 |
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#define SUN4I_RXDATA_REG 0x00 |
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#define SUN4I_TXDATA_REG 0x04 |
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#define SUN4I_CTL_REG 0x08 |
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#define SUN4I_CTL_ENABLE BIT(0) |
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#define SUN4I_CTL_MASTER BIT(1) |
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#define SUN4I_CTL_CPHA BIT(2) |
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#define SUN4I_CTL_CPOL BIT(3) |
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#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4) |
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#define SUN4I_CTL_LMTF BIT(6) |
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#define SUN4I_CTL_TF_RST BIT(8) |
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#define SUN4I_CTL_RF_RST BIT(9) |
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#define SUN4I_CTL_XCH BIT(10) |
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#define SUN4I_CTL_CS_MASK 0x3000 |
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#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK) |
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#define SUN4I_CTL_DHB BIT(15) |
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#define SUN4I_CTL_CS_MANUAL BIT(16) |
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#define SUN4I_CTL_CS_LEVEL BIT(17) |
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#define SUN4I_CTL_TP BIT(18) |
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#define SUN4I_INT_CTL_REG 0x0c |
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#define SUN4I_INT_CTL_RF_F34 BIT(4) |
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#define SUN4I_INT_CTL_TF_E34 BIT(12) |
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#define SUN4I_INT_CTL_TC BIT(16) |
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#define SUN4I_INT_STA_REG 0x10 |
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#define SUN4I_DMA_CTL_REG 0x14 |
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#define SUN4I_WAIT_REG 0x18 |
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#define SUN4I_CLK_CTL_REG 0x1c |
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#define SUN4I_CLK_CTL_CDR2_MASK 0xff |
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#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK) |
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#define SUN4I_CLK_CTL_CDR1_MASK 0xf |
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#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8) |
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#define SUN4I_CLK_CTL_DRS BIT(12) |
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#define SUN4I_MAX_XFER_SIZE 0xffffff |
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#define SUN4I_BURST_CNT_REG 0x20 |
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#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE) |
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#define SUN4I_XMIT_CNT_REG 0x24 |
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#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE) |
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#define SUN4I_FIFO_STA_REG 0x28 |
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#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f |
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#define SUN4I_FIFO_STA_RF_CNT_BITS 0 |
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#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f |
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#define SUN4I_FIFO_STA_TF_CNT_BITS 16 |
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struct sun4i_spi { |
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struct spi_master *master; |
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void __iomem *base_addr; |
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struct clk *hclk; |
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struct clk *mclk; |
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struct completion done; |
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const u8 *tx_buf; |
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u8 *rx_buf; |
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int len; |
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}; |
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static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg) |
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{ |
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return readl(sspi->base_addr + reg); |
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} |
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static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value) |
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{ |
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writel(value, sspi->base_addr + reg); |
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} |
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static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi) |
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{ |
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u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG); |
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reg >>= SUN4I_FIFO_STA_TF_CNT_BITS; |
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return reg & SUN4I_FIFO_STA_TF_CNT_MASK; |
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} |
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static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask) |
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{ |
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u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG); |
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reg |= mask; |
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sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg); |
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} |
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static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 mask) |
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{ |
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u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG); |
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reg &= ~mask; |
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sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg); |
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} |
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static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len) |
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{ |
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u32 reg, cnt; |
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u8 byte; |
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/* See how much data is available */ |
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reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG); |
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reg &= SUN4I_FIFO_STA_RF_CNT_MASK; |
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cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS; |
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if (len > cnt) |
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len = cnt; |
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while (len--) { |
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byte = readb(sspi->base_addr + SUN4I_RXDATA_REG); |
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if (sspi->rx_buf) |
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*sspi->rx_buf++ = byte; |
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} |
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} |
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static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len) |
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{ |
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u32 cnt; |
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u8 byte; |
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/* See how much data we can fit */ |
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cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi); |
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len = min3(len, (int)cnt, sspi->len); |
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while (len--) { |
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byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; |
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writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG); |
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sspi->len--; |
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} |
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} |
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static void sun4i_spi_set_cs(struct spi_device *spi, bool enable) |
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{ |
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struct sun4i_spi *sspi = spi_master_get_devdata(spi->master); |
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u32 reg; |
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reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); |
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reg &= ~SUN4I_CTL_CS_MASK; |
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reg |= SUN4I_CTL_CS(spi->chip_select); |
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/* We want to control the chip select manually */ |
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reg |= SUN4I_CTL_CS_MANUAL; |
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if (enable) |
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reg |= SUN4I_CTL_CS_LEVEL; |
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else |
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reg &= ~SUN4I_CTL_CS_LEVEL; |
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/* |
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* Even though this looks irrelevant since we are supposed to |
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* be controlling the chip select manually, this bit also |
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* controls the levels of the chip select for inactive |
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* devices. |
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* |
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* If we don't set it, the chip select level will go low by |
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* default when the device is idle, which is not really |
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* expected in the common case where the chip select is active |
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* low. |
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*/ |
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if (spi->mode & SPI_CS_HIGH) |
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reg &= ~SUN4I_CTL_CS_ACTIVE_LOW; |
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else |
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reg |= SUN4I_CTL_CS_ACTIVE_LOW; |
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sun4i_spi_write(sspi, SUN4I_CTL_REG, reg); |
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} |
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static size_t sun4i_spi_max_transfer_size(struct spi_device *spi) |
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{ |
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return SUN4I_MAX_XFER_SIZE - 1; |
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} |
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static int sun4i_spi_transfer_one(struct spi_master *master, |
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struct spi_device *spi, |
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struct spi_transfer *tfr) |
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{ |
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struct sun4i_spi *sspi = spi_master_get_devdata(master); |
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unsigned int mclk_rate, div, timeout; |
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unsigned int start, end, tx_time; |
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unsigned int tx_len = 0; |
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int ret = 0; |
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u32 reg; |
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/* We don't support transfer larger than the FIFO */ |
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if (tfr->len > SUN4I_MAX_XFER_SIZE) |
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return -EMSGSIZE; |
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if (tfr->tx_buf && tfr->len >= SUN4I_MAX_XFER_SIZE) |
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return -EMSGSIZE; |
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reinit_completion(&sspi->done); |
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sspi->tx_buf = tfr->tx_buf; |
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sspi->rx_buf = tfr->rx_buf; |
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sspi->len = tfr->len; |
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/* Clear pending interrupts */ |
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sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0); |
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reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); |
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/* Reset FIFOs */ |
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sun4i_spi_write(sspi, SUN4I_CTL_REG, |
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reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST); |
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/* |
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* Setup the transfer control register: Chip Select, |
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* polarities, etc. |
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*/ |
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if (spi->mode & SPI_CPOL) |
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reg |= SUN4I_CTL_CPOL; |
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else |
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reg &= ~SUN4I_CTL_CPOL; |
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if (spi->mode & SPI_CPHA) |
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reg |= SUN4I_CTL_CPHA; |
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else |
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reg &= ~SUN4I_CTL_CPHA; |
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if (spi->mode & SPI_LSB_FIRST) |
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reg |= SUN4I_CTL_LMTF; |
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else |
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reg &= ~SUN4I_CTL_LMTF; |
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/* |
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* If it's a TX only transfer, we don't want to fill the RX |
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* FIFO with bogus data |
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*/ |
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if (sspi->rx_buf) |
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reg &= ~SUN4I_CTL_DHB; |
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else |
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reg |= SUN4I_CTL_DHB; |
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sun4i_spi_write(sspi, SUN4I_CTL_REG, reg); |
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/* Ensure that we have a parent clock fast enough */ |
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mclk_rate = clk_get_rate(sspi->mclk); |
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if (mclk_rate < (2 * tfr->speed_hz)) { |
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clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); |
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mclk_rate = clk_get_rate(sspi->mclk); |
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} |
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/* |
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* Setup clock divider. |
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* |
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* We have two choices there. Either we can use the clock |
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* divide rate 1, which is calculated thanks to this formula: |
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* SPI_CLK = MOD_CLK / (2 ^ (cdr + 1)) |
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* Or we can use CDR2, which is calculated with the formula: |
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* SPI_CLK = MOD_CLK / (2 * (cdr + 1)) |
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* Wether we use the former or the latter is set through the |
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* DRS bit. |
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* |
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* First try CDR2, and if we can't reach the expected |
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* frequency, fall back to CDR1. |
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*/ |
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div = mclk_rate / (2 * tfr->speed_hz); |
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if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { |
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if (div > 0) |
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div--; |
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reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; |
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} else { |
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div = ilog2(mclk_rate) - ilog2(tfr->speed_hz); |
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reg = SUN4I_CLK_CTL_CDR1(div); |
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} |
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sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg); |
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/* Setup the transfer now... */ |
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if (sspi->tx_buf) |
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tx_len = tfr->len; |
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/* Setup the counters */ |
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sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len)); |
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sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len)); |
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/* |
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* Fill the TX FIFO |
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* Filling the FIFO fully causes timeout for some reason |
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* at least on spi2 on A10s |
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*/ |
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sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1); |
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/* Enable the interrupts */ |
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sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC | |
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SUN4I_INT_CTL_RF_F34); |
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/* Only enable Tx FIFO interrupt if we really need it */ |
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if (tx_len > SUN4I_FIFO_DEPTH) |
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sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34); |
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/* Start the transfer */ |
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reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); |
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sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH); |
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tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); |
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start = jiffies; |
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timeout = wait_for_completion_timeout(&sspi->done, |
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msecs_to_jiffies(tx_time)); |
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end = jiffies; |
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if (!timeout) { |
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dev_warn(&master->dev, |
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"%s: timeout transferring %u bytes@%iHz for %i(%i)ms", |
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dev_name(&spi->dev), tfr->len, tfr->speed_hz, |
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jiffies_to_msecs(end - start), tx_time); |
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ret = -ETIMEDOUT; |
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goto out; |
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} |
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out: |
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sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0); |
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return ret; |
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} |
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static irqreturn_t sun4i_spi_handler(int irq, void *dev_id) |
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{ |
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struct sun4i_spi *sspi = dev_id; |
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u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG); |
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/* Transfer complete */ |
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if (status & SUN4I_INT_CTL_TC) { |
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sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC); |
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sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH); |
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complete(&sspi->done); |
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return IRQ_HANDLED; |
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} |
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/* Receive FIFO 3/4 full */ |
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if (status & SUN4I_INT_CTL_RF_F34) { |
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sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH); |
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/* Only clear the interrupt _after_ draining the FIFO */ |
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sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_RF_F34); |
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return IRQ_HANDLED; |
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} |
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/* Transmit FIFO 3/4 empty */ |
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if (status & SUN4I_INT_CTL_TF_E34) { |
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sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH); |
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if (!sspi->len) |
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/* nothing left to transmit */ |
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sun4i_spi_disable_interrupt(sspi, SUN4I_INT_CTL_TF_E34); |
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/* Only clear the interrupt _after_ re-seeding the FIFO */ |
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sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TF_E34); |
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return IRQ_HANDLED; |
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} |
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return IRQ_NONE; |
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} |
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static int sun4i_spi_runtime_resume(struct device *dev) |
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{ |
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struct spi_master *master = dev_get_drvdata(dev); |
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struct sun4i_spi *sspi = spi_master_get_devdata(master); |
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int ret; |
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ret = clk_prepare_enable(sspi->hclk); |
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if (ret) { |
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dev_err(dev, "Couldn't enable AHB clock\n"); |
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goto out; |
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} |
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ret = clk_prepare_enable(sspi->mclk); |
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if (ret) { |
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dev_err(dev, "Couldn't enable module clock\n"); |
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goto err; |
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} |
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sun4i_spi_write(sspi, SUN4I_CTL_REG, |
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SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP); |
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return 0; |
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err: |
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clk_disable_unprepare(sspi->hclk); |
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out: |
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return ret; |
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} |
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static int sun4i_spi_runtime_suspend(struct device *dev) |
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{ |
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struct spi_master *master = dev_get_drvdata(dev); |
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struct sun4i_spi *sspi = spi_master_get_devdata(master); |
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clk_disable_unprepare(sspi->mclk); |
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clk_disable_unprepare(sspi->hclk); |
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return 0; |
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} |
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static int sun4i_spi_probe(struct platform_device *pdev) |
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{ |
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struct spi_master *master; |
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struct sun4i_spi *sspi; |
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int ret = 0, irq; |
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master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi)); |
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if (!master) { |
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dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); |
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return -ENOMEM; |
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} |
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platform_set_drvdata(pdev, master); |
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sspi = spi_master_get_devdata(master); |
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sspi->base_addr = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(sspi->base_addr)) { |
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ret = PTR_ERR(sspi->base_addr); |
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goto err_free_master; |
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} |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) { |
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ret = -ENXIO; |
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goto err_free_master; |
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} |
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ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler, |
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0, "sun4i-spi", sspi); |
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if (ret) { |
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dev_err(&pdev->dev, "Cannot request IRQ\n"); |
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goto err_free_master; |
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} |
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sspi->master = master; |
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master->max_speed_hz = 100 * 1000 * 1000; |
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master->min_speed_hz = 3 * 1000; |
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master->set_cs = sun4i_spi_set_cs; |
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master->transfer_one = sun4i_spi_transfer_one; |
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master->num_chipselect = 4; |
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; |
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master->bits_per_word_mask = SPI_BPW_MASK(8); |
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master->dev.of_node = pdev->dev.of_node; |
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master->auto_runtime_pm = true; |
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master->max_transfer_size = sun4i_spi_max_transfer_size; |
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sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); |
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if (IS_ERR(sspi->hclk)) { |
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dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); |
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ret = PTR_ERR(sspi->hclk); |
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goto err_free_master; |
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} |
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sspi->mclk = devm_clk_get(&pdev->dev, "mod"); |
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if (IS_ERR(sspi->mclk)) { |
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dev_err(&pdev->dev, "Unable to acquire module clock\n"); |
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ret = PTR_ERR(sspi->mclk); |
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goto err_free_master; |
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} |
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init_completion(&sspi->done); |
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/* |
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* This wake-up/shutdown pattern is to be able to have the |
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* device woken up, even if runtime_pm is disabled |
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*/ |
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ret = sun4i_spi_runtime_resume(&pdev->dev); |
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if (ret) { |
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dev_err(&pdev->dev, "Couldn't resume the device\n"); |
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goto err_free_master; |
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} |
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pm_runtime_set_active(&pdev->dev); |
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pm_runtime_enable(&pdev->dev); |
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pm_runtime_idle(&pdev->dev); |
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ret = devm_spi_register_master(&pdev->dev, master); |
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if (ret) { |
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dev_err(&pdev->dev, "cannot register SPI master\n"); |
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goto err_pm_disable; |
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} |
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return 0; |
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err_pm_disable: |
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pm_runtime_disable(&pdev->dev); |
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sun4i_spi_runtime_suspend(&pdev->dev); |
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err_free_master: |
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spi_master_put(master); |
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return ret; |
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} |
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static int sun4i_spi_remove(struct platform_device *pdev) |
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{ |
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pm_runtime_force_suspend(&pdev->dev); |
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return 0; |
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} |
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static const struct of_device_id sun4i_spi_match[] = { |
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{ .compatible = "allwinner,sun4i-a10-spi", }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, sun4i_spi_match); |
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static const struct dev_pm_ops sun4i_spi_pm_ops = { |
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.runtime_resume = sun4i_spi_runtime_resume, |
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.runtime_suspend = sun4i_spi_runtime_suspend, |
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}; |
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static struct platform_driver sun4i_spi_driver = { |
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.probe = sun4i_spi_probe, |
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.remove = sun4i_spi_remove, |
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.driver = { |
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.name = "sun4i-spi", |
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.of_match_table = sun4i_spi_match, |
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.pm = &sun4i_spi_pm_ops, |
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}, |
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}; |
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module_platform_driver(sun4i_spi_driver); |
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MODULE_AUTHOR("Pan Nan <[email protected]>"); |
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MODULE_AUTHOR("Maxime Ripard <[email protected]>"); |
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MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver"); |
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MODULE_LICENSE("GPL");
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