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572 lines
15 KiB
572 lines
15 KiB
/* |
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* Copyright (C) 2017 Spreadtrum Communications Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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#include <linux/delay.h> |
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#include <linux/hwspinlock.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/reboot.h> |
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#include <linux/spi/spi.h> |
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#include <linux/sizes.h> |
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|
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/* Registers definitions for ADI controller */ |
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#define REG_ADI_CTRL0 0x4 |
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#define REG_ADI_CHN_PRIL 0x8 |
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#define REG_ADI_CHN_PRIH 0xc |
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#define REG_ADI_INT_EN 0x10 |
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#define REG_ADI_INT_RAW 0x14 |
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#define REG_ADI_INT_MASK 0x18 |
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#define REG_ADI_INT_CLR 0x1c |
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#define REG_ADI_GSSI_CFG0 0x20 |
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#define REG_ADI_GSSI_CFG1 0x24 |
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#define REG_ADI_RD_CMD 0x28 |
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#define REG_ADI_RD_DATA 0x2c |
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#define REG_ADI_ARM_FIFO_STS 0x30 |
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#define REG_ADI_STS 0x34 |
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#define REG_ADI_EVT_FIFO_STS 0x38 |
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#define REG_ADI_ARM_CMD_STS 0x3c |
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#define REG_ADI_CHN_EN 0x40 |
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#define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4) |
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#define REG_ADI_CHN_EN1 0x20c |
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/* Bits definitions for register REG_ADI_GSSI_CFG0 */ |
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#define BIT_CLK_ALL_ON BIT(30) |
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|
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/* Bits definitions for register REG_ADI_RD_DATA */ |
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#define BIT_RD_CMD_BUSY BIT(31) |
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#define RD_ADDR_SHIFT 16 |
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#define RD_VALUE_MASK GENMASK(15, 0) |
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#define RD_ADDR_MASK GENMASK(30, 16) |
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/* Bits definitions for register REG_ADI_ARM_FIFO_STS */ |
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#define BIT_FIFO_FULL BIT(11) |
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#define BIT_FIFO_EMPTY BIT(10) |
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/* |
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* ADI slave devices include RTC, ADC, regulator, charger, thermal and so on. |
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* The slave devices address offset is always 0x8000 and size is 4K. |
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*/ |
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#define ADI_SLAVE_ADDR_SIZE SZ_4K |
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#define ADI_SLAVE_OFFSET 0x8000 |
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|
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/* Timeout (ms) for the trylock of hardware spinlocks */ |
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#define ADI_HWSPINLOCK_TIMEOUT 5000 |
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/* |
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* ADI controller has 50 channels including 2 software channels |
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* and 48 hardware channels. |
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*/ |
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#define ADI_HW_CHNS 50 |
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#define ADI_FIFO_DRAIN_TIMEOUT 1000 |
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#define ADI_READ_TIMEOUT 2000 |
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#define REG_ADDR_LOW_MASK GENMASK(11, 0) |
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/* Registers definitions for PMIC watchdog controller */ |
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#define REG_WDG_LOAD_LOW 0x80 |
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#define REG_WDG_LOAD_HIGH 0x84 |
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#define REG_WDG_CTRL 0x88 |
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#define REG_WDG_LOCK 0xa0 |
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|
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/* Bits definitions for register REG_WDG_CTRL */ |
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#define BIT_WDG_RUN BIT(1) |
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#define BIT_WDG_NEW BIT(2) |
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#define BIT_WDG_RST BIT(3) |
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|
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/* Registers definitions for PMIC */ |
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#define PMIC_RST_STATUS 0xee8 |
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#define PMIC_MODULE_EN 0xc08 |
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#define PMIC_CLK_EN 0xc18 |
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#define BIT_WDG_EN BIT(2) |
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|
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/* Definition of PMIC reset status register */ |
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#define HWRST_STATUS_SECURITY 0x02 |
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#define HWRST_STATUS_RECOVERY 0x20 |
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#define HWRST_STATUS_NORMAL 0x40 |
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#define HWRST_STATUS_ALARM 0x50 |
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#define HWRST_STATUS_SLEEP 0x60 |
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#define HWRST_STATUS_FASTBOOT 0x30 |
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#define HWRST_STATUS_SPECIAL 0x70 |
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#define HWRST_STATUS_PANIC 0x80 |
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#define HWRST_STATUS_CFTREBOOT 0x90 |
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#define HWRST_STATUS_AUTODLOADER 0xa0 |
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#define HWRST_STATUS_IQMODE 0xb0 |
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#define HWRST_STATUS_SPRDISK 0xc0 |
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#define HWRST_STATUS_FACTORYTEST 0xe0 |
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#define HWRST_STATUS_WATCHDOG 0xf0 |
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/* Use default timeout 50 ms that converts to watchdog values */ |
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#define WDG_LOAD_VAL ((50 * 1000) / 32768) |
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#define WDG_LOAD_MASK GENMASK(15, 0) |
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#define WDG_UNLOCK_KEY 0xe551 |
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struct sprd_adi { |
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struct spi_controller *ctlr; |
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struct device *dev; |
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void __iomem *base; |
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struct hwspinlock *hwlock; |
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unsigned long slave_vbase; |
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unsigned long slave_pbase; |
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struct notifier_block restart_handler; |
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}; |
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static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr) |
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{ |
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if (paddr < sadi->slave_pbase || paddr > |
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(sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) { |
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dev_err(sadi->dev, |
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"slave physical address is incorrect, addr = 0x%x\n", |
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paddr); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr) |
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{ |
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return (paddr - sadi->slave_pbase + sadi->slave_vbase); |
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} |
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static int sprd_adi_drain_fifo(struct sprd_adi *sadi) |
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{ |
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u32 timeout = ADI_FIFO_DRAIN_TIMEOUT; |
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u32 sts; |
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do { |
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sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS); |
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if (sts & BIT_FIFO_EMPTY) |
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break; |
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cpu_relax(); |
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} while (--timeout); |
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if (timeout == 0) { |
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dev_err(sadi->dev, "drain write fifo timeout\n"); |
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return -EBUSY; |
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} |
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return 0; |
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} |
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static int sprd_adi_fifo_is_full(struct sprd_adi *sadi) |
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{ |
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return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL; |
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} |
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static int sprd_adi_read(struct sprd_adi *sadi, u32 reg_paddr, u32 *read_val) |
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{ |
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int read_timeout = ADI_READ_TIMEOUT; |
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unsigned long flags; |
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u32 val, rd_addr; |
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int ret = 0; |
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if (sadi->hwlock) { |
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ret = hwspin_lock_timeout_irqsave(sadi->hwlock, |
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ADI_HWSPINLOCK_TIMEOUT, |
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&flags); |
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if (ret) { |
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dev_err(sadi->dev, "get the hw lock failed\n"); |
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return ret; |
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} |
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} |
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/* |
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* Set the physical register address need to read into RD_CMD register, |
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* then ADI controller will start to transfer automatically. |
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*/ |
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writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD); |
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/* |
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* Wait read operation complete, the BIT_RD_CMD_BUSY will be set |
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* simultaneously when writing read command to register, and the |
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* BIT_RD_CMD_BUSY will be cleared after the read operation is |
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* completed. |
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*/ |
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do { |
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val = readl_relaxed(sadi->base + REG_ADI_RD_DATA); |
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if (!(val & BIT_RD_CMD_BUSY)) |
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break; |
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cpu_relax(); |
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} while (--read_timeout); |
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if (read_timeout == 0) { |
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dev_err(sadi->dev, "ADI read timeout\n"); |
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ret = -EBUSY; |
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goto out; |
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} |
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/* |
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* The return value includes data and read register address, from bit 0 |
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* to bit 15 are data, and from bit 16 to bit 30 are read register |
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* address. Then we can check the returned register address to validate |
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* data. |
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*/ |
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rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT; |
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if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) { |
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dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n", |
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reg_paddr, val); |
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ret = -EIO; |
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goto out; |
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} |
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*read_val = val & RD_VALUE_MASK; |
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out: |
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if (sadi->hwlock) |
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hwspin_unlock_irqrestore(sadi->hwlock, &flags); |
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return ret; |
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} |
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static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val) |
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{ |
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unsigned long reg = sprd_adi_to_vaddr(sadi, reg_paddr); |
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u32 timeout = ADI_FIFO_DRAIN_TIMEOUT; |
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unsigned long flags; |
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int ret; |
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if (sadi->hwlock) { |
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ret = hwspin_lock_timeout_irqsave(sadi->hwlock, |
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ADI_HWSPINLOCK_TIMEOUT, |
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&flags); |
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if (ret) { |
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dev_err(sadi->dev, "get the hw lock failed\n"); |
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return ret; |
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} |
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} |
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ret = sprd_adi_drain_fifo(sadi); |
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if (ret < 0) |
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goto out; |
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/* |
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* we should wait for write fifo is empty before writing data to PMIC |
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* registers. |
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*/ |
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do { |
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if (!sprd_adi_fifo_is_full(sadi)) { |
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writel_relaxed(val, (void __iomem *)reg); |
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break; |
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} |
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cpu_relax(); |
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} while (--timeout); |
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if (timeout == 0) { |
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dev_err(sadi->dev, "write fifo is full\n"); |
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ret = -EBUSY; |
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} |
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out: |
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if (sadi->hwlock) |
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hwspin_unlock_irqrestore(sadi->hwlock, &flags); |
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return ret; |
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} |
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static int sprd_adi_transfer_one(struct spi_controller *ctlr, |
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struct spi_device *spi_dev, |
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struct spi_transfer *t) |
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{ |
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struct sprd_adi *sadi = spi_controller_get_devdata(ctlr); |
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u32 phy_reg, val; |
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int ret; |
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if (t->rx_buf) { |
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phy_reg = *(u32 *)t->rx_buf + sadi->slave_pbase; |
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ret = sprd_adi_check_paddr(sadi, phy_reg); |
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if (ret) |
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return ret; |
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ret = sprd_adi_read(sadi, phy_reg, &val); |
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if (ret) |
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return ret; |
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*(u32 *)t->rx_buf = val; |
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} else if (t->tx_buf) { |
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u32 *p = (u32 *)t->tx_buf; |
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/* |
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* Get the physical register address need to write and convert |
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* the physical address to virtual address. Since we need |
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* virtual register address to write. |
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*/ |
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phy_reg = *p++ + sadi->slave_pbase; |
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ret = sprd_adi_check_paddr(sadi, phy_reg); |
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if (ret) |
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return ret; |
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val = *p; |
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ret = sprd_adi_write(sadi, phy_reg, val); |
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if (ret) |
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return ret; |
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} else { |
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dev_err(sadi->dev, "no buffer for transfer\n"); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static void sprd_adi_set_wdt_rst_mode(struct sprd_adi *sadi) |
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{ |
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#if IS_ENABLED(CONFIG_SPRD_WATCHDOG) |
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u32 val; |
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/* Set default watchdog reboot mode */ |
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sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val); |
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val |= HWRST_STATUS_WATCHDOG; |
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sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val); |
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#endif |
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} |
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static int sprd_adi_restart_handler(struct notifier_block *this, |
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unsigned long mode, void *cmd) |
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{ |
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struct sprd_adi *sadi = container_of(this, struct sprd_adi, |
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restart_handler); |
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u32 val, reboot_mode = 0; |
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if (!cmd) |
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reboot_mode = HWRST_STATUS_NORMAL; |
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else if (!strncmp(cmd, "recovery", 8)) |
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reboot_mode = HWRST_STATUS_RECOVERY; |
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else if (!strncmp(cmd, "alarm", 5)) |
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reboot_mode = HWRST_STATUS_ALARM; |
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else if (!strncmp(cmd, "fastsleep", 9)) |
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reboot_mode = HWRST_STATUS_SLEEP; |
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else if (!strncmp(cmd, "bootloader", 10)) |
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reboot_mode = HWRST_STATUS_FASTBOOT; |
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else if (!strncmp(cmd, "panic", 5)) |
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reboot_mode = HWRST_STATUS_PANIC; |
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else if (!strncmp(cmd, "special", 7)) |
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reboot_mode = HWRST_STATUS_SPECIAL; |
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else if (!strncmp(cmd, "cftreboot", 9)) |
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reboot_mode = HWRST_STATUS_CFTREBOOT; |
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else if (!strncmp(cmd, "autodloader", 11)) |
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reboot_mode = HWRST_STATUS_AUTODLOADER; |
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else if (!strncmp(cmd, "iqmode", 6)) |
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reboot_mode = HWRST_STATUS_IQMODE; |
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else if (!strncmp(cmd, "sprdisk", 7)) |
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reboot_mode = HWRST_STATUS_SPRDISK; |
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else if (!strncmp(cmd, "tospanic", 8)) |
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reboot_mode = HWRST_STATUS_SECURITY; |
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else if (!strncmp(cmd, "factorytest", 11)) |
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reboot_mode = HWRST_STATUS_FACTORYTEST; |
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else |
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reboot_mode = HWRST_STATUS_NORMAL; |
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/* Record the reboot mode */ |
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sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val); |
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val &= ~HWRST_STATUS_WATCHDOG; |
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val |= reboot_mode; |
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sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val); |
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|
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/* Enable the interface clock of the watchdog */ |
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sprd_adi_read(sadi, sadi->slave_pbase + PMIC_MODULE_EN, &val); |
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val |= BIT_WDG_EN; |
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sprd_adi_write(sadi, sadi->slave_pbase + PMIC_MODULE_EN, val); |
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|
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/* Enable the work clock of the watchdog */ |
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sprd_adi_read(sadi, sadi->slave_pbase + PMIC_CLK_EN, &val); |
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val |= BIT_WDG_EN; |
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sprd_adi_write(sadi, sadi->slave_pbase + PMIC_CLK_EN, val); |
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|
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/* Unlock the watchdog */ |
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sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, WDG_UNLOCK_KEY); |
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sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val); |
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val |= BIT_WDG_NEW; |
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sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val); |
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|
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/* Load the watchdog timeout value, 50ms is always enough. */ |
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sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0); |
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sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW, |
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WDG_LOAD_VAL & WDG_LOAD_MASK); |
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|
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/* Start the watchdog to reset system */ |
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sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val); |
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val |= BIT_WDG_RUN | BIT_WDG_RST; |
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sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val); |
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|
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/* Lock the watchdog */ |
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sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, ~WDG_UNLOCK_KEY); |
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mdelay(1000); |
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dev_emerg(sadi->dev, "Unable to restart system\n"); |
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return NOTIFY_DONE; |
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} |
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static void sprd_adi_hw_init(struct sprd_adi *sadi) |
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{ |
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struct device_node *np = sadi->dev->of_node; |
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int i, size, chn_cnt; |
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const __be32 *list; |
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u32 tmp; |
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|
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/* Set all channels as default priority */ |
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writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL); |
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writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH); |
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|
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/* Set clock auto gate mode */ |
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tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0); |
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tmp &= ~BIT_CLK_ALL_ON; |
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writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0); |
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|
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/* Set hardware channels setting */ |
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list = of_get_property(np, "sprd,hw-channels", &size); |
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if (!list || !size) { |
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dev_info(sadi->dev, "no hw channels setting in node\n"); |
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return; |
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} |
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chn_cnt = size / 8; |
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for (i = 0; i < chn_cnt; i++) { |
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u32 value; |
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u32 chn_id = be32_to_cpu(*list++); |
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u32 chn_config = be32_to_cpu(*list++); |
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|
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/* Channel 0 and 1 are software channels */ |
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if (chn_id < 2) |
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continue; |
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writel_relaxed(chn_config, sadi->base + |
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REG_ADI_CHN_ADDR(chn_id)); |
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if (chn_id < 32) { |
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value = readl_relaxed(sadi->base + REG_ADI_CHN_EN); |
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value |= BIT(chn_id); |
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writel_relaxed(value, sadi->base + REG_ADI_CHN_EN); |
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} else if (chn_id < ADI_HW_CHNS) { |
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value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1); |
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value |= BIT(chn_id - 32); |
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writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1); |
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} |
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} |
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} |
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static int sprd_adi_probe(struct platform_device *pdev) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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struct spi_controller *ctlr; |
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struct sprd_adi *sadi; |
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struct resource *res; |
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u32 num_chipselect; |
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int ret; |
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|
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if (!np) { |
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dev_err(&pdev->dev, "can not find the adi bus node\n"); |
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return -ENODEV; |
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} |
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|
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pdev->id = of_alias_get_id(np, "spi"); |
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num_chipselect = of_get_child_count(np); |
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|
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ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi)); |
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if (!ctlr) |
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return -ENOMEM; |
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|
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dev_set_drvdata(&pdev->dev, ctlr); |
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sadi = spi_controller_get_devdata(ctlr); |
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|
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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sadi->base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(sadi->base)) { |
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ret = PTR_ERR(sadi->base); |
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goto put_ctlr; |
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} |
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sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET; |
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sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET; |
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sadi->ctlr = ctlr; |
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sadi->dev = &pdev->dev; |
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ret = of_hwspin_lock_get_id(np, 0); |
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if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) { |
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sadi->hwlock = |
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devm_hwspin_lock_request_specific(&pdev->dev, ret); |
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if (!sadi->hwlock) { |
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ret = -ENXIO; |
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goto put_ctlr; |
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} |
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} else { |
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switch (ret) { |
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case -ENOENT: |
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dev_info(&pdev->dev, "no hardware spinlock supplied\n"); |
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break; |
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default: |
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dev_err_probe(&pdev->dev, ret, "failed to find hwlock id\n"); |
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goto put_ctlr; |
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} |
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} |
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|
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sprd_adi_hw_init(sadi); |
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sprd_adi_set_wdt_rst_mode(sadi); |
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|
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ctlr->dev.of_node = pdev->dev.of_node; |
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ctlr->bus_num = pdev->id; |
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ctlr->num_chipselect = num_chipselect; |
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ctlr->flags = SPI_MASTER_HALF_DUPLEX; |
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ctlr->bits_per_word_mask = 0; |
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ctlr->transfer_one = sprd_adi_transfer_one; |
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|
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ret = devm_spi_register_controller(&pdev->dev, ctlr); |
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if (ret) { |
|
dev_err(&pdev->dev, "failed to register SPI controller\n"); |
|
goto put_ctlr; |
|
} |
|
|
|
sadi->restart_handler.notifier_call = sprd_adi_restart_handler; |
|
sadi->restart_handler.priority = 128; |
|
ret = register_restart_handler(&sadi->restart_handler); |
|
if (ret) { |
|
dev_err(&pdev->dev, "can not register restart handler\n"); |
|
goto put_ctlr; |
|
} |
|
|
|
return 0; |
|
|
|
put_ctlr: |
|
spi_controller_put(ctlr); |
|
return ret; |
|
} |
|
|
|
static int sprd_adi_remove(struct platform_device *pdev) |
|
{ |
|
struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev); |
|
struct sprd_adi *sadi = spi_controller_get_devdata(ctlr); |
|
|
|
unregister_restart_handler(&sadi->restart_handler); |
|
return 0; |
|
} |
|
|
|
static const struct of_device_id sprd_adi_of_match[] = { |
|
{ |
|
.compatible = "sprd,sc9860-adi", |
|
}, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, sprd_adi_of_match); |
|
|
|
static struct platform_driver sprd_adi_driver = { |
|
.driver = { |
|
.name = "sprd-adi", |
|
.of_match_table = sprd_adi_of_match, |
|
}, |
|
.probe = sprd_adi_probe, |
|
.remove = sprd_adi_remove, |
|
}; |
|
module_platform_driver(sprd_adi_driver); |
|
|
|
MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver"); |
|
MODULE_AUTHOR("Baolin Wang <[email protected]>"); |
|
MODULE_LICENSE("GPL v2");
|
|
|