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254 lines
5.8 KiB
254 lines
5.8 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Marvell 88SE64xx/88SE94xx register IO interface |
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* |
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* Copyright 2007 Red Hat, Inc. |
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* Copyright 2008 Marvell. <[email protected]> |
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* Copyright 2009-2011 Marvell. <[email protected]> |
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*/ |
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#ifndef _MV_CHIPS_H_ |
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#define _MV_CHIPS_H_ |
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#define mr32(reg) readl(regs + reg) |
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#define mw32(reg, val) writel((val), regs + reg) |
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#define mw32_f(reg, val) do { \ |
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mw32(reg, val); \ |
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mr32(reg); \ |
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} while (0) |
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#define iow32(reg, val) outl(val, (unsigned long)(regs + reg)) |
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#define ior32(reg) inl((unsigned long)(regs + reg)) |
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#define iow16(reg, val) outw((unsigned long)(val, regs + reg)) |
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#define ior16(reg) inw((unsigned long)(regs + reg)) |
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#define iow8(reg, val) outb((unsigned long)(val, regs + reg)) |
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#define ior8(reg) inb((unsigned long)(regs + reg)) |
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static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr) |
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{ |
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void __iomem *regs = mvi->regs; |
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mw32(MVS_CMD_ADDR, addr); |
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return mr32(MVS_CMD_DATA); |
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} |
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static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val) |
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{ |
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void __iomem *regs = mvi->regs; |
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mw32(MVS_CMD_ADDR, addr); |
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mw32(MVS_CMD_DATA, val); |
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} |
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static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port) |
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{ |
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void __iomem *regs = mvi->regs; |
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return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) : |
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mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4); |
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} |
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static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val) |
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{ |
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void __iomem *regs = mvi->regs; |
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if (port < 4) |
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mw32(MVS_P0_SER_CTLSTAT + port * 4, val); |
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else |
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mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val); |
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} |
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static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off, |
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u32 off2, u32 port) |
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{ |
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void __iomem *regs = mvi->regs + off; |
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void __iomem *regs2 = mvi->regs + off2; |
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return (port < 4) ? readl(regs + port * 8) : |
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readl(regs2 + (port - 4) * 8); |
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} |
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static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2, |
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u32 port, u32 val) |
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{ |
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void __iomem *regs = mvi->regs + off; |
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void __iomem *regs2 = mvi->regs + off2; |
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if (port < 4) |
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writel(val, regs + port * 8); |
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else |
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writel(val, regs2 + (port - 4) * 8); |
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} |
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static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port) |
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{ |
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return mvs_read_port(mvi, MVS_P0_CFG_DATA, |
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MVS_P4_CFG_DATA, port); |
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} |
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static inline void mvs_write_port_cfg_data(struct mvs_info *mvi, |
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u32 port, u32 val) |
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{ |
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mvs_write_port(mvi, MVS_P0_CFG_DATA, |
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MVS_P4_CFG_DATA, port, val); |
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} |
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static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi, |
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u32 port, u32 addr) |
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{ |
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mvs_write_port(mvi, MVS_P0_CFG_ADDR, |
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MVS_P4_CFG_ADDR, port, addr); |
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mdelay(10); |
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} |
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static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port) |
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{ |
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return mvs_read_port(mvi, MVS_P0_VSR_DATA, |
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MVS_P4_VSR_DATA, port); |
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} |
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static inline void mvs_write_port_vsr_data(struct mvs_info *mvi, |
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u32 port, u32 val) |
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{ |
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mvs_write_port(mvi, MVS_P0_VSR_DATA, |
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MVS_P4_VSR_DATA, port, val); |
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} |
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static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi, |
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u32 port, u32 addr) |
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{ |
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mvs_write_port(mvi, MVS_P0_VSR_ADDR, |
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MVS_P4_VSR_ADDR, port, addr); |
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mdelay(10); |
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} |
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static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port) |
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{ |
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return mvs_read_port(mvi, MVS_P0_INT_STAT, |
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MVS_P4_INT_STAT, port); |
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} |
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static inline void mvs_write_port_irq_stat(struct mvs_info *mvi, |
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u32 port, u32 val) |
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{ |
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mvs_write_port(mvi, MVS_P0_INT_STAT, |
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MVS_P4_INT_STAT, port, val); |
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} |
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static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port) |
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{ |
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return mvs_read_port(mvi, MVS_P0_INT_MASK, |
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MVS_P4_INT_MASK, port); |
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} |
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static inline void mvs_write_port_irq_mask(struct mvs_info *mvi, |
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u32 port, u32 val) |
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{ |
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mvs_write_port(mvi, MVS_P0_INT_MASK, |
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MVS_P4_INT_MASK, port, val); |
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} |
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static inline void mvs_phy_hacks(struct mvs_info *mvi) |
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{ |
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u32 tmp; |
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tmp = mvs_cr32(mvi, CMD_PHY_TIMER); |
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tmp &= ~(1 << 9); |
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tmp |= (1 << 10); |
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mvs_cw32(mvi, CMD_PHY_TIMER, tmp); |
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/* enable retry 127 times */ |
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mvs_cw32(mvi, CMD_SAS_CTL1, 0x7f7f); |
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/* extend open frame timeout to max */ |
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tmp = mvs_cr32(mvi, CMD_SAS_CTL0); |
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tmp &= ~0xffff; |
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tmp |= 0x3fff; |
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mvs_cw32(mvi, CMD_SAS_CTL0, tmp); |
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mvs_cw32(mvi, CMD_WD_TIMER, 0x7a0000); |
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/* not to halt for different port op during wideport link change */ |
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mvs_cw32(mvi, CMD_APP_ERR_CONFIG, 0xffefbf7d); |
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} |
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static inline void mvs_int_sata(struct mvs_info *mvi) |
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{ |
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u32 tmp; |
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void __iomem *regs = mvi->regs; |
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tmp = mr32(MVS_INT_STAT_SRS_0); |
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if (tmp) |
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mw32(MVS_INT_STAT_SRS_0, tmp); |
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MVS_CHIP_DISP->clear_active_cmds(mvi); |
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} |
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static inline void mvs_int_full(struct mvs_info *mvi) |
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{ |
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void __iomem *regs = mvi->regs; |
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u32 tmp, stat; |
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int i; |
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stat = mr32(MVS_INT_STAT); |
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mvs_int_rx(mvi, false); |
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for (i = 0; i < mvi->chip->n_phy; i++) { |
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tmp = (stat >> i) & (CINT_PORT | CINT_PORT_STOPPED); |
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if (tmp) |
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mvs_int_port(mvi, i, tmp); |
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} |
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if (stat & CINT_NON_SPEC_NCQ_ERROR) |
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MVS_CHIP_DISP->non_spec_ncq_error(mvi); |
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if (stat & CINT_SRS) |
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mvs_int_sata(mvi); |
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mw32(MVS_INT_STAT, stat); |
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} |
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static inline void mvs_start_delivery(struct mvs_info *mvi, u32 tx) |
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{ |
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void __iomem *regs = mvi->regs; |
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mw32(MVS_TX_PROD_IDX, tx); |
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} |
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static inline u32 mvs_rx_update(struct mvs_info *mvi) |
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{ |
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void __iomem *regs = mvi->regs; |
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return mr32(MVS_RX_CONS_IDX); |
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} |
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static inline u32 mvs_get_prd_size(void) |
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{ |
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return sizeof(struct mvs_prd); |
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} |
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static inline u32 mvs_get_prd_count(void) |
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{ |
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return MAX_SG_ENTRY; |
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} |
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static inline void mvs_show_pcie_usage(struct mvs_info *mvi) |
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{ |
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u16 link_stat, link_spd; |
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const char *spd[] = { |
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"UnKnown", |
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"2.5", |
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"5.0", |
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}; |
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if (mvi->flags & MVF_FLAG_SOC || mvi->id > 0) |
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return; |
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pci_read_config_word(mvi->pdev, PCR_LINK_STAT, &link_stat); |
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link_spd = (link_stat & PLS_LINK_SPD) >> PLS_LINK_SPD_OFFS; |
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if (link_spd >= 3) |
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link_spd = 0; |
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dev_printk(KERN_INFO, mvi->dev, |
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"mvsas: PCI-E x%u, Bandwidth Usage: %s Gbps\n", |
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(link_stat & PLS_NEG_LINK_WD) >> PLS_NEG_LINK_WD_OFFS, |
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spd[link_spd]); |
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} |
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static inline u32 mvs_hw_max_link_rate(void) |
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{ |
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return MAX_LINK_RATE; |
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} |
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#endif /* _MV_CHIPS_H_ */ |
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