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129 lines
3.2 KiB
129 lines
3.2 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* CXL Flash Device Driver |
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* |
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* Written by: Manoj N. Kumar <[email protected]>, IBM Corporation |
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* Matthew R. Ochs <[email protected]>, IBM Corporation |
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* |
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* Copyright (C) 2015 IBM Corporation |
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*/ |
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#ifndef _CXLFLASH_MAIN_H |
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#define _CXLFLASH_MAIN_H |
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#include <linux/list.h> |
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#include <linux/types.h> |
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#include <scsi/scsi.h> |
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#include <scsi/scsi_device.h> |
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#include "backend.h" |
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#define CXLFLASH_NAME "cxlflash" |
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#define CXLFLASH_ADAPTER_NAME "IBM POWER CXL Flash Adapter" |
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#define CXLFLASH_MAX_ADAPTERS 32 |
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#define PCI_DEVICE_ID_IBM_CORSA 0x04F0 |
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#define PCI_DEVICE_ID_IBM_FLASH_GT 0x0600 |
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#define PCI_DEVICE_ID_IBM_BRIARD 0x0624 |
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/* Since there is only one target, make it 0 */ |
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#define CXLFLASH_TARGET 0 |
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#define CXLFLASH_MAX_CDB_LEN 16 |
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/* Really only one target per bus since the Texan is directly attached */ |
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#define CXLFLASH_MAX_NUM_TARGETS_PER_BUS 1 |
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#define CXLFLASH_MAX_NUM_LUNS_PER_TARGET 65536 |
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#define CXLFLASH_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ) |
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/* FC defines */ |
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#define FC_MTIP_CMDCONFIG 0x010 |
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#define FC_MTIP_STATUS 0x018 |
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#define FC_MAX_NUM_LUNS 0x080 /* Max LUNs host can provision for port */ |
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#define FC_CUR_NUM_LUNS 0x088 /* Cur number LUNs provisioned for port */ |
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#define FC_MAX_CAP_PORT 0x090 /* Max capacity all LUNs for port (4K blocks) */ |
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#define FC_CUR_CAP_PORT 0x098 /* Cur capacity all LUNs for port (4K blocks) */ |
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#define FC_PNAME 0x300 |
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#define FC_CONFIG 0x320 |
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#define FC_CONFIG2 0x328 |
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#define FC_STATUS 0x330 |
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#define FC_ERROR 0x380 |
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#define FC_ERRCAP 0x388 |
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#define FC_ERRMSK 0x390 |
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#define FC_CNT_CRCERR 0x538 |
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#define FC_CRC_THRESH 0x580 |
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#define FC_MTIP_CMDCONFIG_ONLINE 0x20ULL |
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#define FC_MTIP_CMDCONFIG_OFFLINE 0x40ULL |
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#define FC_MTIP_STATUS_MASK 0x30ULL |
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#define FC_MTIP_STATUS_ONLINE 0x20ULL |
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#define FC_MTIP_STATUS_OFFLINE 0x10ULL |
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/* TIMEOUT and RETRY definitions */ |
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/* AFU command timeout values */ |
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#define MC_AFU_SYNC_TIMEOUT 5 /* 5 secs */ |
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#define MC_LUN_PROV_TIMEOUT 5 /* 5 secs */ |
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#define MC_AFU_DEBUG_TIMEOUT 5 /* 5 secs */ |
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/* AFU command room retry limit */ |
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#define MC_ROOM_RETRY_CNT 10 |
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/* FC CRC clear periodic timer */ |
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#define MC_CRC_THRESH 100 /* threshold in 5 mins */ |
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#define FC_PORT_STATUS_RETRY_CNT 100 /* 100 100ms retries = 10 seconds */ |
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#define FC_PORT_STATUS_RETRY_INTERVAL_US 100000 /* microseconds */ |
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/* VPD defines */ |
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#define CXLFLASH_VPD_LEN 256 |
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#define WWPN_LEN 16 |
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#define WWPN_BUF_LEN (WWPN_LEN + 1) |
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enum undo_level { |
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UNDO_NOOP = 0, |
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FREE_IRQ, |
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UNMAP_ONE, |
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UNMAP_TWO, |
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UNMAP_THREE |
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}; |
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struct dev_dependent_vals { |
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u64 max_sectors; |
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u64 flags; |
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#define CXLFLASH_NOTIFY_SHUTDOWN 0x0000000000000001ULL |
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#define CXLFLASH_WWPN_VPD_REQUIRED 0x0000000000000002ULL |
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#define CXLFLASH_OCXL_DEV 0x0000000000000004ULL |
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}; |
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static inline const struct cxlflash_backend_ops * |
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cxlflash_assign_ops(struct dev_dependent_vals *ddv) |
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{ |
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const struct cxlflash_backend_ops *ops = NULL; |
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#ifdef CONFIG_OCXL_BASE |
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if (ddv->flags & CXLFLASH_OCXL_DEV) |
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ops = &cxlflash_ocxl_ops; |
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#endif |
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#ifdef CONFIG_CXL_BASE |
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if (!(ddv->flags & CXLFLASH_OCXL_DEV)) |
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ops = &cxlflash_cxl_ops; |
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#endif |
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return ops; |
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} |
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struct asyc_intr_info { |
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u64 status; |
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char *desc; |
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u8 port; |
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u8 action; |
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#define CLR_FC_ERROR 0x01 |
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#define LINK_RESET 0x02 |
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#define SCAN_HOST 0x04 |
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}; |
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#endif /* _CXLFLASH_MAIN_H */
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