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322 lines
11 KiB
322 lines
11 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* NCR 5380 defines |
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* |
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* Copyright 1993, Drew Eckhardt |
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* Visionary Computing |
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* (Unix consulting and custom programming) |
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* [email protected] |
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* +1 (303) 666-5836 |
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* |
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* For more information, please consult |
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* |
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* NCR 5380 Family |
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* SCSI Protocol Controller |
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* Databook |
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* NCR Microelectronics |
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* 1635 Aeroplaza Drive |
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* Colorado Springs, CO 80916 |
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* 1+ (719) 578-3400 |
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* 1+ (800) 334-5454 |
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*/ |
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#ifndef NCR5380_H |
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#define NCR5380_H |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/list.h> |
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#include <linux/workqueue.h> |
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#include <scsi/scsi_dbg.h> |
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#include <scsi/scsi_eh.h> |
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#include <scsi/scsi_transport_spi.h> |
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#define NDEBUG_ARBITRATION 0x1 |
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#define NDEBUG_AUTOSENSE 0x2 |
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#define NDEBUG_DMA 0x4 |
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#define NDEBUG_HANDSHAKE 0x8 |
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#define NDEBUG_INFORMATION 0x10 |
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#define NDEBUG_INIT 0x20 |
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#define NDEBUG_INTR 0x40 |
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#define NDEBUG_LINKED 0x80 |
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#define NDEBUG_MAIN 0x100 |
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#define NDEBUG_NO_DATAOUT 0x200 |
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#define NDEBUG_NO_WRITE 0x400 |
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#define NDEBUG_PIO 0x800 |
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#define NDEBUG_PSEUDO_DMA 0x1000 |
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#define NDEBUG_QUEUES 0x2000 |
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#define NDEBUG_RESELECTION 0x4000 |
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#define NDEBUG_SELECTION 0x8000 |
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#define NDEBUG_USLEEP 0x10000 |
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#define NDEBUG_LAST_BYTE_SENT 0x20000 |
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#define NDEBUG_RESTART_SELECT 0x40000 |
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#define NDEBUG_EXTENDED 0x80000 |
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#define NDEBUG_C400_PREAD 0x100000 |
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#define NDEBUG_C400_PWRITE 0x200000 |
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#define NDEBUG_LISTS 0x400000 |
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#define NDEBUG_ABORT 0x800000 |
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#define NDEBUG_TAGS 0x1000000 |
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#define NDEBUG_MERGING 0x2000000 |
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#define NDEBUG_ANY 0xFFFFFFFFUL |
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/* |
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* The contents of the OUTPUT DATA register are asserted on the bus when |
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* either arbitration is occurring or the phase-indicating signals ( |
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* IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA |
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* bit in the INITIATOR COMMAND register is set. |
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*/ |
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#define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */ |
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#define CURRENT_SCSI_DATA_REG 0 /* ro same */ |
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#define INITIATOR_COMMAND_REG 1 /* rw */ |
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#define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */ |
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#define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */ |
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#define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */ |
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#define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */ |
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#define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */ |
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#define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */ |
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#define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */ |
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#define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */ |
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#define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */ |
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#define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */ |
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#define ICR_BASE 0 |
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#define MODE_REG 2 |
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/* |
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* Note : BLOCK_DMA code will keep DRQ asserted for the duration of the |
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* transfer, causing the chip to hog the bus. You probably don't want |
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* this. |
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*/ |
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#define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */ |
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#define MR_TARGET 0x40 /* rw target mode */ |
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#define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */ |
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#define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */ |
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#define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */ |
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#define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */ |
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#define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */ |
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#define MR_ARBITRATE 0x01 /* rw start arbitration */ |
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#define MR_BASE 0 |
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#define TARGET_COMMAND_REG 3 |
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#define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */ |
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#define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */ |
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#define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */ |
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#define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */ |
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#define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */ |
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#define STATUS_REG 4 /* ro */ |
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/* |
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* Note : a set bit indicates an active signal, driven by us or another |
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* device. |
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*/ |
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#define SR_RST 0x80 |
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#define SR_BSY 0x40 |
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#define SR_REQ 0x20 |
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#define SR_MSG 0x10 |
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#define SR_CD 0x08 |
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#define SR_IO 0x04 |
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#define SR_SEL 0x02 |
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#define SR_DBP 0x01 |
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/* |
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* Setting a bit in this register will cause an interrupt to be generated when |
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* BSY is false and SEL true and this bit is asserted on the bus. |
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*/ |
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#define SELECT_ENABLE_REG 4 /* wo */ |
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#define BUS_AND_STATUS_REG 5 /* ro */ |
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#define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */ |
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#define BASR_DRQ 0x40 /* ro mirror of DRQ pin */ |
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#define BASR_PARITY_ERROR 0x20 /* ro parity error detected */ |
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#define BASR_IRQ 0x10 /* ro mirror of IRQ pin */ |
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#define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */ |
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#define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */ |
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#define BASR_ATN 0x02 /* ro BUS status */ |
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#define BASR_ACK 0x01 /* ro BUS status */ |
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/* Write any value to this register to start a DMA send */ |
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#define START_DMA_SEND_REG 5 /* wo */ |
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/* |
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* Used in DMA transfer mode, data is latched from the SCSI bus on |
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* the falling edge of REQ (ini) or ACK (tgt) |
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*/ |
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#define INPUT_DATA_REG 6 /* ro */ |
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/* Write any value to this register to start a DMA receive */ |
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#define START_DMA_TARGET_RECEIVE_REG 6 /* wo */ |
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/* Read this register to clear interrupt conditions */ |
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#define RESET_PARITY_INTERRUPT_REG 7 /* ro */ |
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/* Write any value to this register to start an ini mode DMA receive */ |
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#define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */ |
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/* NCR 53C400(A) Control Status Register bits: */ |
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#define CSR_RESET 0x80 /* wo Resets 53c400 */ |
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#define CSR_53C80_REG 0x80 /* ro 5380 registers busy */ |
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#define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */ |
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#define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */ |
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#define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */ |
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#define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */ |
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#define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */ |
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#define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */ |
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#define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */ |
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#define CSR_BASE CSR_53C80_INTR |
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/* Note : PHASE_* macros are based on the values of the STATUS register */ |
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#define PHASE_MASK (SR_MSG | SR_CD | SR_IO) |
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#define PHASE_DATAOUT 0 |
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#define PHASE_DATAIN SR_IO |
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#define PHASE_CMDOUT SR_CD |
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#define PHASE_STATIN (SR_CD | SR_IO) |
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#define PHASE_MSGOUT (SR_MSG | SR_CD) |
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#define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO) |
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#define PHASE_UNKNOWN 0xff |
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/* |
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* Convert status register phase to something we can use to set phase in |
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* the target register so we can get phase mismatch interrupts on DMA |
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* transfers. |
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*/ |
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#define PHASE_SR_TO_TCR(phase) ((phase) >> 2) |
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#ifndef NO_IRQ |
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#define NO_IRQ 0 |
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#endif |
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#define FLAG_DMA_FIXUP 1 /* Use DMA errata workarounds */ |
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#define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */ |
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#define FLAG_LATE_DMA_SETUP 32 /* Setup NCR before DMA H/W */ |
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#define FLAG_TOSHIBA_DELAY 128 /* Allow for borken CD-ROMs */ |
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struct NCR5380_hostdata { |
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NCR5380_implementation_fields; /* Board-specific data */ |
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u8 __iomem *io; /* Remapped 5380 address */ |
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u8 __iomem *pdma_io; /* Remapped PDMA address */ |
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unsigned long poll_loops; /* Register polling limit */ |
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spinlock_t lock; /* Protects this struct */ |
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struct scsi_cmnd *connected; /* Currently connected cmnd */ |
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struct list_head disconnected; /* Waiting for reconnect */ |
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struct Scsi_Host *host; /* SCSI host backpointer */ |
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struct workqueue_struct *work_q; /* SCSI host work queue */ |
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struct work_struct main_task; /* Work item for main loop */ |
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int flags; /* Board-specific quirks */ |
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int dma_len; /* Requested length of DMA */ |
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int read_overruns; /* Transfer size reduction for DMA erratum */ |
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unsigned long io_port; /* Device IO port */ |
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unsigned long base; /* Device base address */ |
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struct list_head unissued; /* Waiting to be issued */ |
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struct scsi_cmnd *selecting; /* Cmnd to be connected */ |
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struct list_head autosense; /* Priority cmnd queue */ |
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struct scsi_cmnd *sensing; /* Cmnd needing autosense */ |
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struct scsi_eh_save ses; /* Cmnd state saved for EH */ |
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unsigned char busy[8]; /* Index = target, bit = lun */ |
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unsigned char id_mask; /* 1 << Host ID */ |
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unsigned char id_higher_mask; /* All bits above id_mask */ |
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unsigned char last_message; /* Last Message Out */ |
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unsigned long region_size; /* Size of address/port range */ |
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char info[168]; /* Host banner message */ |
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}; |
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struct NCR5380_cmd { |
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struct list_head list; |
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}; |
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#define NCR5380_CMD_SIZE (sizeof(struct NCR5380_cmd)) |
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#define NCR5380_PIO_CHUNK_SIZE 256 |
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/* Time limit (ms) to poll registers when IRQs are disabled, e.g. during PDMA */ |
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#define NCR5380_REG_POLL_TIME 10 |
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static inline struct scsi_cmnd *NCR5380_to_scmd(struct NCR5380_cmd *ncmd_ptr) |
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{ |
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return ((struct scsi_cmnd *)ncmd_ptr) - 1; |
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} |
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#ifndef NDEBUG |
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#define NDEBUG (0) |
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#endif |
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#define dprintk(flg, fmt, ...) \ |
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do { if ((NDEBUG) & (flg)) \ |
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printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0) |
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#define dsprintk(flg, host, fmt, ...) \ |
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do { if ((NDEBUG) & (flg)) \ |
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shost_printk(KERN_DEBUG, host, fmt, ## __VA_ARGS__); \ |
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} while (0) |
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#if NDEBUG |
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#define NCR5380_dprint(flg, arg) \ |
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do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0) |
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#define NCR5380_dprint_phase(flg, arg) \ |
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do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0) |
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static void NCR5380_print_phase(struct Scsi_Host *instance); |
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static void NCR5380_print(struct Scsi_Host *instance); |
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#else |
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#define NCR5380_dprint(flg, arg) do {} while (0) |
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#define NCR5380_dprint_phase(flg, arg) do {} while (0) |
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#endif |
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static int NCR5380_init(struct Scsi_Host *instance, int flags); |
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static int NCR5380_maybe_reset_bus(struct Scsi_Host *); |
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static void NCR5380_exit(struct Scsi_Host *instance); |
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static void NCR5380_information_transfer(struct Scsi_Host *instance); |
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static irqreturn_t NCR5380_intr(int irq, void *dev_id); |
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static void NCR5380_main(struct work_struct *work); |
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static const char *NCR5380_info(struct Scsi_Host *instance); |
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static void NCR5380_reselect(struct Scsi_Host *instance); |
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static bool NCR5380_select(struct Scsi_Host *, struct scsi_cmnd *); |
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static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data); |
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static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data, |
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unsigned int can_sleep); |
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static int NCR5380_poll_politely2(struct NCR5380_hostdata *, |
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unsigned int, u8, u8, |
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unsigned int, u8, u8, unsigned long); |
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static inline int NCR5380_poll_politely(struct NCR5380_hostdata *hostdata, |
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unsigned int reg, u8 bit, u8 val, |
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unsigned long wait) |
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{ |
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if ((NCR5380_read(reg) & bit) == val) |
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return 0; |
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return NCR5380_poll_politely2(hostdata, reg, bit, val, |
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reg, bit, val, wait); |
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} |
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static int NCR5380_dma_xfer_len(struct NCR5380_hostdata *, |
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struct scsi_cmnd *); |
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static int NCR5380_dma_send_setup(struct NCR5380_hostdata *, |
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unsigned char *, int); |
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static int NCR5380_dma_recv_setup(struct NCR5380_hostdata *, |
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unsigned char *, int); |
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static int NCR5380_dma_residual(struct NCR5380_hostdata *); |
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static inline int NCR5380_dma_xfer_none(struct NCR5380_hostdata *hostdata, |
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struct scsi_cmnd *cmd) |
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{ |
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return 0; |
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} |
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static inline int NCR5380_dma_setup_none(struct NCR5380_hostdata *hostdata, |
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unsigned char *data, int count) |
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{ |
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return 0; |
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} |
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static inline int NCR5380_dma_residual_none(struct NCR5380_hostdata *hostdata) |
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{ |
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return 0; |
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} |
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#endif /* NCR5380_H */
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