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392 lines
10 KiB
392 lines
10 KiB
/* |
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* Ricoh RS5C313 RTC device/driver |
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* Copyright (C) 2007 Nobuhiro Iwamatsu |
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* |
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* 2005-09-19 modifed by kogiidena |
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* |
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* Based on the old drivers/char/rs5c313_rtc.c by: |
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* Copyright (C) 2000 Philipp Rumpf <[email protected]> |
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* Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka |
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* |
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* Based on code written by Paul Gortmaker. |
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* Copyright (C) 1996 Paul Gortmaker |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Based on other minimal char device drivers, like Alan's |
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* watchdog, Ted's random, etc. etc. |
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* |
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* 1.07 Paul Gortmaker. |
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* 1.08 Miquel van Smoorenburg: disallow certain things on the |
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* DEC Alpha as the CMOS clock is also used for other things. |
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* 1.09 Nikita Schmidt: epoch support and some Alpha cleanup. |
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* 1.09a Pete Zaitcev: Sun SPARC |
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* 1.09b Jeff Garzik: Modularize, init cleanup |
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* 1.09c Jeff Garzik: SMP cleanup |
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* 1.10 Paul Barton-Davis: add support for async I/O |
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* 1.10a Andrea Arcangeli: Alpha updates |
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* 1.10b Andrew Morton: SMP lock fix |
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* 1.10c Cesar Barros: SMP locking fixes and cleanup |
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* 1.10d Paul Gortmaker: delete paranoia check in rtc_exit |
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* 1.10e Maciej W. Rozycki: Handle DECstation's year weirdness. |
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* 1.11 Takashi Iwai: Kernel access functions |
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* rtc_register/rtc_unregister/rtc_control |
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* 1.11a Daniele Bellucci: Audit create_proc_read_entry in rtc_init |
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* 1.12 Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer |
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* CONFIG_HPET_EMULATE_RTC |
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* 1.13 Nobuhiro Iwamatsu: Updata driver. |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/module.h> |
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#include <linux/err.h> |
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#include <linux/rtc.h> |
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#include <linux/platform_device.h> |
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#include <linux/bcd.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#define DRV_NAME "rs5c313" |
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#ifdef CONFIG_SH_LANDISK |
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/*****************************************************/ |
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/* LANDISK dependence part of RS5C313 */ |
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/*****************************************************/ |
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#define SCSMR1 0xFFE00000 |
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#define SCSCR1 0xFFE00008 |
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#define SCSMR1_CA 0x80 |
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#define SCSCR1_CKE 0x03 |
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#define SCSPTR1 0xFFE0001C |
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#define SCSPTR1_EIO 0x80 |
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#define SCSPTR1_SPB1IO 0x08 |
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#define SCSPTR1_SPB1DT 0x04 |
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#define SCSPTR1_SPB0IO 0x02 |
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#define SCSPTR1_SPB0DT 0x01 |
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#define SDA_OEN SCSPTR1_SPB1IO |
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#define SDA SCSPTR1_SPB1DT |
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#define SCL_OEN SCSPTR1_SPB0IO |
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#define SCL SCSPTR1_SPB0DT |
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/* RICOH RS5C313 CE port */ |
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#define RS5C313_CE 0xB0000003 |
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/* RICOH RS5C313 CE port bit */ |
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#define RS5C313_CE_RTCCE 0x02 |
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/* SCSPTR1 data */ |
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unsigned char scsptr1_data; |
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#define RS5C313_CEENABLE __raw_writeb(RS5C313_CE_RTCCE, RS5C313_CE); |
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#define RS5C313_CEDISABLE __raw_writeb(0x00, RS5C313_CE) |
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#define RS5C313_MISCOP __raw_writeb(0x02, 0xB0000008) |
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static void rs5c313_init_port(void) |
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{ |
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/* Set SCK as I/O port and Initialize SCSPTR1 data & I/O port. */ |
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__raw_writeb(__raw_readb(SCSMR1) & ~SCSMR1_CA, SCSMR1); |
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__raw_writeb(__raw_readb(SCSCR1) & ~SCSCR1_CKE, SCSCR1); |
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/* And Initialize SCL for RS5C313 clock */ |
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scsptr1_data = __raw_readb(SCSPTR1) | SCL; /* SCL:H */ |
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__raw_writeb(scsptr1_data, SCSPTR1); |
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scsptr1_data = __raw_readb(SCSPTR1) | SCL_OEN; /* SCL output enable */ |
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__raw_writeb(scsptr1_data, SCSPTR1); |
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RS5C313_CEDISABLE; /* CE:L */ |
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} |
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static void rs5c313_write_data(unsigned char data) |
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{ |
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int i; |
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for (i = 0; i < 8; i++) { |
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/* SDA:Write Data */ |
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scsptr1_data = (scsptr1_data & ~SDA) | |
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((((0x80 >> i) & data) >> (7 - i)) << 2); |
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__raw_writeb(scsptr1_data, SCSPTR1); |
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if (i == 0) { |
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scsptr1_data |= SDA_OEN; /* SDA:output enable */ |
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__raw_writeb(scsptr1_data, SCSPTR1); |
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} |
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ndelay(700); |
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scsptr1_data &= ~SCL; /* SCL:L */ |
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__raw_writeb(scsptr1_data, SCSPTR1); |
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ndelay(700); |
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scsptr1_data |= SCL; /* SCL:H */ |
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__raw_writeb(scsptr1_data, SCSPTR1); |
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} |
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scsptr1_data &= ~SDA_OEN; /* SDA:output disable */ |
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__raw_writeb(scsptr1_data, SCSPTR1); |
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} |
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static unsigned char rs5c313_read_data(void) |
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{ |
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int i; |
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unsigned char data = 0; |
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for (i = 0; i < 8; i++) { |
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ndelay(700); |
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/* SDA:Read Data */ |
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data |= ((__raw_readb(SCSPTR1) & SDA) >> 2) << (7 - i); |
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scsptr1_data &= ~SCL; /* SCL:L */ |
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__raw_writeb(scsptr1_data, SCSPTR1); |
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ndelay(700); |
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scsptr1_data |= SCL; /* SCL:H */ |
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__raw_writeb(scsptr1_data, SCSPTR1); |
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} |
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return data & 0x0F; |
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} |
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#endif /* CONFIG_SH_LANDISK */ |
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/*****************************************************/ |
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/* machine independence part of RS5C313 */ |
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/*****************************************************/ |
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/* RICOH RS5C313 address */ |
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#define RS5C313_ADDR_SEC 0x00 |
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#define RS5C313_ADDR_SEC10 0x01 |
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#define RS5C313_ADDR_MIN 0x02 |
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#define RS5C313_ADDR_MIN10 0x03 |
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#define RS5C313_ADDR_HOUR 0x04 |
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#define RS5C313_ADDR_HOUR10 0x05 |
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#define RS5C313_ADDR_WEEK 0x06 |
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#define RS5C313_ADDR_INTINTVREG 0x07 |
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#define RS5C313_ADDR_DAY 0x08 |
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#define RS5C313_ADDR_DAY10 0x09 |
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#define RS5C313_ADDR_MON 0x0A |
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#define RS5C313_ADDR_MON10 0x0B |
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#define RS5C313_ADDR_YEAR 0x0C |
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#define RS5C313_ADDR_YEAR10 0x0D |
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#define RS5C313_ADDR_CNTREG 0x0E |
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#define RS5C313_ADDR_TESTREG 0x0F |
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/* RICOH RS5C313 control register */ |
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#define RS5C313_CNTREG_ADJ_BSY 0x01 |
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#define RS5C313_CNTREG_WTEN_XSTP 0x02 |
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#define RS5C313_CNTREG_12_24 0x04 |
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#define RS5C313_CNTREG_CTFG 0x08 |
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/* RICOH RS5C313 test register */ |
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#define RS5C313_TESTREG_TEST 0x01 |
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/* RICOH RS5C313 control bit */ |
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#define RS5C313_CNTBIT_READ 0x40 |
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#define RS5C313_CNTBIT_AD 0x20 |
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#define RS5C313_CNTBIT_DT 0x10 |
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static unsigned char rs5c313_read_reg(unsigned char addr) |
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{ |
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rs5c313_write_data(addr | RS5C313_CNTBIT_READ | RS5C313_CNTBIT_AD); |
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return rs5c313_read_data(); |
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} |
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static void rs5c313_write_reg(unsigned char addr, unsigned char data) |
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{ |
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data &= 0x0f; |
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rs5c313_write_data(addr | RS5C313_CNTBIT_AD); |
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rs5c313_write_data(data | RS5C313_CNTBIT_DT); |
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return; |
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} |
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static inline unsigned char rs5c313_read_cntreg(void) |
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{ |
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return rs5c313_read_reg(RS5C313_ADDR_CNTREG); |
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} |
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static inline void rs5c313_write_cntreg(unsigned char data) |
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{ |
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rs5c313_write_reg(RS5C313_ADDR_CNTREG, data); |
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} |
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static inline void rs5c313_write_intintvreg(unsigned char data) |
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{ |
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rs5c313_write_reg(RS5C313_ADDR_INTINTVREG, data); |
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} |
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static int rs5c313_rtc_read_time(struct device *dev, struct rtc_time *tm) |
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{ |
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int data; |
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int cnt; |
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cnt = 0; |
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while (1) { |
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RS5C313_CEENABLE; /* CE:H */ |
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/* Initialize control reg. 24 hour */ |
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rs5c313_write_cntreg(0x04); |
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if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY)) |
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break; |
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RS5C313_CEDISABLE; |
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ndelay(700); /* CE:L */ |
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if (cnt++ > 100) { |
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dev_err(dev, "%s: timeout error\n", __func__); |
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return -EIO; |
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} |
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} |
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data = rs5c313_read_reg(RS5C313_ADDR_SEC); |
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data |= (rs5c313_read_reg(RS5C313_ADDR_SEC10) << 4); |
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tm->tm_sec = bcd2bin(data); |
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data = rs5c313_read_reg(RS5C313_ADDR_MIN); |
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data |= (rs5c313_read_reg(RS5C313_ADDR_MIN10) << 4); |
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tm->tm_min = bcd2bin(data); |
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data = rs5c313_read_reg(RS5C313_ADDR_HOUR); |
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data |= (rs5c313_read_reg(RS5C313_ADDR_HOUR10) << 4); |
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tm->tm_hour = bcd2bin(data); |
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data = rs5c313_read_reg(RS5C313_ADDR_DAY); |
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data |= (rs5c313_read_reg(RS5C313_ADDR_DAY10) << 4); |
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tm->tm_mday = bcd2bin(data); |
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data = rs5c313_read_reg(RS5C313_ADDR_MON); |
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data |= (rs5c313_read_reg(RS5C313_ADDR_MON10) << 4); |
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tm->tm_mon = bcd2bin(data) - 1; |
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data = rs5c313_read_reg(RS5C313_ADDR_YEAR); |
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data |= (rs5c313_read_reg(RS5C313_ADDR_YEAR10) << 4); |
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tm->tm_year = bcd2bin(data); |
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if (tm->tm_year < 70) |
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tm->tm_year += 100; |
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data = rs5c313_read_reg(RS5C313_ADDR_WEEK); |
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tm->tm_wday = bcd2bin(data); |
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RS5C313_CEDISABLE; |
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ndelay(700); /* CE:L */ |
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return 0; |
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} |
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static int rs5c313_rtc_set_time(struct device *dev, struct rtc_time *tm) |
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{ |
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int data; |
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int cnt; |
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cnt = 0; |
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/* busy check. */ |
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while (1) { |
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RS5C313_CEENABLE; /* CE:H */ |
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/* Initiatlize control reg. 24 hour */ |
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rs5c313_write_cntreg(0x04); |
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if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY)) |
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break; |
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RS5C313_MISCOP; |
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RS5C313_CEDISABLE; |
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ndelay(700); /* CE:L */ |
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if (cnt++ > 100) { |
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dev_err(dev, "%s: timeout error\n", __func__); |
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return -EIO; |
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} |
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} |
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data = bin2bcd(tm->tm_sec); |
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rs5c313_write_reg(RS5C313_ADDR_SEC, data); |
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rs5c313_write_reg(RS5C313_ADDR_SEC10, (data >> 4)); |
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data = bin2bcd(tm->tm_min); |
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rs5c313_write_reg(RS5C313_ADDR_MIN, data); |
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rs5c313_write_reg(RS5C313_ADDR_MIN10, (data >> 4)); |
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data = bin2bcd(tm->tm_hour); |
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rs5c313_write_reg(RS5C313_ADDR_HOUR, data); |
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rs5c313_write_reg(RS5C313_ADDR_HOUR10, (data >> 4)); |
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data = bin2bcd(tm->tm_mday); |
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rs5c313_write_reg(RS5C313_ADDR_DAY, data); |
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rs5c313_write_reg(RS5C313_ADDR_DAY10, (data >> 4)); |
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data = bin2bcd(tm->tm_mon + 1); |
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rs5c313_write_reg(RS5C313_ADDR_MON, data); |
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rs5c313_write_reg(RS5C313_ADDR_MON10, (data >> 4)); |
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data = bin2bcd(tm->tm_year % 100); |
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rs5c313_write_reg(RS5C313_ADDR_YEAR, data); |
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rs5c313_write_reg(RS5C313_ADDR_YEAR10, (data >> 4)); |
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data = bin2bcd(tm->tm_wday); |
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rs5c313_write_reg(RS5C313_ADDR_WEEK, data); |
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RS5C313_CEDISABLE; /* CE:H */ |
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ndelay(700); |
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return 0; |
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} |
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static void rs5c313_check_xstp_bit(void) |
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{ |
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struct rtc_time tm; |
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int cnt; |
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RS5C313_CEENABLE; /* CE:H */ |
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if (rs5c313_read_cntreg() & RS5C313_CNTREG_WTEN_XSTP) { |
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/* INT interval reg. OFF */ |
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rs5c313_write_intintvreg(0x00); |
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/* Initialize control reg. 24 hour & adjust */ |
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rs5c313_write_cntreg(0x07); |
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/* busy check. */ |
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for (cnt = 0; cnt < 100; cnt++) { |
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if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY)) |
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break; |
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RS5C313_MISCOP; |
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} |
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memset(&tm, 0, sizeof(struct rtc_time)); |
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tm.tm_mday = 1; |
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tm.tm_mon = 1 - 1; |
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tm.tm_year = 2000 - 1900; |
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rs5c313_rtc_set_time(NULL, &tm); |
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pr_err("invalid value, resetting to 1 Jan 2000\n"); |
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} |
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RS5C313_CEDISABLE; |
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ndelay(700); /* CE:L */ |
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} |
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static const struct rtc_class_ops rs5c313_rtc_ops = { |
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.read_time = rs5c313_rtc_read_time, |
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.set_time = rs5c313_rtc_set_time, |
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}; |
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static int rs5c313_rtc_probe(struct platform_device *pdev) |
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{ |
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struct rtc_device *rtc; |
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rs5c313_init_port(); |
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rs5c313_check_xstp_bit(); |
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rtc = devm_rtc_device_register(&pdev->dev, "rs5c313", &rs5c313_rtc_ops, |
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THIS_MODULE); |
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return PTR_ERR_OR_ZERO(rtc); |
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} |
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static struct platform_driver rs5c313_rtc_platform_driver = { |
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.driver = { |
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.name = DRV_NAME, |
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}, |
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.probe = rs5c313_rtc_probe, |
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}; |
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module_platform_driver(rs5c313_rtc_platform_driver); |
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MODULE_AUTHOR("kogiidena , Nobuhiro Iwamatsu <[email protected]>"); |
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MODULE_DESCRIPTION("Ricoh RS5C313 RTC device driver"); |
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MODULE_LICENSE("GPL"); |
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MODULE_ALIAS("platform:" DRV_NAME);
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