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615 lines
15 KiB
615 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2016-2018 Linaro Ltd. |
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* Copyright (C) 2014 Sony Mobile Communications AB |
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* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. |
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*/ |
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#include <linux/iopoll.h> |
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#include <linux/kernel.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/of_reserved_mem.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/reset.h> |
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#include <linux/soc/qcom/mdt_loader.h> |
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#include "qcom_common.h" |
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#include "qcom_pil_info.h" |
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#include "qcom_q6v5.h" |
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#define WCSS_CRASH_REASON 421 |
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/* Q6SS Register Offsets */ |
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#define Q6SS_RESET_REG 0x014 |
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#define Q6SS_GFMUX_CTL_REG 0x020 |
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#define Q6SS_PWR_CTL_REG 0x030 |
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#define Q6SS_MEM_PWR_CTL 0x0B0 |
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/* AXI Halt Register Offsets */ |
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#define AXI_HALTREQ_REG 0x0 |
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#define AXI_HALTACK_REG 0x4 |
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#define AXI_IDLE_REG 0x8 |
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#define HALT_ACK_TIMEOUT_MS 100 |
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/* Q6SS_RESET */ |
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#define Q6SS_STOP_CORE BIT(0) |
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#define Q6SS_CORE_ARES BIT(1) |
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#define Q6SS_BUS_ARES_ENABLE BIT(2) |
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/* Q6SS_GFMUX_CTL */ |
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#define Q6SS_CLK_ENABLE BIT(1) |
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/* Q6SS_PWR_CTL */ |
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#define Q6SS_L2DATA_STBY_N BIT(18) |
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#define Q6SS_SLP_RET_N BIT(19) |
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#define Q6SS_CLAMP_IO BIT(20) |
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#define QDSS_BHS_ON BIT(21) |
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/* Q6SS parameters */ |
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#define Q6SS_LDO_BYP BIT(25) |
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#define Q6SS_BHS_ON BIT(24) |
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#define Q6SS_CLAMP_WL BIT(21) |
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#define Q6SS_CLAMP_QMC_MEM BIT(22) |
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#define HALT_CHECK_MAX_LOOPS 200 |
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#define Q6SS_XO_CBCR GENMASK(5, 3) |
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/* Q6SS config/status registers */ |
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#define TCSR_GLOBAL_CFG0 0x0 |
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#define TCSR_GLOBAL_CFG1 0x4 |
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#define SSCAON_CONFIG 0x8 |
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#define SSCAON_STATUS 0xc |
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#define Q6SS_BHS_STATUS 0x78 |
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#define Q6SS_RST_EVB 0x10 |
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#define BHS_EN_REST_ACK BIT(0) |
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#define SSCAON_ENABLE BIT(13) |
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#define SSCAON_BUS_EN BIT(15) |
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#define SSCAON_BUS_MUX_MASK GENMASK(18, 16) |
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#define MEM_BANKS 19 |
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#define TCSR_WCSS_CLK_MASK 0x1F |
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#define TCSR_WCSS_CLK_ENABLE 0x14 |
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struct q6v5_wcss { |
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struct device *dev; |
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void __iomem *reg_base; |
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void __iomem *rmb_base; |
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struct regmap *halt_map; |
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u32 halt_q6; |
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u32 halt_wcss; |
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u32 halt_nc; |
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struct reset_control *wcss_aon_reset; |
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struct reset_control *wcss_reset; |
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struct reset_control *wcss_q6_reset; |
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struct qcom_q6v5 q6v5; |
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phys_addr_t mem_phys; |
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phys_addr_t mem_reloc; |
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void *mem_region; |
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size_t mem_size; |
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struct qcom_rproc_glink glink_subdev; |
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struct qcom_rproc_ssr ssr_subdev; |
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}; |
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static int q6v5_wcss_reset(struct q6v5_wcss *wcss) |
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{ |
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int ret; |
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u32 val; |
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int i; |
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/* Assert resets, stop core */ |
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val = readl(wcss->reg_base + Q6SS_RESET_REG); |
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val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; |
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writel(val, wcss->reg_base + Q6SS_RESET_REG); |
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/* BHS require xo cbcr to be enabled */ |
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val = readl(wcss->reg_base + Q6SS_XO_CBCR); |
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val |= 0x1; |
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writel(val, wcss->reg_base + Q6SS_XO_CBCR); |
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/* Read CLKOFF bit to go low indicating CLK is enabled */ |
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ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, |
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val, !(val & BIT(31)), 1, |
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HALT_CHECK_MAX_LOOPS); |
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if (ret) { |
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dev_err(wcss->dev, |
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"xo cbcr enabling timed out (rc:%d)\n", ret); |
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return ret; |
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} |
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/* Enable power block headswitch and wait for it to stabilize */ |
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val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); |
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val |= Q6SS_BHS_ON; |
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); |
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udelay(1); |
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/* Put LDO in bypass mode */ |
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val |= Q6SS_LDO_BYP; |
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); |
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/* Deassert Q6 compiler memory clamp */ |
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val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); |
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val &= ~Q6SS_CLAMP_QMC_MEM; |
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); |
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/* Deassert memory peripheral sleep and L2 memory standby */ |
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val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; |
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); |
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/* Turn on L1, L2, ETB and JU memories 1 at a time */ |
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val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); |
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for (i = MEM_BANKS; i >= 0; i--) { |
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val |= BIT(i); |
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writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); |
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/* |
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* Read back value to ensure the write is done then |
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* wait for 1us for both memory peripheral and data |
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* array to turn on. |
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*/ |
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val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); |
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udelay(1); |
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} |
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/* Remove word line clamp */ |
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val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); |
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val &= ~Q6SS_CLAMP_WL; |
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); |
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/* Remove IO clamp */ |
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val &= ~Q6SS_CLAMP_IO; |
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); |
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/* Bring core out of reset */ |
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val = readl(wcss->reg_base + Q6SS_RESET_REG); |
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val &= ~Q6SS_CORE_ARES; |
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writel(val, wcss->reg_base + Q6SS_RESET_REG); |
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/* Turn on core clock */ |
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val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); |
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val |= Q6SS_CLK_ENABLE; |
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writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); |
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/* Start core execution */ |
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val = readl(wcss->reg_base + Q6SS_RESET_REG); |
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val &= ~Q6SS_STOP_CORE; |
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writel(val, wcss->reg_base + Q6SS_RESET_REG); |
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return 0; |
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} |
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static int q6v5_wcss_start(struct rproc *rproc) |
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{ |
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struct q6v5_wcss *wcss = rproc->priv; |
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int ret; |
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qcom_q6v5_prepare(&wcss->q6v5); |
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/* Release Q6 and WCSS reset */ |
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ret = reset_control_deassert(wcss->wcss_reset); |
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if (ret) { |
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dev_err(wcss->dev, "wcss_reset failed\n"); |
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return ret; |
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} |
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ret = reset_control_deassert(wcss->wcss_q6_reset); |
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if (ret) { |
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dev_err(wcss->dev, "wcss_q6_reset failed\n"); |
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goto wcss_reset; |
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} |
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/* Lithium configuration - clock gating and bus arbitration */ |
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ret = regmap_update_bits(wcss->halt_map, |
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wcss->halt_nc + TCSR_GLOBAL_CFG0, |
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TCSR_WCSS_CLK_MASK, |
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TCSR_WCSS_CLK_ENABLE); |
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if (ret) |
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goto wcss_q6_reset; |
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ret = regmap_update_bits(wcss->halt_map, |
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wcss->halt_nc + TCSR_GLOBAL_CFG1, |
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1, 0); |
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if (ret) |
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goto wcss_q6_reset; |
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/* Write bootaddr to EVB so that Q6WCSS will jump there after reset */ |
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writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); |
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ret = q6v5_wcss_reset(wcss); |
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if (ret) |
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goto wcss_q6_reset; |
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ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); |
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if (ret == -ETIMEDOUT) |
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dev_err(wcss->dev, "start timed out\n"); |
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return ret; |
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wcss_q6_reset: |
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reset_control_assert(wcss->wcss_q6_reset); |
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wcss_reset: |
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reset_control_assert(wcss->wcss_reset); |
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return ret; |
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} |
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static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss, |
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struct regmap *halt_map, |
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u32 offset) |
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{ |
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unsigned long timeout; |
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unsigned int val; |
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int ret; |
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/* Check if we're already idle */ |
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ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); |
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if (!ret && val) |
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return; |
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/* Assert halt request */ |
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regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1); |
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/* Wait for halt */ |
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timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS); |
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for (;;) { |
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ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val); |
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if (ret || val || time_after(jiffies, timeout)) |
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break; |
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msleep(1); |
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} |
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ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); |
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if (ret || !val) |
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dev_err(wcss->dev, "port failed halt\n"); |
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/* Clear halt request (port will remain halted until reset) */ |
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regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0); |
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} |
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static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss) |
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{ |
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int ret; |
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u32 val; |
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/* 1 - Assert WCSS/Q6 HALTREQ */ |
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q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss); |
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/* 2 - Enable WCSSAON_CONFIG */ |
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val = readl(wcss->rmb_base + SSCAON_CONFIG); |
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val |= SSCAON_ENABLE; |
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writel(val, wcss->rmb_base + SSCAON_CONFIG); |
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/* 3 - Set SSCAON_CONFIG */ |
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val |= SSCAON_BUS_EN; |
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val &= ~SSCAON_BUS_MUX_MASK; |
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writel(val, wcss->rmb_base + SSCAON_CONFIG); |
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/* 4 - SSCAON_CONFIG 1 */ |
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val |= BIT(1); |
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writel(val, wcss->rmb_base + SSCAON_CONFIG); |
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/* 5 - wait for SSCAON_STATUS */ |
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ret = readl_poll_timeout(wcss->rmb_base + SSCAON_STATUS, |
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val, (val & 0xffff) == 0x400, 1000, |
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HALT_CHECK_MAX_LOOPS); |
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if (ret) { |
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dev_err(wcss->dev, |
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"can't get SSCAON_STATUS rc:%d)\n", ret); |
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return ret; |
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} |
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/* 6 - De-assert WCSS_AON reset */ |
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reset_control_assert(wcss->wcss_aon_reset); |
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/* 7 - Disable WCSSAON_CONFIG 13 */ |
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val = readl(wcss->rmb_base + SSCAON_CONFIG); |
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val &= ~SSCAON_ENABLE; |
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writel(val, wcss->rmb_base + SSCAON_CONFIG); |
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/* 8 - De-assert WCSS/Q6 HALTREQ */ |
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reset_control_assert(wcss->wcss_reset); |
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return 0; |
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} |
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static int q6v5_q6_powerdown(struct q6v5_wcss *wcss) |
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{ |
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int ret; |
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u32 val; |
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int i; |
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/* 1 - Halt Q6 bus interface */ |
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q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_q6); |
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/* 2 - Disable Q6 Core clock */ |
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val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); |
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val &= ~Q6SS_CLK_ENABLE; |
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writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); |
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/* 3 - Clamp I/O */ |
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val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); |
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val |= Q6SS_CLAMP_IO; |
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); |
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/* 4 - Clamp WL */ |
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val |= QDSS_BHS_ON; |
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); |
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/* 5 - Clear Erase standby */ |
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val &= ~Q6SS_L2DATA_STBY_N; |
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); |
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/* 6 - Clear Sleep RTN */ |
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val &= ~Q6SS_SLP_RET_N; |
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); |
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/* 7 - turn off Q6 memory foot/head switch one bank at a time */ |
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for (i = 0; i < 20; i++) { |
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val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); |
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val &= ~BIT(i); |
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writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); |
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mdelay(1); |
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} |
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/* 8 - Assert QMC memory RTN */ |
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val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); |
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val |= Q6SS_CLAMP_QMC_MEM; |
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); |
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/* 9 - Turn off BHS */ |
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val &= ~Q6SS_BHS_ON; |
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); |
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udelay(1); |
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/* 10 - Wait till BHS Reset is done */ |
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ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS, |
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val, !(val & BHS_EN_REST_ACK), 1000, |
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HALT_CHECK_MAX_LOOPS); |
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if (ret) { |
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dev_err(wcss->dev, "BHS_STATUS not OFF (rc:%d)\n", ret); |
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return ret; |
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} |
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/* 11 - Assert WCSS reset */ |
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reset_control_assert(wcss->wcss_reset); |
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/* 12 - Assert Q6 reset */ |
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reset_control_assert(wcss->wcss_q6_reset); |
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return 0; |
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} |
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static int q6v5_wcss_stop(struct rproc *rproc) |
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{ |
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struct q6v5_wcss *wcss = rproc->priv; |
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int ret; |
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/* WCSS powerdown */ |
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ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL); |
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if (ret == -ETIMEDOUT) { |
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dev_err(wcss->dev, "timed out on wait\n"); |
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return ret; |
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} |
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ret = q6v5_wcss_powerdown(wcss); |
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if (ret) |
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return ret; |
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/* Q6 Power down */ |
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ret = q6v5_q6_powerdown(wcss); |
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if (ret) |
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return ret; |
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qcom_q6v5_unprepare(&wcss->q6v5); |
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return 0; |
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} |
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static void *q6v5_wcss_da_to_va(struct rproc *rproc, u64 da, size_t len) |
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{ |
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struct q6v5_wcss *wcss = rproc->priv; |
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int offset; |
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offset = da - wcss->mem_reloc; |
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if (offset < 0 || offset + len > wcss->mem_size) |
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return NULL; |
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return wcss->mem_region + offset; |
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} |
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static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) |
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{ |
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struct q6v5_wcss *wcss = rproc->priv; |
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int ret; |
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ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, |
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0, wcss->mem_region, wcss->mem_phys, |
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wcss->mem_size, &wcss->mem_reloc); |
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if (ret) |
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return ret; |
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qcom_pil_info_store("wcnss", wcss->mem_phys, wcss->mem_size); |
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return ret; |
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} |
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static const struct rproc_ops q6v5_wcss_ops = { |
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.start = q6v5_wcss_start, |
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.stop = q6v5_wcss_stop, |
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.da_to_va = q6v5_wcss_da_to_va, |
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.load = q6v5_wcss_load, |
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.get_boot_addr = rproc_elf_get_boot_addr, |
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}; |
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static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss) |
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{ |
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struct device *dev = wcss->dev; |
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wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset"); |
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if (IS_ERR(wcss->wcss_aon_reset)) { |
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dev_err(wcss->dev, "unable to acquire wcss_aon_reset\n"); |
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return PTR_ERR(wcss->wcss_aon_reset); |
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} |
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wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset"); |
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if (IS_ERR(wcss->wcss_reset)) { |
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dev_err(wcss->dev, "unable to acquire wcss_reset\n"); |
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return PTR_ERR(wcss->wcss_reset); |
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} |
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wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset"); |
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if (IS_ERR(wcss->wcss_q6_reset)) { |
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dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n"); |
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return PTR_ERR(wcss->wcss_q6_reset); |
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} |
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return 0; |
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} |
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static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss, |
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struct platform_device *pdev) |
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{ |
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struct of_phandle_args args; |
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struct resource *res; |
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int ret; |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6"); |
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wcss->reg_base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(wcss->reg_base)) |
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return PTR_ERR(wcss->reg_base); |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb"); |
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wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(wcss->rmb_base)) |
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return PTR_ERR(wcss->rmb_base); |
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ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, |
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"qcom,halt-regs", 3, 0, &args); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); |
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return -EINVAL; |
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} |
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wcss->halt_map = syscon_node_to_regmap(args.np); |
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of_node_put(args.np); |
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if (IS_ERR(wcss->halt_map)) |
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return PTR_ERR(wcss->halt_map); |
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wcss->halt_q6 = args.args[0]; |
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wcss->halt_wcss = args.args[1]; |
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wcss->halt_nc = args.args[2]; |
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return 0; |
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} |
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static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss) |
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{ |
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struct reserved_mem *rmem = NULL; |
|
struct device_node *node; |
|
struct device *dev = wcss->dev; |
|
|
|
node = of_parse_phandle(dev->of_node, "memory-region", 0); |
|
if (node) |
|
rmem = of_reserved_mem_lookup(node); |
|
of_node_put(node); |
|
|
|
if (!rmem) { |
|
dev_err(dev, "unable to acquire memory-region\n"); |
|
return -EINVAL; |
|
} |
|
|
|
wcss->mem_phys = rmem->base; |
|
wcss->mem_reloc = rmem->base; |
|
wcss->mem_size = rmem->size; |
|
wcss->mem_region = devm_ioremap_wc(dev, wcss->mem_phys, wcss->mem_size); |
|
if (!wcss->mem_region) { |
|
dev_err(dev, "unable to map memory region: %pa+%pa\n", |
|
&rmem->base, &rmem->size); |
|
return -EBUSY; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int q6v5_wcss_probe(struct platform_device *pdev) |
|
{ |
|
struct q6v5_wcss *wcss; |
|
struct rproc *rproc; |
|
int ret; |
|
|
|
rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ops, |
|
"IPQ8074/q6_fw.mdt", sizeof(*wcss)); |
|
if (!rproc) { |
|
dev_err(&pdev->dev, "failed to allocate rproc\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
wcss = rproc->priv; |
|
wcss->dev = &pdev->dev; |
|
|
|
ret = q6v5_wcss_init_mmio(wcss, pdev); |
|
if (ret) |
|
goto free_rproc; |
|
|
|
ret = q6v5_alloc_memory_region(wcss); |
|
if (ret) |
|
goto free_rproc; |
|
|
|
ret = q6v5_wcss_init_reset(wcss); |
|
if (ret) |
|
goto free_rproc; |
|
|
|
ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, WCSS_CRASH_REASON, NULL); |
|
if (ret) |
|
goto free_rproc; |
|
|
|
qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss"); |
|
qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss"); |
|
|
|
ret = rproc_add(rproc); |
|
if (ret) |
|
goto free_rproc; |
|
|
|
platform_set_drvdata(pdev, rproc); |
|
|
|
return 0; |
|
|
|
free_rproc: |
|
rproc_free(rproc); |
|
|
|
return ret; |
|
} |
|
|
|
static int q6v5_wcss_remove(struct platform_device *pdev) |
|
{ |
|
struct rproc *rproc = platform_get_drvdata(pdev); |
|
|
|
rproc_del(rproc); |
|
rproc_free(rproc); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id q6v5_wcss_of_match[] = { |
|
{ .compatible = "qcom,ipq8074-wcss-pil" }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, q6v5_wcss_of_match); |
|
|
|
static struct platform_driver q6v5_wcss_driver = { |
|
.probe = q6v5_wcss_probe, |
|
.remove = q6v5_wcss_remove, |
|
.driver = { |
|
.name = "qcom-q6v5-wcss-pil", |
|
.of_match_table = q6v5_wcss_of_match, |
|
}, |
|
}; |
|
module_platform_driver(q6v5_wcss_driver); |
|
|
|
MODULE_DESCRIPTION("Hexagon WCSS Peripheral Image Loader"); |
|
MODULE_LICENSE("GPL v2");
|
|
|