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386 lines
9.8 KiB
386 lines
9.8 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* drivers/pwm/pwm-tegra.c |
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* |
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* Tegra pulse-width-modulation controller driver |
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* |
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* Copyright (c) 2010-2020, NVIDIA Corporation. |
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* Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <[email protected]> |
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* |
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* Overview of Tegra Pulse Width Modulator Register: |
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* 1. 13-bit: Frequency division (SCALE) |
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* 2. 8-bit : Pulse division (DUTY) |
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* 3. 1-bit : Enable bit |
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* |
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* The PWM clock frequency is divided by 256 before subdividing it based |
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* on the programmable frequency division value to generate the required |
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* frequency for PWM output. The maximum output frequency that can be |
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* achieved is (max rate of source clock) / 256. |
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* e.g. if source clock rate is 408 MHz, maximum output frequency can be: |
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* 408 MHz/256 = 1.6 MHz. |
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* This 1.6 MHz frequency can further be divided using SCALE value in PWM. |
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* |
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* PWM pulse width: 8 bits are usable [23:16] for varying pulse width. |
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* To achieve 100% duty cycle, program Bit [24] of this register to |
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* 1’b1. In which case the other bits [23:16] are set to don't care. |
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* |
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* Limitations: |
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* - When PWM is disabled, the output is driven to inactive. |
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* - It does not allow the current PWM period to complete and |
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* stops abruptly. |
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* |
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* - If the register is reconfigured while PWM is running, |
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* it does not complete the currently running period. |
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* |
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* - If the user input duty is beyond acceptible limits, |
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* -EINVAL is returned. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/pwm.h> |
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#include <linux/platform_device.h> |
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#include <linux/pinctrl/consumer.h> |
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#include <linux/slab.h> |
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#include <linux/reset.h> |
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#define PWM_ENABLE (1 << 31) |
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#define PWM_DUTY_WIDTH 8 |
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#define PWM_DUTY_SHIFT 16 |
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#define PWM_SCALE_WIDTH 13 |
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#define PWM_SCALE_SHIFT 0 |
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struct tegra_pwm_soc { |
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unsigned int num_channels; |
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/* Maximum IP frequency for given SoCs */ |
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unsigned long max_frequency; |
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}; |
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struct tegra_pwm_chip { |
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struct pwm_chip chip; |
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struct device *dev; |
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struct clk *clk; |
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struct reset_control*rst; |
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unsigned long clk_rate; |
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unsigned long min_period_ns; |
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void __iomem *regs; |
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const struct tegra_pwm_soc *soc; |
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}; |
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static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip) |
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{ |
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return container_of(chip, struct tegra_pwm_chip, chip); |
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} |
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static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num) |
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{ |
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return readl(chip->regs + (num << 4)); |
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} |
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static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num, |
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unsigned long val) |
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{ |
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writel(val, chip->regs + (num << 4)); |
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} |
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static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
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int duty_ns, int period_ns) |
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{ |
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struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); |
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unsigned long long c = duty_ns, hz; |
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unsigned long rate, required_clk_rate; |
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u32 val = 0; |
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int err; |
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/* |
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* Convert from duty_ns / period_ns to a fixed number of duty ticks |
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* per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the |
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* nearest integer during division. |
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*/ |
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c *= (1 << PWM_DUTY_WIDTH); |
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c = DIV_ROUND_CLOSEST_ULL(c, period_ns); |
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val = (u32)c << PWM_DUTY_SHIFT; |
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/* |
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* min period = max clock limit >> PWM_DUTY_WIDTH |
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*/ |
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if (period_ns < pc->min_period_ns) |
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return -EINVAL; |
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/* |
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* Compute the prescaler value for which (1 << PWM_DUTY_WIDTH) |
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* cycles at the PWM clock rate will take period_ns nanoseconds. |
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* |
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* num_channels: If single instance of PWM controller has multiple |
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* channels (e.g. Tegra210 or older) then it is not possible to |
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* configure separate clock rates to each of the channels, in such |
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* case the value stored during probe will be referred. |
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* |
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* If every PWM controller instance has one channel respectively, i.e. |
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* nums_channels == 1 then only the clock rate can be modified |
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* dynamically (e.g. Tegra186 or Tegra194). |
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*/ |
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if (pc->soc->num_channels == 1) { |
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/* |
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* Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches |
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* with the maximum possible rate that the controller can |
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* provide. Any further lower value can be derived by setting |
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* PFM bits[0:12]. |
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* |
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* required_clk_rate is a reference rate for source clock and |
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* it is derived based on user requested period. By setting the |
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* source clock rate as required_clk_rate, PWM controller will |
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* be able to configure the requested period. |
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*/ |
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required_clk_rate = |
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(NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH; |
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err = clk_set_rate(pc->clk, required_clk_rate); |
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if (err < 0) |
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return -EINVAL; |
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/* Store the new rate for further references */ |
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pc->clk_rate = clk_get_rate(pc->clk); |
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} |
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rate = pc->clk_rate >> PWM_DUTY_WIDTH; |
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/* Consider precision in PWM_SCALE_WIDTH rate calculation */ |
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hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns); |
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rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz); |
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/* |
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* Since the actual PWM divider is the register's frequency divider |
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* field plus 1, we need to decrement to get the correct value to |
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* write to the register. |
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*/ |
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if (rate > 0) |
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rate--; |
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/* |
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* Make sure that the rate will fit in the register's frequency |
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* divider field. |
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*/ |
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if (rate >> PWM_SCALE_WIDTH) |
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return -EINVAL; |
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val |= rate << PWM_SCALE_SHIFT; |
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/* |
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* If the PWM channel is disabled, make sure to turn on the clock |
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* before writing the register. Otherwise, keep it enabled. |
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*/ |
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if (!pwm_is_enabled(pwm)) { |
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err = clk_prepare_enable(pc->clk); |
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if (err < 0) |
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return err; |
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} else |
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val |= PWM_ENABLE; |
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pwm_writel(pc, pwm->hwpwm, val); |
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/* |
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* If the PWM is not enabled, turn the clock off again to save power. |
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*/ |
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if (!pwm_is_enabled(pwm)) |
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clk_disable_unprepare(pc->clk); |
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return 0; |
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} |
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static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); |
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int rc = 0; |
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u32 val; |
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rc = clk_prepare_enable(pc->clk); |
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if (rc < 0) |
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return rc; |
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val = pwm_readl(pc, pwm->hwpwm); |
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val |= PWM_ENABLE; |
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pwm_writel(pc, pwm->hwpwm, val); |
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return 0; |
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} |
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static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); |
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u32 val; |
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val = pwm_readl(pc, pwm->hwpwm); |
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val &= ~PWM_ENABLE; |
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pwm_writel(pc, pwm->hwpwm, val); |
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clk_disable_unprepare(pc->clk); |
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} |
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static const struct pwm_ops tegra_pwm_ops = { |
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.config = tegra_pwm_config, |
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.enable = tegra_pwm_enable, |
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.disable = tegra_pwm_disable, |
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.owner = THIS_MODULE, |
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}; |
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static int tegra_pwm_probe(struct platform_device *pdev) |
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{ |
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struct tegra_pwm_chip *pwm; |
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int ret; |
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pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); |
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if (!pwm) |
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return -ENOMEM; |
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pwm->soc = of_device_get_match_data(&pdev->dev); |
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pwm->dev = &pdev->dev; |
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pwm->regs = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(pwm->regs)) |
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return PTR_ERR(pwm->regs); |
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platform_set_drvdata(pdev, pwm); |
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pwm->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(pwm->clk)) |
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return PTR_ERR(pwm->clk); |
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/* Set maximum frequency of the IP */ |
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ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); |
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return ret; |
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} |
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/* |
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* The requested and configured frequency may differ due to |
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* clock register resolutions. Get the configured frequency |
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* so that PWM period can be calculated more accurately. |
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*/ |
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pwm->clk_rate = clk_get_rate(pwm->clk); |
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/* Set minimum limit of PWM period for the IP */ |
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pwm->min_period_ns = |
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(NSEC_PER_SEC / (pwm->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1; |
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pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm"); |
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if (IS_ERR(pwm->rst)) { |
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ret = PTR_ERR(pwm->rst); |
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dev_err(&pdev->dev, "Reset control is not found: %d\n", ret); |
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return ret; |
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} |
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reset_control_deassert(pwm->rst); |
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pwm->chip.dev = &pdev->dev; |
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pwm->chip.ops = &tegra_pwm_ops; |
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pwm->chip.base = -1; |
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pwm->chip.npwm = pwm->soc->num_channels; |
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ret = pwmchip_add(&pwm->chip); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); |
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reset_control_assert(pwm->rst); |
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return ret; |
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} |
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return 0; |
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} |
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static int tegra_pwm_remove(struct platform_device *pdev) |
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{ |
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struct tegra_pwm_chip *pc = platform_get_drvdata(pdev); |
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unsigned int i; |
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int err; |
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if (WARN_ON(!pc)) |
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return -ENODEV; |
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err = clk_prepare_enable(pc->clk); |
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if (err < 0) |
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return err; |
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for (i = 0; i < pc->chip.npwm; i++) { |
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struct pwm_device *pwm = &pc->chip.pwms[i]; |
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if (!pwm_is_enabled(pwm)) |
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if (clk_prepare_enable(pc->clk) < 0) |
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continue; |
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pwm_writel(pc, i, 0); |
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clk_disable_unprepare(pc->clk); |
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} |
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reset_control_assert(pc->rst); |
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clk_disable_unprepare(pc->clk); |
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return pwmchip_remove(&pc->chip); |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int tegra_pwm_suspend(struct device *dev) |
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{ |
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return pinctrl_pm_select_sleep_state(dev); |
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} |
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static int tegra_pwm_resume(struct device *dev) |
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{ |
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return pinctrl_pm_select_default_state(dev); |
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} |
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#endif |
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static const struct tegra_pwm_soc tegra20_pwm_soc = { |
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.num_channels = 4, |
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.max_frequency = 48000000UL, |
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}; |
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static const struct tegra_pwm_soc tegra186_pwm_soc = { |
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.num_channels = 1, |
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.max_frequency = 102000000UL, |
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}; |
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static const struct tegra_pwm_soc tegra194_pwm_soc = { |
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.num_channels = 1, |
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.max_frequency = 408000000UL, |
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}; |
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static const struct of_device_id tegra_pwm_of_match[] = { |
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{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc }, |
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{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc }, |
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{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); |
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static const struct dev_pm_ops tegra_pwm_pm_ops = { |
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SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume) |
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}; |
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static struct platform_driver tegra_pwm_driver = { |
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.driver = { |
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.name = "tegra-pwm", |
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.of_match_table = tegra_pwm_of_match, |
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.pm = &tegra_pwm_pm_ops, |
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}, |
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.probe = tegra_pwm_probe, |
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.remove = tegra_pwm_remove, |
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}; |
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module_platform_driver(tegra_pwm_driver); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Sandipan Patra <[email protected]>"); |
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MODULE_DESCRIPTION("Tegra PWM controller driver"); |
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MODULE_ALIAS("platform:tegra-pwm");
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