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648 lines
17 KiB
648 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2007 Ben Dooks |
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* Copyright (c) 2008 Simtec Electronics |
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* Ben Dooks <[email protected]>, <[email protected]> |
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* Copyright (c) 2013 Tomasz Figa <[email protected]> |
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* Copyright (c) 2017 Samsung Electronics Co., Ltd. |
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* |
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* PWM driver for Samsung SoCs |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/export.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/pwm.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/time.h> |
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/* For struct samsung_timer_variant and samsung_pwm_lock. */ |
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#include <clocksource/samsung_pwm.h> |
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#define REG_TCFG0 0x00 |
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#define REG_TCFG1 0x04 |
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#define REG_TCON 0x08 |
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#define REG_TCNTB(chan) (0x0c + ((chan) * 0xc)) |
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#define REG_TCMPB(chan) (0x10 + ((chan) * 0xc)) |
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#define TCFG0_PRESCALER_MASK 0xff |
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#define TCFG0_PRESCALER1_SHIFT 8 |
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#define TCFG1_MUX_MASK 0xf |
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#define TCFG1_SHIFT(chan) (4 * (chan)) |
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/* |
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* Each channel occupies 4 bits in TCON register, but there is a gap of 4 |
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* bits (one channel) after channel 0, so channels have different numbering |
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* when accessing TCON register. See to_tcon_channel() function. |
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* |
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* In addition, the location of autoreload bit for channel 4 (TCON channel 5) |
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* in its set of bits is 2 as opposed to 3 for other channels. |
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*/ |
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#define TCON_START(chan) BIT(4 * (chan) + 0) |
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#define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1) |
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#define TCON_INVERT(chan) BIT(4 * (chan) + 2) |
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#define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3) |
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#define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2) |
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#define TCON_AUTORELOAD(chan) \ |
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((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan)) |
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/** |
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* struct samsung_pwm_channel - private data of PWM channel |
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* @period_ns: current period in nanoseconds programmed to the hardware |
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* @duty_ns: current duty time in nanoseconds programmed to the hardware |
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* @tin_ns: time of one timer tick in nanoseconds with current timer rate |
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*/ |
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struct samsung_pwm_channel { |
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u32 period_ns; |
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u32 duty_ns; |
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u32 tin_ns; |
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}; |
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/** |
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* struct samsung_pwm_chip - private data of PWM chip |
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* @chip: generic PWM chip |
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* @variant: local copy of hardware variant data |
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* @inverter_mask: inverter status for all channels - one bit per channel |
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* @disabled_mask: disabled status for all channels - one bit per channel |
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* @base: base address of mapped PWM registers |
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* @base_clk: base clock used to drive the timers |
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* @tclk0: external clock 0 (can be ERR_PTR if not present) |
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* @tclk1: external clock 1 (can be ERR_PTR if not present) |
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*/ |
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struct samsung_pwm_chip { |
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struct pwm_chip chip; |
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struct samsung_pwm_variant variant; |
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u8 inverter_mask; |
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u8 disabled_mask; |
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void __iomem *base; |
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struct clk *base_clk; |
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struct clk *tclk0; |
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struct clk *tclk1; |
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}; |
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#ifndef CONFIG_CLKSRC_SAMSUNG_PWM |
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/* |
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* PWM block is shared between pwm-samsung and samsung_pwm_timer drivers |
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* and some registers need access synchronization. If both drivers are |
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* compiled in, the spinlock is defined in the clocksource driver, |
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* otherwise following definition is used. |
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* |
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* Currently we do not need any more complex synchronization method |
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* because all the supported SoCs contain only one instance of the PWM |
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* IP. Should this change, both drivers will need to be modified to |
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* properly synchronize accesses to particular instances. |
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*/ |
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static DEFINE_SPINLOCK(samsung_pwm_lock); |
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#endif |
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static inline |
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struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip) |
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{ |
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return container_of(chip, struct samsung_pwm_chip, chip); |
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} |
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static inline unsigned int to_tcon_channel(unsigned int channel) |
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{ |
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/* TCON register has a gap of 4 bits (1 channel) after channel 0 */ |
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return (channel == 0) ? 0 : (channel + 1); |
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} |
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static void pwm_samsung_set_divisor(struct samsung_pwm_chip *pwm, |
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unsigned int channel, u8 divisor) |
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{ |
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u8 shift = TCFG1_SHIFT(channel); |
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unsigned long flags; |
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u32 reg; |
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u8 bits; |
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bits = (fls(divisor) - 1) - pwm->variant.div_base; |
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spin_lock_irqsave(&samsung_pwm_lock, flags); |
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reg = readl(pwm->base + REG_TCFG1); |
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reg &= ~(TCFG1_MUX_MASK << shift); |
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reg |= bits << shift; |
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writel(reg, pwm->base + REG_TCFG1); |
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spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
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} |
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static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *chip, unsigned int chan) |
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{ |
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struct samsung_pwm_variant *variant = &chip->variant; |
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u32 reg; |
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reg = readl(chip->base + REG_TCFG1); |
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reg >>= TCFG1_SHIFT(chan); |
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reg &= TCFG1_MUX_MASK; |
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return (BIT(reg) & variant->tclk_mask) == 0; |
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} |
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static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *chip, |
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unsigned int chan) |
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{ |
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unsigned long rate; |
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u32 reg; |
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rate = clk_get_rate(chip->base_clk); |
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reg = readl(chip->base + REG_TCFG0); |
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if (chan >= 2) |
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reg >>= TCFG0_PRESCALER1_SHIFT; |
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reg &= TCFG0_PRESCALER_MASK; |
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return rate / (reg + 1); |
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} |
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static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *chip, |
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unsigned int chan, unsigned long freq) |
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{ |
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struct samsung_pwm_variant *variant = &chip->variant; |
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unsigned long rate; |
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struct clk *clk; |
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u8 div; |
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if (!pwm_samsung_is_tdiv(chip, chan)) { |
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clk = (chan < 2) ? chip->tclk0 : chip->tclk1; |
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if (!IS_ERR(clk)) { |
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rate = clk_get_rate(clk); |
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if (rate) |
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return rate; |
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} |
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dev_warn(chip->chip.dev, |
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"tclk of PWM %d is inoperational, using tdiv\n", chan); |
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} |
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rate = pwm_samsung_get_tin_rate(chip, chan); |
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dev_dbg(chip->chip.dev, "tin parent at %lu\n", rate); |
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/* |
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* Compare minimum PWM frequency that can be achieved with possible |
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* divider settings and choose the lowest divisor that can generate |
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* frequencies lower than requested. |
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*/ |
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if (variant->bits < 32) { |
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/* Only for s3c24xx */ |
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for (div = variant->div_base; div < 4; ++div) |
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if ((rate >> (variant->bits + div)) < freq) |
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break; |
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} else { |
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/* |
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* Other variants have enough counter bits to generate any |
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* requested rate, so no need to check higher divisors. |
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*/ |
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div = variant->div_base; |
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} |
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pwm_samsung_set_divisor(chip, chan, BIT(div)); |
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return rate >> div; |
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} |
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static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); |
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struct samsung_pwm_channel *our_chan; |
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if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { |
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dev_warn(chip->dev, |
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"tried to request PWM channel %d without output\n", |
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pwm->hwpwm); |
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return -EINVAL; |
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} |
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our_chan = kzalloc(sizeof(*our_chan), GFP_KERNEL); |
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if (!our_chan) |
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return -ENOMEM; |
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pwm_set_chip_data(pwm, our_chan); |
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return 0; |
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} |
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static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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kfree(pwm_get_chip_data(pwm)); |
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} |
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static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); |
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unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); |
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unsigned long flags; |
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u32 tcon; |
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spin_lock_irqsave(&samsung_pwm_lock, flags); |
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tcon = readl(our_chip->base + REG_TCON); |
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tcon &= ~TCON_START(tcon_chan); |
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tcon |= TCON_MANUALUPDATE(tcon_chan); |
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writel(tcon, our_chip->base + REG_TCON); |
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tcon &= ~TCON_MANUALUPDATE(tcon_chan); |
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tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan); |
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writel(tcon, our_chip->base + REG_TCON); |
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our_chip->disabled_mask &= ~BIT(pwm->hwpwm); |
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spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
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return 0; |
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} |
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static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); |
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unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); |
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unsigned long flags; |
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u32 tcon; |
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spin_lock_irqsave(&samsung_pwm_lock, flags); |
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tcon = readl(our_chip->base + REG_TCON); |
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tcon &= ~TCON_AUTORELOAD(tcon_chan); |
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writel(tcon, our_chip->base + REG_TCON); |
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our_chip->disabled_mask |= BIT(pwm->hwpwm); |
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spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
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} |
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static void pwm_samsung_manual_update(struct samsung_pwm_chip *chip, |
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struct pwm_device *pwm) |
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{ |
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unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); |
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u32 tcon; |
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unsigned long flags; |
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spin_lock_irqsave(&samsung_pwm_lock, flags); |
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tcon = readl(chip->base + REG_TCON); |
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tcon |= TCON_MANUALUPDATE(tcon_chan); |
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writel(tcon, chip->base + REG_TCON); |
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tcon &= ~TCON_MANUALUPDATE(tcon_chan); |
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writel(tcon, chip->base + REG_TCON); |
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spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
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} |
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static int __pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm, |
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int duty_ns, int period_ns, bool force_period) |
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{ |
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struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); |
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struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm); |
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u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp; |
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/* |
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* We currently avoid using 64bit arithmetic by using the |
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* fact that anything faster than 1Hz is easily representable |
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* by 32bits. |
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*/ |
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if (period_ns > NSEC_PER_SEC) |
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return -ERANGE; |
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tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm)); |
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oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm)); |
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/* We need tick count for calculation, not last tick. */ |
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++tcnt; |
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/* Check to see if we are changing the clock rate of the PWM. */ |
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if (chan->period_ns != period_ns || force_period) { |
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unsigned long tin_rate; |
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u32 period; |
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period = NSEC_PER_SEC / period_ns; |
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dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%u)\n", |
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duty_ns, period_ns, period); |
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tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period); |
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dev_dbg(our_chip->chip.dev, "tin_rate=%lu\n", tin_rate); |
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tin_ns = NSEC_PER_SEC / tin_rate; |
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tcnt = period_ns / tin_ns; |
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} |
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/* Period is too short. */ |
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if (tcnt <= 1) |
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return -ERANGE; |
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/* Note that counters count down. */ |
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tcmp = duty_ns / tin_ns; |
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/* 0% duty is not available */ |
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if (!tcmp) |
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++tcmp; |
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tcmp = tcnt - tcmp; |
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/* Decrement to get tick numbers, instead of tick counts. */ |
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--tcnt; |
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/* -1UL will give 100% duty. */ |
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--tcmp; |
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dev_dbg(our_chip->chip.dev, |
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"tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt); |
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/* Update PWM registers. */ |
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writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm)); |
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writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm)); |
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/* |
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* In case the PWM is currently at 100% duty cycle, force a manual |
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* update to prevent the signal staying high if the PWM is disabled |
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* shortly afer this update (before it autoreloaded the new values). |
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*/ |
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if (oldtcmp == (u32) -1) { |
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dev_dbg(our_chip->chip.dev, "Forcing manual update"); |
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pwm_samsung_manual_update(our_chip, pwm); |
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} |
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chan->period_ns = period_ns; |
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chan->tin_ns = tin_ns; |
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chan->duty_ns = duty_ns; |
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return 0; |
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} |
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static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm, |
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int duty_ns, int period_ns) |
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{ |
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return __pwm_samsung_config(chip, pwm, duty_ns, period_ns, false); |
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} |
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static void pwm_samsung_set_invert(struct samsung_pwm_chip *chip, |
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unsigned int channel, bool invert) |
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{ |
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unsigned int tcon_chan = to_tcon_channel(channel); |
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unsigned long flags; |
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u32 tcon; |
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spin_lock_irqsave(&samsung_pwm_lock, flags); |
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tcon = readl(chip->base + REG_TCON); |
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if (invert) { |
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chip->inverter_mask |= BIT(channel); |
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tcon |= TCON_INVERT(tcon_chan); |
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} else { |
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chip->inverter_mask &= ~BIT(channel); |
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tcon &= ~TCON_INVERT(tcon_chan); |
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} |
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writel(tcon, chip->base + REG_TCON); |
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spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
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} |
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static int pwm_samsung_set_polarity(struct pwm_chip *chip, |
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struct pwm_device *pwm, |
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enum pwm_polarity polarity) |
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{ |
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struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); |
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bool invert = (polarity == PWM_POLARITY_NORMAL); |
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/* Inverted means normal in the hardware. */ |
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pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert); |
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return 0; |
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} |
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static const struct pwm_ops pwm_samsung_ops = { |
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.request = pwm_samsung_request, |
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.free = pwm_samsung_free, |
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.enable = pwm_samsung_enable, |
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.disable = pwm_samsung_disable, |
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.config = pwm_samsung_config, |
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.set_polarity = pwm_samsung_set_polarity, |
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.owner = THIS_MODULE, |
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}; |
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#ifdef CONFIG_OF |
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static const struct samsung_pwm_variant s3c24xx_variant = { |
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.bits = 16, |
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.div_base = 1, |
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.has_tint_cstat = false, |
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.tclk_mask = BIT(4), |
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}; |
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static const struct samsung_pwm_variant s3c64xx_variant = { |
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.bits = 32, |
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.div_base = 0, |
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.has_tint_cstat = true, |
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.tclk_mask = BIT(7) | BIT(6) | BIT(5), |
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}; |
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static const struct samsung_pwm_variant s5p64x0_variant = { |
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.bits = 32, |
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.div_base = 0, |
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.has_tint_cstat = true, |
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.tclk_mask = 0, |
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}; |
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static const struct samsung_pwm_variant s5pc100_variant = { |
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.bits = 32, |
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.div_base = 0, |
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.has_tint_cstat = true, |
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.tclk_mask = BIT(5), |
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}; |
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static const struct of_device_id samsung_pwm_matches[] = { |
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{ .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant }, |
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{ .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant }, |
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{ .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant }, |
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{ .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant }, |
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{ .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, samsung_pwm_matches); |
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static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip) |
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{ |
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struct device_node *np = chip->chip.dev->of_node; |
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const struct of_device_id *match; |
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struct property *prop; |
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const __be32 *cur; |
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u32 val; |
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match = of_match_node(samsung_pwm_matches, np); |
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if (!match) |
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return -ENODEV; |
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memcpy(&chip->variant, match->data, sizeof(chip->variant)); |
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of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) { |
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if (val >= SAMSUNG_PWM_NUM) { |
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dev_err(chip->chip.dev, |
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"%s: invalid channel index in samsung,pwm-outputs property\n", |
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__func__); |
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continue; |
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} |
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chip->variant.output_mask |= BIT(val); |
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} |
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return 0; |
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} |
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#else |
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static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip) |
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{ |
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return -ENODEV; |
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} |
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#endif |
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static int pwm_samsung_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct samsung_pwm_chip *chip; |
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unsigned int chan; |
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int ret; |
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chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); |
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if (chip == NULL) |
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return -ENOMEM; |
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chip->chip.dev = &pdev->dev; |
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chip->chip.ops = &pwm_samsung_ops; |
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chip->chip.base = -1; |
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chip->chip.npwm = SAMSUNG_PWM_NUM; |
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chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1; |
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|
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if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { |
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ret = pwm_samsung_parse_dt(chip); |
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if (ret) |
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return ret; |
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chip->chip.of_xlate = of_pwm_xlate_with_flags; |
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chip->chip.of_pwm_n_cells = 3; |
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} else { |
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if (!pdev->dev.platform_data) { |
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dev_err(&pdev->dev, "no platform data specified\n"); |
|
return -EINVAL; |
|
} |
|
|
|
memcpy(&chip->variant, pdev->dev.platform_data, |
|
sizeof(chip->variant)); |
|
} |
|
|
|
chip->base = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(chip->base)) |
|
return PTR_ERR(chip->base); |
|
|
|
chip->base_clk = devm_clk_get(&pdev->dev, "timers"); |
|
if (IS_ERR(chip->base_clk)) { |
|
dev_err(dev, "failed to get timer base clk\n"); |
|
return PTR_ERR(chip->base_clk); |
|
} |
|
|
|
ret = clk_prepare_enable(chip->base_clk); |
|
if (ret < 0) { |
|
dev_err(dev, "failed to enable base clock\n"); |
|
return ret; |
|
} |
|
|
|
for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan) |
|
if (chip->variant.output_mask & BIT(chan)) |
|
pwm_samsung_set_invert(chip, chan, true); |
|
|
|
/* Following clocks are optional. */ |
|
chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0"); |
|
chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1"); |
|
|
|
platform_set_drvdata(pdev, chip); |
|
|
|
ret = pwmchip_add(&chip->chip); |
|
if (ret < 0) { |
|
dev_err(dev, "failed to register PWM chip\n"); |
|
clk_disable_unprepare(chip->base_clk); |
|
return ret; |
|
} |
|
|
|
dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n", |
|
clk_get_rate(chip->base_clk), |
|
!IS_ERR(chip->tclk0) ? clk_get_rate(chip->tclk0) : 0, |
|
!IS_ERR(chip->tclk1) ? clk_get_rate(chip->tclk1) : 0); |
|
|
|
return 0; |
|
} |
|
|
|
static int pwm_samsung_remove(struct platform_device *pdev) |
|
{ |
|
struct samsung_pwm_chip *chip = platform_get_drvdata(pdev); |
|
int ret; |
|
|
|
ret = pwmchip_remove(&chip->chip); |
|
if (ret < 0) |
|
return ret; |
|
|
|
clk_disable_unprepare(chip->base_clk); |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int pwm_samsung_resume(struct device *dev) |
|
{ |
|
struct samsung_pwm_chip *our_chip = dev_get_drvdata(dev); |
|
struct pwm_chip *chip = &our_chip->chip; |
|
unsigned int i; |
|
|
|
for (i = 0; i < SAMSUNG_PWM_NUM; i++) { |
|
struct pwm_device *pwm = &chip->pwms[i]; |
|
struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm); |
|
|
|
if (!chan) |
|
continue; |
|
|
|
if (our_chip->variant.output_mask & BIT(i)) |
|
pwm_samsung_set_invert(our_chip, i, |
|
our_chip->inverter_mask & BIT(i)); |
|
|
|
if (chan->period_ns) { |
|
__pwm_samsung_config(chip, pwm, chan->duty_ns, |
|
chan->period_ns, true); |
|
/* needed to make PWM disable work on Odroid-XU3 */ |
|
pwm_samsung_manual_update(our_chip, pwm); |
|
} |
|
|
|
if (our_chip->disabled_mask & BIT(i)) |
|
pwm_samsung_disable(chip, pwm); |
|
else |
|
pwm_samsung_enable(chip, pwm); |
|
} |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, NULL, pwm_samsung_resume); |
|
|
|
static struct platform_driver pwm_samsung_driver = { |
|
.driver = { |
|
.name = "samsung-pwm", |
|
.pm = &pwm_samsung_pm_ops, |
|
.of_match_table = of_match_ptr(samsung_pwm_matches), |
|
}, |
|
.probe = pwm_samsung_probe, |
|
.remove = pwm_samsung_remove, |
|
}; |
|
module_platform_driver(pwm_samsung_driver); |
|
|
|
MODULE_LICENSE("GPL"); |
|
MODULE_AUTHOR("Tomasz Figa <[email protected]>"); |
|
MODULE_ALIAS("platform:samsung-pwm");
|
|
|