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290 lines
8.0 KiB
290 lines
8.0 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* ST spear1340-miphy driver |
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* |
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* Copyright (C) 2014 ST Microelectronics |
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* Pratyush Anand <[email protected]> |
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* Mohit Kumar <[email protected]> |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/delay.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/kernel.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/phy/phy.h> |
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#include <linux/regmap.h> |
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/* SPEAr1340 Registers */ |
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/* Power Management Registers */ |
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#define SPEAR1340_PCM_CFG 0x100 |
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#define SPEAR1340_PCM_CFG_SATA_POWER_EN BIT(11) |
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#define SPEAR1340_PCM_WKUP_CFG 0x104 |
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#define SPEAR1340_SWITCH_CTR 0x108 |
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#define SPEAR1340_PERIP1_SW_RST 0x318 |
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#define SPEAR1340_PERIP1_SW_RSATA BIT(12) |
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#define SPEAR1340_PERIP2_SW_RST 0x31C |
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#define SPEAR1340_PERIP3_SW_RST 0x320 |
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/* PCIE - SATA configuration registers */ |
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#define SPEAR1340_PCIE_SATA_CFG 0x424 |
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/* PCIE CFG MASks */ |
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#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT BIT(11) |
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#define SPEAR1340_PCIE_CFG_POWERUP_RESET BIT(10) |
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#define SPEAR1340_PCIE_CFG_CORE_CLK_EN BIT(9) |
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#define SPEAR1340_PCIE_CFG_AUX_CLK_EN BIT(8) |
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#define SPEAR1340_SATA_CFG_TX_CLK_EN BIT(4) |
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#define SPEAR1340_SATA_CFG_RX_CLK_EN BIT(3) |
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#define SPEAR1340_SATA_CFG_POWERUP_RESET BIT(2) |
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#define SPEAR1340_SATA_CFG_PM_CLK_EN BIT(1) |
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#define SPEAR1340_PCIE_SATA_SEL_PCIE (0) |
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#define SPEAR1340_PCIE_SATA_SEL_SATA (1) |
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#define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F |
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#define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \ |
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SPEAR1340_PCIE_CFG_AUX_CLK_EN | \ |
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SPEAR1340_PCIE_CFG_CORE_CLK_EN | \ |
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SPEAR1340_PCIE_CFG_POWERUP_RESET | \ |
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SPEAR1340_PCIE_CFG_DEVICE_PRESENT) |
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#define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \ |
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SPEAR1340_SATA_CFG_PM_CLK_EN | \ |
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SPEAR1340_SATA_CFG_POWERUP_RESET | \ |
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SPEAR1340_SATA_CFG_RX_CLK_EN | \ |
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SPEAR1340_SATA_CFG_TX_CLK_EN) |
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#define SPEAR1340_PCIE_MIPHY_CFG 0x428 |
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#define SPEAR1340_MIPHY_OSC_BYPASS_EXT BIT(31) |
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#define SPEAR1340_MIPHY_CLK_REF_DIV2 BIT(27) |
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#define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27) |
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#define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27) |
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#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0) |
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#define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF |
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#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \ |
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(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ |
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SPEAR1340_MIPHY_CLK_REF_DIV2 | \ |
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SPEAR1340_MIPHY_PLL_RATIO_TOP(60)) |
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#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ |
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(SPEAR1340_MIPHY_PLL_RATIO_TOP(120)) |
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#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \ |
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(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ |
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SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) |
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enum spear1340_miphy_mode { |
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SATA, |
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PCIE, |
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}; |
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struct spear1340_miphy_priv { |
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/* phy mode: 0 for SATA 1 for PCIe */ |
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enum spear1340_miphy_mode mode; |
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/* regmap for any soc specific misc registers */ |
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struct regmap *misc; |
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/* phy struct pointer */ |
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struct phy *phy; |
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}; |
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static int spear1340_miphy_sata_init(struct spear1340_miphy_priv *priv) |
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{ |
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regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG, |
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SPEAR1340_PCIE_SATA_CFG_MASK, |
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SPEAR1340_SATA_CFG_VAL); |
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regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG, |
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SPEAR1340_PCIE_MIPHY_CFG_MASK, |
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SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK); |
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/* Switch on sata power domain */ |
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regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG, |
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SPEAR1340_PCM_CFG_SATA_POWER_EN, |
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SPEAR1340_PCM_CFG_SATA_POWER_EN); |
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/* Wait for SATA power domain on */ |
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msleep(20); |
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/* Disable PCIE SATA Controller reset */ |
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regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST, |
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SPEAR1340_PERIP1_SW_RSATA, 0); |
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/* Wait for SATA reset de-assert completion */ |
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msleep(20); |
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return 0; |
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} |
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static int spear1340_miphy_sata_exit(struct spear1340_miphy_priv *priv) |
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{ |
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regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG, |
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SPEAR1340_PCIE_SATA_CFG_MASK, 0); |
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regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG, |
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SPEAR1340_PCIE_MIPHY_CFG_MASK, 0); |
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/* Enable PCIE SATA Controller reset */ |
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regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST, |
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SPEAR1340_PERIP1_SW_RSATA, |
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SPEAR1340_PERIP1_SW_RSATA); |
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/* Wait for SATA power domain off */ |
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msleep(20); |
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/* Switch off sata power domain */ |
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regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG, |
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SPEAR1340_PCM_CFG_SATA_POWER_EN, 0); |
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/* Wait for SATA reset assert completion */ |
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msleep(20); |
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return 0; |
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} |
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static int spear1340_miphy_pcie_init(struct spear1340_miphy_priv *priv) |
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{ |
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regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG, |
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SPEAR1340_PCIE_MIPHY_CFG_MASK, |
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SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE); |
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regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG, |
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SPEAR1340_PCIE_SATA_CFG_MASK, |
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SPEAR1340_PCIE_CFG_VAL); |
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return 0; |
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} |
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static int spear1340_miphy_pcie_exit(struct spear1340_miphy_priv *priv) |
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{ |
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regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG, |
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SPEAR1340_PCIE_MIPHY_CFG_MASK, 0); |
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regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG, |
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SPEAR1340_PCIE_SATA_CFG_MASK, 0); |
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return 0; |
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} |
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static int spear1340_miphy_init(struct phy *phy) |
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{ |
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struct spear1340_miphy_priv *priv = phy_get_drvdata(phy); |
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int ret = 0; |
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if (priv->mode == SATA) |
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ret = spear1340_miphy_sata_init(priv); |
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else if (priv->mode == PCIE) |
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ret = spear1340_miphy_pcie_init(priv); |
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return ret; |
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} |
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static int spear1340_miphy_exit(struct phy *phy) |
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{ |
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struct spear1340_miphy_priv *priv = phy_get_drvdata(phy); |
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int ret = 0; |
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if (priv->mode == SATA) |
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ret = spear1340_miphy_sata_exit(priv); |
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else if (priv->mode == PCIE) |
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ret = spear1340_miphy_pcie_exit(priv); |
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return ret; |
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} |
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static const struct of_device_id spear1340_miphy_of_match[] = { |
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{ .compatible = "st,spear1340-miphy" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, spear1340_miphy_of_match); |
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static const struct phy_ops spear1340_miphy_ops = { |
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.init = spear1340_miphy_init, |
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.exit = spear1340_miphy_exit, |
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.owner = THIS_MODULE, |
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}; |
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#ifdef CONFIG_PM_SLEEP |
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static int spear1340_miphy_suspend(struct device *dev) |
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{ |
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struct spear1340_miphy_priv *priv = dev_get_drvdata(dev); |
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int ret = 0; |
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if (priv->mode == SATA) |
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ret = spear1340_miphy_sata_exit(priv); |
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return ret; |
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} |
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static int spear1340_miphy_resume(struct device *dev) |
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{ |
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struct spear1340_miphy_priv *priv = dev_get_drvdata(dev); |
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int ret = 0; |
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if (priv->mode == SATA) |
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ret = spear1340_miphy_sata_init(priv); |
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return ret; |
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} |
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#endif |
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static SIMPLE_DEV_PM_OPS(spear1340_miphy_pm_ops, spear1340_miphy_suspend, |
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spear1340_miphy_resume); |
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static struct phy *spear1340_miphy_xlate(struct device *dev, |
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struct of_phandle_args *args) |
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{ |
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struct spear1340_miphy_priv *priv = dev_get_drvdata(dev); |
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if (args->args_count < 1) { |
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dev_err(dev, "DT did not pass correct no of args\n"); |
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return ERR_PTR(-ENODEV); |
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} |
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priv->mode = args->args[0]; |
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if (priv->mode != SATA && priv->mode != PCIE) { |
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dev_err(dev, "DT did not pass correct phy mode\n"); |
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return ERR_PTR(-ENODEV); |
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} |
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return priv->phy; |
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} |
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static int spear1340_miphy_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct spear1340_miphy_priv *priv; |
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struct phy_provider *phy_provider; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->misc = |
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syscon_regmap_lookup_by_phandle(dev->of_node, "misc"); |
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if (IS_ERR(priv->misc)) { |
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dev_err(dev, "failed to find misc regmap\n"); |
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return PTR_ERR(priv->misc); |
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} |
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priv->phy = devm_phy_create(dev, NULL, &spear1340_miphy_ops); |
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if (IS_ERR(priv->phy)) { |
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dev_err(dev, "failed to create SATA PCIe PHY\n"); |
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return PTR_ERR(priv->phy); |
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} |
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dev_set_drvdata(dev, priv); |
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phy_set_drvdata(priv->phy, priv); |
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phy_provider = |
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devm_of_phy_provider_register(dev, spear1340_miphy_xlate); |
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if (IS_ERR(phy_provider)) { |
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dev_err(dev, "failed to register phy provider\n"); |
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return PTR_ERR(phy_provider); |
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} |
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return 0; |
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} |
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static struct platform_driver spear1340_miphy_driver = { |
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.probe = spear1340_miphy_probe, |
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.driver = { |
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.name = "spear1340-miphy", |
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.pm = &spear1340_miphy_pm_ops, |
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.of_match_table = of_match_ptr(spear1340_miphy_of_match), |
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}, |
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}; |
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module_platform_driver(spear1340_miphy_driver); |
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MODULE_DESCRIPTION("ST SPEAR1340-MIPHY driver"); |
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MODULE_AUTHOR("Pratyush Anand <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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