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298 lines
8.1 KiB
298 lines
8.1 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Meson GXL and GXM USB2 PHY driver |
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* |
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* Copyright (C) 2017 Martin Blumenstingl <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/regmap.h> |
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#include <linux/reset.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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/* bits [31:27] are read-only */ |
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#define U2P_R0 0x0 |
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#define U2P_R0_BYPASS_SEL BIT(0) |
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#define U2P_R0_BYPASS_DM_EN BIT(1) |
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#define U2P_R0_BYPASS_DP_EN BIT(2) |
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#define U2P_R0_TXBITSTUFF_ENH BIT(3) |
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#define U2P_R0_TXBITSTUFF_EN BIT(4) |
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#define U2P_R0_DM_PULLDOWN BIT(5) |
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#define U2P_R0_DP_PULLDOWN BIT(6) |
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#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) |
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#define U2P_R0_DP_VBUS_VLD_EXT BIT(8) |
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#define U2P_R0_ADP_PRB_EN BIT(9) |
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#define U2P_R0_ADP_DISCHARGE BIT(10) |
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#define U2P_R0_ADP_CHARGE BIT(11) |
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#define U2P_R0_DRV_VBUS BIT(12) |
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#define U2P_R0_ID_PULLUP BIT(13) |
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#define U2P_R0_LOOPBACK_EN_B BIT(14) |
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#define U2P_R0_OTG_DISABLE BIT(15) |
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#define U2P_R0_COMMON_ONN BIT(16) |
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#define U2P_R0_FSEL_MASK GENMASK(19, 17) |
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#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) |
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#define U2P_R0_POWER_ON_RESET BIT(22) |
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#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) |
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#define U2P_R0_ID_SET_ID_DQ BIT(25) |
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#define U2P_R0_ATE_RESET BIT(26) |
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#define U2P_R0_FSV_MINUS BIT(27) |
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#define U2P_R0_FSV_PLUS BIT(28) |
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#define U2P_R0_BYPASS_DM_DATA BIT(29) |
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#define U2P_R0_BYPASS_DP_DATA BIT(30) |
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#define U2P_R1 0x4 |
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#define U2P_R1_BURN_IN_TEST BIT(0) |
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#define U2P_R1_ACA_ENABLE BIT(1) |
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#define U2P_R1_DCD_ENABLE BIT(2) |
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#define U2P_R1_VDAT_SRC_EN_B BIT(3) |
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#define U2P_R1_VDAT_DET_EN_B BIT(4) |
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#define U2P_R1_CHARGES_SEL BIT(5) |
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#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) |
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#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) |
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#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) |
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#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) |
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#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) |
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#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) |
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#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) |
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#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) |
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#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) |
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#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) |
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/* bits [31:14] are read-only */ |
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#define U2P_R2 0x8 |
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#define U2P_R2_TESTDATA_IN_MASK GENMASK(7, 0) |
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#define U2P_R2_TESTADDR_MASK GENMASK(11, 8) |
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#define U2P_R2_TESTDATA_OUT_SEL BIT(12) |
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#define U2P_R2_TESTCLK BIT(13) |
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#define U2P_R2_TESTDATA_OUT_MASK GENMASK(17, 14) |
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#define U2P_R2_ACA_PIN_RANGE_C BIT(18) |
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#define U2P_R2_ACA_PIN_RANGE_B BIT(19) |
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#define U2P_R2_ACA_PIN_RANGE_A BIT(20) |
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#define U2P_R2_ACA_PIN_GND BIT(21) |
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#define U2P_R2_ACA_PIN_FLOAT BIT(22) |
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#define U2P_R2_CHARGE_DETECT BIT(23) |
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#define U2P_R2_DEVICE_SESSION_VALID BIT(24) |
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#define U2P_R2_ADP_PROBE BIT(25) |
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#define U2P_R2_ADP_SENSE BIT(26) |
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#define U2P_R2_SESSION_END BIT(27) |
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#define U2P_R2_VBUS_VALID BIT(28) |
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#define U2P_R2_B_VALID BIT(29) |
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#define U2P_R2_A_VALID BIT(30) |
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#define U2P_R2_ID_DIG BIT(31) |
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#define U2P_R3 0xc |
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#define RESET_COMPLETE_TIME 500 |
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struct phy_meson_gxl_usb2_priv { |
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struct regmap *regmap; |
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enum phy_mode mode; |
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int is_enabled; |
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struct clk *clk; |
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struct reset_control *reset; |
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}; |
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static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { |
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.reg_bits = 8, |
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.val_bits = 32, |
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.reg_stride = 4, |
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.max_register = U2P_R3, |
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}; |
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static int phy_meson_gxl_usb2_init(struct phy *phy) |
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{ |
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struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); |
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int ret; |
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ret = reset_control_reset(priv->reset); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(priv->clk); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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static int phy_meson_gxl_usb2_exit(struct phy *phy) |
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{ |
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struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); |
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clk_disable_unprepare(priv->clk); |
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return 0; |
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} |
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static int phy_meson_gxl_usb2_reset(struct phy *phy) |
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{ |
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struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); |
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if (priv->is_enabled) { |
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/* reset the PHY and wait until settings are stabilized */ |
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regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET, |
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U2P_R0_POWER_ON_RESET); |
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udelay(RESET_COMPLETE_TIME); |
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regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET, |
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0); |
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udelay(RESET_COMPLETE_TIME); |
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} |
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return 0; |
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} |
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static int phy_meson_gxl_usb2_set_mode(struct phy *phy, |
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enum phy_mode mode, int submode) |
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{ |
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struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); |
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switch (mode) { |
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case PHY_MODE_USB_HOST: |
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case PHY_MODE_USB_OTG: |
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regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DM_PULLDOWN, |
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U2P_R0_DM_PULLDOWN); |
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regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DP_PULLDOWN, |
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U2P_R0_DP_PULLDOWN); |
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regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_ID_PULLUP, |
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U2P_R0_ID_PULLUP); |
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break; |
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case PHY_MODE_USB_DEVICE: |
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regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DM_PULLDOWN, |
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0); |
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regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DP_PULLDOWN, |
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0); |
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regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_ID_PULLUP, |
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U2P_R0_ID_PULLUP); |
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break; |
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default: |
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return -EINVAL; |
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} |
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phy_meson_gxl_usb2_reset(phy); |
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priv->mode = mode; |
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return 0; |
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} |
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static int phy_meson_gxl_usb2_power_off(struct phy *phy) |
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{ |
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struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); |
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priv->is_enabled = 0; |
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/* power off the PHY by putting it into reset mode */ |
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regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET, |
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U2P_R0_POWER_ON_RESET); |
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return 0; |
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} |
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static int phy_meson_gxl_usb2_power_on(struct phy *phy) |
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{ |
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struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); |
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int ret; |
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priv->is_enabled = 1; |
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/* power on the PHY by taking it out of reset mode */ |
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regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET, 0); |
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ret = phy_meson_gxl_usb2_set_mode(phy, priv->mode, 0); |
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if (ret) { |
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phy_meson_gxl_usb2_power_off(phy); |
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dev_err(&phy->dev, "Failed to initialize PHY with mode %d\n", |
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priv->mode); |
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return ret; |
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} |
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return 0; |
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} |
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static const struct phy_ops phy_meson_gxl_usb2_ops = { |
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.init = phy_meson_gxl_usb2_init, |
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.exit = phy_meson_gxl_usb2_exit, |
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.power_on = phy_meson_gxl_usb2_power_on, |
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.power_off = phy_meson_gxl_usb2_power_off, |
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.set_mode = phy_meson_gxl_usb2_set_mode, |
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.reset = phy_meson_gxl_usb2_reset, |
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.owner = THIS_MODULE, |
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}; |
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static int phy_meson_gxl_usb2_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct phy_provider *phy_provider; |
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struct phy_meson_gxl_usb2_priv *priv; |
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struct phy *phy; |
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void __iomem *base; |
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int ret; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, priv); |
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base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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/* start in host mode */ |
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priv->mode = PHY_MODE_USB_HOST; |
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priv->regmap = devm_regmap_init_mmio(dev, base, |
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&phy_meson_gxl_usb2_regmap_conf); |
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if (IS_ERR(priv->regmap)) |
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return PTR_ERR(priv->regmap); |
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priv->clk = devm_clk_get_optional(dev, "phy"); |
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if (IS_ERR(priv->clk)) |
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return PTR_ERR(priv->clk); |
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priv->reset = devm_reset_control_get_optional_shared(dev, "phy"); |
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if (IS_ERR(priv->reset)) |
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return PTR_ERR(priv->reset); |
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phy = devm_phy_create(dev, NULL, &phy_meson_gxl_usb2_ops); |
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if (IS_ERR(phy)) { |
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ret = PTR_ERR(phy); |
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if (ret != -EPROBE_DEFER) |
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dev_err(dev, "failed to create PHY\n"); |
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return ret; |
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} |
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phy_set_drvdata(phy, priv); |
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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} |
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static const struct of_device_id phy_meson_gxl_usb2_of_match[] = { |
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{ .compatible = "amlogic,meson-gxl-usb2-phy", }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, phy_meson_gxl_usb2_of_match); |
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static struct platform_driver phy_meson_gxl_usb2_driver = { |
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.probe = phy_meson_gxl_usb2_probe, |
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.driver = { |
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.name = "phy-meson-gxl-usb2", |
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.of_match_table = phy_meson_gxl_usb2_of_match, |
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}, |
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}; |
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module_platform_driver(phy_meson_gxl_usb2_driver); |
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MODULE_AUTHOR("Martin Blumenstingl <[email protected]>"); |
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MODULE_DESCRIPTION("Meson GXL and GXM USB2 PHY driver"); |
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MODULE_LICENSE("GPL v2");
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