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174 lines
5.0 KiB
174 lines
5.0 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Private structs/constants for PARISC IOSAPIC support |
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* |
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* Copyright (C) 2000 Hewlett Packard (Grant Grundler) |
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* Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org) |
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* Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org) |
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*/ |
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/* |
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** This file is private to iosapic driver. |
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** If stuff needs to be used by another driver, move it to a common file. |
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** |
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** WARNING: fields most data structures here are ordered to make sure |
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** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8) |
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*/ |
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/* |
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** Interrupt Routing Stuff |
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** ----------------------- |
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** The interrupt routing table consists of entries derived from |
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** MP Specification Draft 1.5. There is one interrupt routing |
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** table per cell. N- and L-class consist of a single cell. |
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*/ |
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struct irt_entry { |
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/* Entry Type 139 identifies an I/O SAPIC interrupt entry */ |
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u8 entry_type; |
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/* Entry Length 16 indicates entry is 16 bytes long */ |
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u8 entry_length; |
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/* |
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** Interrupt Type of 0 indicates a vectored interrupt, |
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** all other values are reserved |
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*/ |
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u8 interrupt_type; |
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/* |
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** PO and EL |
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** Polarity of SAPIC I/O input signals: |
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** 00 = Reserved |
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** 01 = Active high |
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** 10 = Reserved |
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** 11 = Active low |
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** Trigger mode of SAPIC I/O input signals: |
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** 00 = Reserved |
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** 01 = Edge-triggered |
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** 10 = Reserved |
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** 11 = Level-triggered |
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*/ |
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u8 polarity_trigger; |
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/* |
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** IRQ and DEVNO |
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** irq identifies PCI interrupt signal where |
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** 0x0 corresponds to INT_A#, |
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** 0x1 corresponds to INT_B#, |
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** 0x2 corresponds to INT_C# |
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** 0x3 corresponds to INT_D# |
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** PCI device number where interrupt originates |
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*/ |
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u8 src_bus_irq_devno; |
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/* Source Bus ID identifies the bus where interrupt signal comes from */ |
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u8 src_bus_id; |
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/* |
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** Segment ID is unique across a protection domain and |
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** identifies a segment of PCI buses (reserved in |
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** MP Specification Draft 1.5) |
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*/ |
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u8 src_seg_id; |
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/* |
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** Destination I/O SAPIC INTIN# identifies the INTIN n pin |
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** to which the signal is connected |
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*/ |
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u8 dest_iosapic_intin; |
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/* |
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** Destination I/O SAPIC Address identifies the I/O SAPIC |
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** to which the signal is connected |
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*/ |
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u64 dest_iosapic_addr; |
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}; |
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#define IRT_IOSAPIC_TYPE 139 |
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#define IRT_IOSAPIC_LENGTH 16 |
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#define IRT_VECTORED_INTR 0 |
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#define IRT_PO_MASK 0x3 |
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#define IRT_ACTIVE_HI 1 |
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#define IRT_ACTIVE_LO 3 |
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#define IRT_EL_MASK 0x3 |
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#define IRT_EL_SHIFT 2 |
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#define IRT_EDGE_TRIG 1 |
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#define IRT_LEVEL_TRIG 3 |
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#define IRT_IRQ_MASK 0x3 |
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#define IRT_DEV_MASK 0x1f |
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#define IRT_DEV_SHIFT 2 |
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#define IRT_IRQ_DEVNO_MASK ((IRT_DEV_MASK << IRT_DEV_SHIFT) | IRT_IRQ_MASK) |
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#ifdef SUPPORT_MULTI_CELL |
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struct iosapic_irt { |
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struct iosapic_irt *irt_next; /* next routing table */ |
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struct irt_entry *irt_base; /* intr routing table address */ |
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size_t irte_count; /* number of entries in the table */ |
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size_t irte_size; /* size (bytes) of each entry */ |
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}; |
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#endif |
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struct vector_info { |
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struct iosapic_info *iosapic; /* I/O SAPIC this vector is on */ |
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struct irt_entry *irte; /* IRT entry */ |
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u32 __iomem *eoi_addr; /* precalculate EOI reg address */ |
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u32 eoi_data; /* IA64: ? PA: swapped txn_data */ |
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int txn_irq; /* virtual IRQ number for processor */ |
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ulong txn_addr; /* IA64: id_eid PA: partial HPA */ |
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u32 txn_data; /* CPU interrupt bit */ |
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u8 status; /* status/flags */ |
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u8 irqline; /* INTINn(IRQ) */ |
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}; |
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struct iosapic_info { |
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struct iosapic_info * isi_next; /* list of I/O SAPIC */ |
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void __iomem * addr; /* remapped address */ |
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unsigned long isi_hpa; /* physical base address */ |
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struct vector_info * isi_vector; /* IRdT (IRQ line) array */ |
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int isi_num_vectors; /* size of IRdT array */ |
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int isi_status; /* status/flags */ |
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unsigned int isi_version; /* DEBUG: data fr version reg */ |
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}; |
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#ifdef __IA64__ |
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/* |
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** PA risc does NOT have any local sapics. IA64 does. |
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** PIB (Processor Interrupt Block) is handled by Astro or Dew (Stretch CEC). |
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** |
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** PA: Get id_eid from IRT and hardcode PIB to 0xfeeNNNN0 |
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** Emulate the data on PAT platforms. |
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*/ |
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struct local_sapic_info { |
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struct local_sapic_info *lsi_next; /* point to next CPU info */ |
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int *lsi_cpu_id; /* point to logical CPU id */ |
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unsigned long *lsi_id_eid; /* point to IA-64 CPU id */ |
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int *lsi_status; /* point to CPU status */ |
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void *lsi_private; /* point to special info */ |
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}; |
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/* |
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** "root" data structure which ties everything together. |
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** Should always be able to start with sapic_root and locate |
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** the desired information. |
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*/ |
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struct sapic_info { |
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struct sapic_info *si_next; /* info is per cell */ |
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int si_cellid; /* cell id */ |
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unsigned int si_status; /* status */ |
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char *si_pib_base; /* intr blk base address */ |
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local_sapic_info_t *si_local_info; |
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io_sapic_info_t *si_io_info; |
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extint_info_t *si_extint_info;/* External Intr info */ |
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}; |
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#endif |
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