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1122 lines
28 KiB
1122 lines
28 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* This file is part of wl1271 |
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* |
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* Copyright (C) 1998-2009 Texas Instruments. All rights reserved. |
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* Copyright (C) 2008-2010 Nokia Corporation |
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* |
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* Contact: Luciano Coelho <[email protected]> |
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*/ |
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#ifndef __ACX_H__ |
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#define __ACX_H__ |
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#include "wlcore.h" |
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#include "cmd.h" |
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/************************************************************************* |
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Host Interrupt Register (WiLink -> Host) |
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**************************************************************************/ |
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/* HW Initiated interrupt Watchdog timer expiration */ |
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#define WL1271_ACX_INTR_WATCHDOG BIT(0) |
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/* Init sequence is done (masked interrupt, detection through polling only ) */ |
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#define WL1271_ACX_INTR_INIT_COMPLETE BIT(1) |
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/* Event was entered to Event MBOX #A*/ |
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#define WL1271_ACX_INTR_EVENT_A BIT(2) |
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/* Event was entered to Event MBOX #B*/ |
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#define WL1271_ACX_INTR_EVENT_B BIT(3) |
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/* Command processing completion*/ |
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#define WL1271_ACX_INTR_CMD_COMPLETE BIT(4) |
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/* Signaling the host on HW wakeup */ |
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#define WL1271_ACX_INTR_HW_AVAILABLE BIT(5) |
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/* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */ |
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#define WL1271_ACX_INTR_DATA BIT(6) |
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/* Trace message on MBOX #A */ |
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#define WL1271_ACX_INTR_TRACE_A BIT(7) |
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/* Trace message on MBOX #B */ |
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#define WL1271_ACX_INTR_TRACE_B BIT(8) |
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/* SW FW Initiated interrupt Watchdog timer expiration */ |
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#define WL1271_ACX_SW_INTR_WATCHDOG BIT(9) |
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#define WL1271_ACX_INTR_ALL 0xFFFFFFFF |
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/* all possible interrupts - only appropriate ones will be masked in */ |
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#define WLCORE_ALL_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \ |
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WL1271_ACX_INTR_EVENT_A | \ |
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WL1271_ACX_INTR_EVENT_B | \ |
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WL1271_ACX_INTR_HW_AVAILABLE | \ |
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WL1271_ACX_INTR_DATA | \ |
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WL1271_ACX_SW_INTR_WATCHDOG) |
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/* Target's information element */ |
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struct acx_header { |
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struct wl1271_cmd_header cmd; |
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/* acx (or information element) header */ |
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__le16 id; |
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/* payload length (not including headers */ |
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__le16 len; |
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} __packed; |
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struct acx_error_counter { |
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struct acx_header header; |
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/* The number of PLCP errors since the last time this */ |
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/* information element was interrogated. This field is */ |
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/* automatically cleared when it is interrogated.*/ |
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__le32 PLCP_error; |
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/* The number of FCS errors since the last time this */ |
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/* information element was interrogated. This field is */ |
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/* automatically cleared when it is interrogated.*/ |
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__le32 FCS_error; |
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/* The number of MPDUs without PLCP header errors received*/ |
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/* since the last time this information element was interrogated. */ |
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/* This field is automatically cleared when it is interrogated.*/ |
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__le32 valid_frame; |
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/* the number of missed sequence numbers in the squentially */ |
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/* values of frames seq numbers */ |
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__le32 seq_num_miss; |
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} __packed; |
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enum wl12xx_role { |
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WL1271_ROLE_STA = 0, |
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WL1271_ROLE_IBSS, |
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WL1271_ROLE_AP, |
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WL1271_ROLE_DEVICE, |
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WL1271_ROLE_P2P_CL, |
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WL1271_ROLE_P2P_GO, |
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WL1271_ROLE_MESH_POINT, |
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WL12XX_INVALID_ROLE_TYPE = 0xff |
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}; |
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enum wl1271_psm_mode { |
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/* Active mode */ |
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WL1271_PSM_CAM = 0, |
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/* Power save mode */ |
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WL1271_PSM_PS = 1, |
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/* Extreme low power */ |
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WL1271_PSM_ELP = 2, |
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WL1271_PSM_MAX = WL1271_PSM_ELP, |
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/* illegal out of band value of PSM mode */ |
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WL1271_PSM_ILLEGAL = 0xff |
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}; |
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struct acx_sleep_auth { |
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struct acx_header header; |
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/* The sleep level authorization of the device. */ |
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/* 0 - Always active*/ |
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/* 1 - Power down mode: light / fast sleep*/ |
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/* 2 - ELP mode: Deep / Max sleep*/ |
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u8 sleep_auth; |
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u8 padding[3]; |
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} __packed; |
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enum { |
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HOSTIF_PCI_MASTER_HOST_INDIRECT, |
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HOSTIF_PCI_MASTER_HOST_DIRECT, |
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HOSTIF_SLAVE, |
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HOSTIF_PKT_RING, |
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HOSTIF_DONTCARE = 0xFF |
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}; |
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#define DEFAULT_UCAST_PRIORITY 0 |
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#define DEFAULT_RX_Q_PRIORITY 0 |
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#define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */ |
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#define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */ |
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#define TRACE_BUFFER_MAX_SIZE 256 |
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#define DP_RX_PACKET_RING_CHUNK_SIZE 1600 |
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#define DP_TX_PACKET_RING_CHUNK_SIZE 1600 |
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#define DP_RX_PACKET_RING_CHUNK_NUM 2 |
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#define DP_TX_PACKET_RING_CHUNK_NUM 2 |
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#define DP_TX_COMPLETE_TIME_OUT 20 |
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#define TX_MSDU_LIFETIME_MIN 0 |
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#define TX_MSDU_LIFETIME_MAX 3000 |
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#define TX_MSDU_LIFETIME_DEF 512 |
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#define RX_MSDU_LIFETIME_MIN 0 |
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#define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF |
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#define RX_MSDU_LIFETIME_DEF 512000 |
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struct acx_rx_msdu_lifetime { |
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struct acx_header header; |
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/* |
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* The maximum amount of time, in TU, before the |
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* firmware discards the MSDU. |
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*/ |
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__le32 lifetime; |
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} __packed; |
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enum acx_slot_type { |
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SLOT_TIME_LONG = 0, |
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SLOT_TIME_SHORT = 1, |
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DEFAULT_SLOT_TIME = SLOT_TIME_SHORT, |
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MAX_SLOT_TIMES = 0xFF |
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}; |
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#define STATION_WONE_INDEX 0 |
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struct acx_slot { |
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struct acx_header header; |
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u8 role_id; |
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u8 wone_index; /* Reserved */ |
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u8 slot_time; |
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u8 reserved[5]; |
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} __packed; |
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#define ACX_MC_ADDRESS_GROUP_MAX (8) |
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#define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX) |
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struct acx_dot11_grp_addr_tbl { |
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struct acx_header header; |
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u8 role_id; |
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u8 enabled; |
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u8 num_groups; |
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u8 pad[1]; |
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u8 mac_table[ADDRESS_GROUP_MAX_LEN]; |
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} __packed; |
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struct acx_rx_timeout { |
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struct acx_header header; |
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u8 role_id; |
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u8 reserved; |
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__le16 ps_poll_timeout; |
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__le16 upsd_timeout; |
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u8 padding[2]; |
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} __packed; |
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struct acx_rts_threshold { |
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struct acx_header header; |
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u8 role_id; |
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u8 reserved; |
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__le16 threshold; |
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} __packed; |
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struct acx_beacon_filter_option { |
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struct acx_header header; |
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u8 role_id; |
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u8 enable; |
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/* |
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* The number of beacons without the unicast TIM |
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* bit set that the firmware buffers before |
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* signaling the host about ready frames. |
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* When set to 0 and the filter is enabled, beacons |
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* without the unicast TIM bit set are dropped. |
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*/ |
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u8 max_num_beacons; |
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u8 pad[1]; |
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} __packed; |
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/* |
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* ACXBeaconFilterEntry (not 221) |
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* Byte Offset Size (Bytes) Definition |
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* =========== ============ ========== |
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* 0 1 IE identifier |
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* 1 1 Treatment bit mask |
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* |
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* ACXBeaconFilterEntry (221) |
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* Byte Offset Size (Bytes) Definition |
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* =========== ============ ========== |
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* 0 1 IE identifier |
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* 1 1 Treatment bit mask |
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* 2 3 OUI |
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* 5 1 Type |
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* 6 2 Version |
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* |
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* |
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* Treatment bit mask - The information element handling: |
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* bit 0 - The information element is compared and transferred |
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* in case of change. |
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* bit 1 - The information element is transferred to the host |
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* with each appearance or disappearance. |
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* Note that both bits can be set at the same time. |
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*/ |
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#define BEACON_FILTER_TABLE_MAX_IE_NUM (32) |
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#define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6) |
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#define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2) |
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#define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6) |
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#define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \ |
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BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \ |
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(BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \ |
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BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE)) |
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struct acx_beacon_filter_ie_table { |
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struct acx_header header; |
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u8 role_id; |
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u8 num_ie; |
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u8 pad[2]; |
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u8 table[BEACON_FILTER_TABLE_MAX_SIZE]; |
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} __packed; |
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struct acx_conn_monit_params { |
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struct acx_header header; |
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u8 role_id; |
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u8 padding[3]; |
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__le32 synch_fail_thold; /* number of beacons missed */ |
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__le32 bss_lose_timeout; /* number of TU's from synch fail */ |
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} __packed; |
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struct acx_bt_wlan_coex { |
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struct acx_header header; |
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u8 enable; |
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u8 pad[3]; |
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} __packed; |
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struct acx_bt_wlan_coex_param { |
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struct acx_header header; |
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__le32 params[WLCORE_CONF_SG_PARAMS_MAX]; |
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u8 param_idx; |
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u8 padding[3]; |
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} __packed; |
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struct acx_dco_itrim_params { |
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struct acx_header header; |
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u8 enable; |
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u8 padding[3]; |
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__le32 timeout; |
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} __packed; |
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struct acx_energy_detection { |
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struct acx_header header; |
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/* The RX Clear Channel Assessment threshold in the PHY */ |
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__le16 rx_cca_threshold; |
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u8 tx_energy_detection; |
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u8 pad; |
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} __packed; |
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struct acx_beacon_broadcast { |
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struct acx_header header; |
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u8 role_id; |
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/* Enables receiving of broadcast packets in PS mode */ |
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u8 rx_broadcast_in_ps; |
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__le16 beacon_rx_timeout; |
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__le16 broadcast_timeout; |
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/* Consecutive PS Poll failures before updating the host */ |
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u8 ps_poll_threshold; |
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u8 pad[1]; |
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} __packed; |
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struct acx_event_mask { |
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struct acx_header header; |
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__le32 event_mask; |
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__le32 high_event_mask; /* Unused */ |
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} __packed; |
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#define SCAN_PASSIVE BIT(0) |
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#define SCAN_5GHZ_BAND BIT(1) |
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#define SCAN_TRIGGERED BIT(2) |
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#define SCAN_PRIORITY_HIGH BIT(3) |
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/* When set, disable HW encryption */ |
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#define DF_ENCRYPTION_DISABLE 0x01 |
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#define DF_SNIFF_MODE_ENABLE 0x80 |
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struct acx_feature_config { |
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struct acx_header header; |
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u8 role_id; |
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u8 padding[3]; |
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__le32 options; |
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__le32 data_flow_options; |
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} __packed; |
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struct acx_current_tx_power { |
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struct acx_header header; |
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u8 role_id; |
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u8 current_tx_power; |
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u8 padding[2]; |
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} __packed; |
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struct acx_wake_up_condition { |
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struct acx_header header; |
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u8 role_id; |
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u8 wake_up_event; /* Only one bit can be set */ |
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u8 listen_interval; |
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u8 pad[1]; |
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} __packed; |
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struct acx_aid { |
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struct acx_header header; |
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/* |
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* To be set when associated with an AP. |
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*/ |
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u8 role_id; |
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u8 reserved; |
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__le16 aid; |
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} __packed; |
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enum acx_preamble_type { |
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ACX_PREAMBLE_LONG = 0, |
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ACX_PREAMBLE_SHORT = 1 |
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}; |
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struct acx_preamble { |
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struct acx_header header; |
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/* |
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* When set, the WiLink transmits the frames with a short preamble and |
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* when cleared, the WiLink transmits the frames with a long preamble. |
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*/ |
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u8 role_id; |
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u8 preamble; |
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u8 padding[2]; |
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} __packed; |
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enum acx_ctsprotect_type { |
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CTSPROTECT_DISABLE = 0, |
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CTSPROTECT_ENABLE = 1 |
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}; |
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struct acx_ctsprotect { |
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struct acx_header header; |
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u8 role_id; |
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u8 ctsprotect; |
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u8 padding[2]; |
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} __packed; |
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struct acx_rate_class { |
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__le32 enabled_rates; |
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u8 short_retry_limit; |
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u8 long_retry_limit; |
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u8 aflags; |
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u8 reserved; |
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}; |
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struct acx_rate_policy { |
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struct acx_header header; |
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__le32 rate_policy_idx; |
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struct acx_rate_class rate_policy; |
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} __packed; |
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struct acx_ac_cfg { |
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struct acx_header header; |
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u8 role_id; |
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u8 ac; |
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u8 aifsn; |
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u8 cw_min; |
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__le16 cw_max; |
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__le16 tx_op_limit; |
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} __packed; |
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struct acx_tid_config { |
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struct acx_header header; |
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u8 role_id; |
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u8 queue_id; |
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u8 channel_type; |
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u8 tsid; |
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u8 ps_scheme; |
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u8 ack_policy; |
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u8 padding[2]; |
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__le32 apsd_conf[2]; |
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} __packed; |
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struct acx_frag_threshold { |
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struct acx_header header; |
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__le16 frag_threshold; |
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u8 padding[2]; |
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} __packed; |
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struct acx_tx_config_options { |
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struct acx_header header; |
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__le16 tx_compl_timeout; /* msec */ |
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__le16 tx_compl_threshold; /* number of packets */ |
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} __packed; |
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struct wl12xx_acx_config_memory { |
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struct acx_header header; |
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u8 rx_mem_block_num; |
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u8 tx_min_mem_block_num; |
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u8 num_stations; |
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u8 num_ssid_profiles; |
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__le32 total_tx_descriptors; |
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u8 dyn_mem_enable; |
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u8 tx_free_req; |
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u8 rx_free_req; |
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u8 tx_min; |
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u8 fwlog_blocks; |
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u8 padding[3]; |
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} __packed; |
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struct wl1271_acx_mem_map { |
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struct acx_header header; |
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__le32 code_start; |
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__le32 code_end; |
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__le32 wep_defkey_start; |
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__le32 wep_defkey_end; |
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__le32 sta_table_start; |
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__le32 sta_table_end; |
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__le32 packet_template_start; |
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__le32 packet_template_end; |
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/* Address of the TX result interface (control block) */ |
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__le32 tx_result; |
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__le32 tx_result_queue_start; |
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__le32 queue_memory_start; |
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__le32 queue_memory_end; |
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__le32 packet_memory_pool_start; |
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__le32 packet_memory_pool_end; |
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|
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__le32 debug_buffer1_start; |
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__le32 debug_buffer1_end; |
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|
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__le32 debug_buffer2_start; |
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__le32 debug_buffer2_end; |
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|
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/* Number of blocks FW allocated for TX packets */ |
|
__le32 num_tx_mem_blocks; |
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|
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/* Number of blocks FW allocated for RX packets */ |
|
__le32 num_rx_mem_blocks; |
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|
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/* the following 4 fields are valid in SLAVE mode only */ |
|
u8 *tx_cbuf; |
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u8 *rx_cbuf; |
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__le32 rx_ctrl; |
|
__le32 tx_ctrl; |
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} __packed; |
|
|
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struct wl1271_acx_rx_config_opt { |
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struct acx_header header; |
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|
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__le16 mblk_threshold; |
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__le16 threshold; |
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__le16 timeout; |
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u8 queue_type; |
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u8 reserved; |
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} __packed; |
|
|
|
|
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struct wl1271_acx_bet_enable { |
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struct acx_header header; |
|
|
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u8 role_id; |
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u8 enable; |
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u8 max_consecutive; |
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u8 padding[1]; |
|
} __packed; |
|
|
|
#define ACX_IPV4_VERSION 4 |
|
#define ACX_IPV6_VERSION 6 |
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#define ACX_IPV4_ADDR_SIZE 4 |
|
|
|
/* bitmap of enabled arp_filter features */ |
|
#define ACX_ARP_FILTER_ARP_FILTERING BIT(0) |
|
#define ACX_ARP_FILTER_AUTO_ARP BIT(1) |
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|
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struct wl1271_acx_arp_filter { |
|
struct acx_header header; |
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u8 role_id; |
|
u8 version; /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */ |
|
u8 enable; /* bitmap of enabled ARP filtering features */ |
|
u8 padding[1]; |
|
u8 address[16]; /* The configured device IP address - all ARP |
|
requests directed to this IP address will pass |
|
through. For IPv4, the first four bytes are |
|
used. */ |
|
} __packed; |
|
|
|
struct wl1271_acx_pm_config { |
|
struct acx_header header; |
|
|
|
__le32 host_clk_settling_time; |
|
u8 host_fast_wakeup_support; |
|
u8 padding[3]; |
|
} __packed; |
|
|
|
struct wl1271_acx_keep_alive_mode { |
|
struct acx_header header; |
|
|
|
u8 role_id; |
|
u8 enabled; |
|
u8 padding[2]; |
|
} __packed; |
|
|
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enum { |
|
ACX_KEEP_ALIVE_NO_TX = 0, |
|
ACX_KEEP_ALIVE_PERIOD_ONLY |
|
}; |
|
|
|
enum { |
|
ACX_KEEP_ALIVE_TPL_INVALID = 0, |
|
ACX_KEEP_ALIVE_TPL_VALID |
|
}; |
|
|
|
struct wl1271_acx_keep_alive_config { |
|
struct acx_header header; |
|
|
|
u8 role_id; |
|
u8 index; |
|
u8 tpl_validation; |
|
u8 trigger; |
|
__le32 period; |
|
} __packed; |
|
|
|
/* TODO: maybe this needs to be moved somewhere else? */ |
|
#define HOST_IF_CFG_RX_FIFO_ENABLE BIT(0) |
|
#define HOST_IF_CFG_TX_EXTRA_BLKS_SWAP BIT(1) |
|
#define HOST_IF_CFG_TX_PAD_TO_SDIO_BLK BIT(3) |
|
#define HOST_IF_CFG_RX_PAD_TO_SDIO_BLK BIT(4) |
|
#define HOST_IF_CFG_ADD_RX_ALIGNMENT BIT(6) |
|
|
|
enum { |
|
WL1271_ACX_TRIG_TYPE_LEVEL = 0, |
|
WL1271_ACX_TRIG_TYPE_EDGE, |
|
}; |
|
|
|
enum { |
|
WL1271_ACX_TRIG_DIR_LOW = 0, |
|
WL1271_ACX_TRIG_DIR_HIGH, |
|
WL1271_ACX_TRIG_DIR_BIDIR, |
|
}; |
|
|
|
enum { |
|
WL1271_ACX_TRIG_ENABLE = 1, |
|
WL1271_ACX_TRIG_DISABLE, |
|
}; |
|
|
|
enum { |
|
WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0, |
|
WL1271_ACX_TRIG_METRIC_RSSI_DATA, |
|
WL1271_ACX_TRIG_METRIC_SNR_BEACON, |
|
WL1271_ACX_TRIG_METRIC_SNR_DATA, |
|
}; |
|
|
|
enum { |
|
WL1271_ACX_TRIG_IDX_RSSI = 0, |
|
WL1271_ACX_TRIG_COUNT = 8, |
|
}; |
|
|
|
struct wl1271_acx_rssi_snr_trigger { |
|
struct acx_header header; |
|
|
|
u8 role_id; |
|
u8 metric; |
|
u8 type; |
|
u8 dir; |
|
__le16 threshold; |
|
__le16 pacing; /* 0 - 60000 ms */ |
|
u8 hysteresis; |
|
u8 index; |
|
u8 enable; |
|
u8 padding[1]; |
|
}; |
|
|
|
struct wl1271_acx_rssi_snr_avg_weights { |
|
struct acx_header header; |
|
|
|
u8 role_id; |
|
u8 padding[3]; |
|
u8 rssi_beacon; |
|
u8 rssi_data; |
|
u8 snr_beacon; |
|
u8 snr_data; |
|
}; |
|
|
|
|
|
/* special capability bit (not employed by the 802.11n spec) */ |
|
#define WL12XX_HT_CAP_HT_OPERATION BIT(16) |
|
|
|
/* |
|
* ACX_PEER_HT_CAP |
|
* Configure HT capabilities - declare the capabilities of the peer |
|
* we are connected to. |
|
*/ |
|
struct wl1271_acx_ht_capabilities { |
|
struct acx_header header; |
|
|
|
/* bitmask of capability bits supported by the peer */ |
|
__le32 ht_capabilites; |
|
|
|
/* Indicates to which link these capabilities apply. */ |
|
u8 hlid; |
|
|
|
/* |
|
* This the maximum A-MPDU length supported by the AP. The FW may not |
|
* exceed this length when sending A-MPDUs |
|
*/ |
|
u8 ampdu_max_length; |
|
|
|
/* This is the minimal spacing required when sending A-MPDUs to the AP*/ |
|
u8 ampdu_min_spacing; |
|
|
|
u8 padding; |
|
} __packed; |
|
|
|
/* |
|
* ACX_HT_BSS_OPERATION |
|
* Configure HT capabilities - AP rules for behavior in the BSS. |
|
*/ |
|
struct wl1271_acx_ht_information { |
|
struct acx_header header; |
|
|
|
u8 role_id; |
|
|
|
/* Values: 0 - RIFS not allowed, 1 - RIFS allowed */ |
|
u8 rifs_mode; |
|
|
|
/* Values: 0 - 3 like in spec */ |
|
u8 ht_protection; |
|
|
|
/* Values: 0 - GF protection not required, 1 - GF protection required */ |
|
u8 gf_protection; |
|
|
|
/*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/ |
|
u8 ht_tx_burst_limit; |
|
|
|
/* |
|
* Values: 0 - Dual CTS protection not required, |
|
* 1 - Dual CTS Protection required |
|
* Note: When this value is set to 1 FW will protect all TXOP with RTS |
|
* frame and will not use CTS-to-self regardless of the value of the |
|
* ACX_CTS_PROTECTION information element |
|
*/ |
|
u8 dual_cts_protection; |
|
|
|
u8 padding[2]; |
|
} __packed; |
|
|
|
struct wl1271_acx_ba_initiator_policy { |
|
struct acx_header header; |
|
|
|
/* Specifies role Id, Range 0-7, 0xFF means ANY role. */ |
|
u8 role_id; |
|
|
|
/* |
|
* Per TID setting for allowing TX BA. Set a bit to 1 to allow |
|
* TX BA sessions for the corresponding TID. |
|
*/ |
|
u8 tid_bitmap; |
|
|
|
/* Windows size in number of packets */ |
|
u8 win_size; |
|
|
|
u8 padding1[1]; |
|
|
|
/* As initiator inactivity timeout in time units(TU) of 1024us */ |
|
u16 inactivity_timeout; |
|
|
|
u8 padding[2]; |
|
} __packed; |
|
|
|
struct wl1271_acx_ba_receiver_setup { |
|
struct acx_header header; |
|
|
|
/* Specifies link id, range 0-31 */ |
|
u8 hlid; |
|
|
|
u8 tid; |
|
|
|
u8 enable; |
|
|
|
/* Windows size in number of packets */ |
|
u8 win_size; |
|
|
|
/* BA session starting sequence number. RANGE 0-FFF */ |
|
u16 ssn; |
|
|
|
u8 padding[2]; |
|
} __packed; |
|
|
|
struct wl12xx_acx_fw_tsf_information { |
|
struct acx_header header; |
|
|
|
u8 role_id; |
|
u8 padding1[3]; |
|
__le32 current_tsf_high; |
|
__le32 current_tsf_low; |
|
__le32 last_bttt_high; |
|
__le32 last_tbtt_low; |
|
u8 last_dtim_count; |
|
u8 padding2[3]; |
|
} __packed; |
|
|
|
struct wl1271_acx_ps_rx_streaming { |
|
struct acx_header header; |
|
|
|
u8 role_id; |
|
u8 tid; |
|
u8 enable; |
|
|
|
/* interval between triggers (10-100 msec) */ |
|
u8 period; |
|
|
|
/* timeout before first trigger (0-200 msec) */ |
|
u8 timeout; |
|
u8 padding[3]; |
|
} __packed; |
|
|
|
struct wl1271_acx_ap_max_tx_retry { |
|
struct acx_header header; |
|
|
|
u8 role_id; |
|
u8 padding_1; |
|
|
|
/* |
|
* the number of frames transmission failures before |
|
* issuing the aging event. |
|
*/ |
|
__le16 max_tx_retry; |
|
} __packed; |
|
|
|
struct wl1271_acx_config_ps { |
|
struct acx_header header; |
|
|
|
u8 exit_retries; |
|
u8 enter_retries; |
|
u8 padding[2]; |
|
__le32 null_data_rate; |
|
} __packed; |
|
|
|
struct wl1271_acx_inconnection_sta { |
|
struct acx_header header; |
|
|
|
u8 addr[ETH_ALEN]; |
|
u8 role_id; |
|
u8 padding; |
|
} __packed; |
|
|
|
/* |
|
* ACX_FM_COEX_CFG |
|
* set the FM co-existence parameters. |
|
*/ |
|
struct wl1271_acx_fm_coex { |
|
struct acx_header header; |
|
/* enable(1) / disable(0) the FM Coex feature */ |
|
u8 enable; |
|
/* |
|
* Swallow period used in COEX PLL swallowing mechanism. |
|
* 0xFF = use FW default |
|
*/ |
|
u8 swallow_period; |
|
/* |
|
* The N divider used in COEX PLL swallowing mechanism for Fref of |
|
* 38.4/19.2 Mhz. 0xFF = use FW default |
|
*/ |
|
u8 n_divider_fref_set_1; |
|
/* |
|
* The N divider used in COEX PLL swallowing mechanism for Fref of |
|
* 26/52 Mhz. 0xFF = use FW default |
|
*/ |
|
u8 n_divider_fref_set_2; |
|
/* |
|
* The M divider used in COEX PLL swallowing mechanism for Fref of |
|
* 38.4/19.2 Mhz. 0xFFFF = use FW default |
|
*/ |
|
__le16 m_divider_fref_set_1; |
|
/* |
|
* The M divider used in COEX PLL swallowing mechanism for Fref of |
|
* 26/52 Mhz. 0xFFFF = use FW default |
|
*/ |
|
__le16 m_divider_fref_set_2; |
|
/* |
|
* The time duration in uSec required for COEX PLL to stabilize. |
|
* 0xFFFFFFFF = use FW default |
|
*/ |
|
__le32 coex_pll_stabilization_time; |
|
/* |
|
* The time duration in uSec required for LDO to stabilize. |
|
* 0xFFFFFFFF = use FW default |
|
*/ |
|
__le16 ldo_stabilization_time; |
|
/* |
|
* The disturbed frequency band margin around the disturbed frequency |
|
* center (single sided). |
|
* For example, if 2 is configured, the following channels will be |
|
* considered disturbed channel: |
|
* 80 +- 0.1 MHz, 91 +- 0.1 MHz, 98 +- 0.1 MHz, 102 +- 0.1 MH |
|
* 0xFF = use FW default |
|
*/ |
|
u8 fm_disturbed_band_margin; |
|
/* |
|
* The swallow clock difference of the swallowing mechanism. |
|
* 0xFF = use FW default |
|
*/ |
|
u8 swallow_clk_diff; |
|
} __packed; |
|
|
|
#define ACX_RATE_MGMT_ALL_PARAMS 0xff |
|
struct wl12xx_acx_set_rate_mgmt_params { |
|
struct acx_header header; |
|
|
|
u8 index; /* 0xff to configure all params */ |
|
u8 padding1; |
|
__le16 rate_retry_score; |
|
__le16 per_add; |
|
__le16 per_th1; |
|
__le16 per_th2; |
|
__le16 max_per; |
|
u8 inverse_curiosity_factor; |
|
u8 tx_fail_low_th; |
|
u8 tx_fail_high_th; |
|
u8 per_alpha_shift; |
|
u8 per_add_shift; |
|
u8 per_beta1_shift; |
|
u8 per_beta2_shift; |
|
u8 rate_check_up; |
|
u8 rate_check_down; |
|
u8 rate_retry_policy[ACX_RATE_MGMT_NUM_OF_RATES]; |
|
u8 padding2[2]; |
|
} __packed; |
|
|
|
struct wl12xx_acx_config_hangover { |
|
struct acx_header header; |
|
|
|
__le32 recover_time; |
|
u8 hangover_period; |
|
u8 dynamic_mode; |
|
u8 early_termination_mode; |
|
u8 max_period; |
|
u8 min_period; |
|
u8 increase_delta; |
|
u8 decrease_delta; |
|
u8 quiet_time; |
|
u8 increase_time; |
|
u8 window_size; |
|
u8 padding[2]; |
|
} __packed; |
|
|
|
|
|
struct acx_default_rx_filter { |
|
struct acx_header header; |
|
u8 enable; |
|
|
|
/* action of type FILTER_XXX */ |
|
u8 default_action; |
|
|
|
u8 pad[2]; |
|
} __packed; |
|
|
|
|
|
struct acx_rx_filter_cfg { |
|
struct acx_header header; |
|
|
|
u8 enable; |
|
|
|
/* 0 - WL1271_MAX_RX_FILTERS-1 */ |
|
u8 index; |
|
|
|
u8 action; |
|
|
|
u8 num_fields; |
|
u8 fields[]; |
|
} __packed; |
|
|
|
struct acx_roaming_stats { |
|
struct acx_header header; |
|
|
|
u8 role_id; |
|
u8 pad[3]; |
|
u32 missed_beacons; |
|
u8 snr_data; |
|
u8 snr_bacon; |
|
s8 rssi_data; |
|
s8 rssi_beacon; |
|
} __packed; |
|
|
|
enum { |
|
ACX_WAKE_UP_CONDITIONS = 0x0000, |
|
ACX_MEM_CFG = 0x0001, |
|
ACX_SLOT = 0x0002, |
|
ACX_AC_CFG = 0x0003, |
|
ACX_MEM_MAP = 0x0004, |
|
ACX_AID = 0x0005, |
|
ACX_MEDIUM_USAGE = 0x0006, |
|
ACX_STATISTICS = 0x0007, |
|
ACX_PWR_CONSUMPTION_STATISTICS = 0x0008, |
|
ACX_TID_CFG = 0x0009, |
|
ACX_PS_RX_STREAMING = 0x000A, |
|
ACX_BEACON_FILTER_OPT = 0x000B, |
|
ACX_NOISE_HIST = 0x000C, |
|
ACX_HDK_VERSION = 0x000D, |
|
ACX_PD_THRESHOLD = 0x000E, |
|
ACX_TX_CONFIG_OPT = 0x000F, |
|
ACX_CCA_THRESHOLD = 0x0010, |
|
ACX_EVENT_MBOX_MASK = 0x0011, |
|
ACX_CONN_MONIT_PARAMS = 0x0012, |
|
ACX_DISABLE_BROADCASTS = 0x0013, |
|
ACX_BCN_DTIM_OPTIONS = 0x0014, |
|
ACX_SG_ENABLE = 0x0015, |
|
ACX_SG_CFG = 0x0016, |
|
ACX_FM_COEX_CFG = 0x0017, |
|
ACX_BEACON_FILTER_TABLE = 0x0018, |
|
ACX_ARP_IP_FILTER = 0x0019, |
|
ACX_ROAMING_STATISTICS_TBL = 0x001A, |
|
ACX_RATE_POLICY = 0x001B, |
|
ACX_CTS_PROTECTION = 0x001C, |
|
ACX_SLEEP_AUTH = 0x001D, |
|
ACX_PREAMBLE_TYPE = 0x001E, |
|
ACX_ERROR_CNT = 0x001F, |
|
ACX_IBSS_FILTER = 0x0020, |
|
ACX_SERVICE_PERIOD_TIMEOUT = 0x0021, |
|
ACX_TSF_INFO = 0x0022, |
|
ACX_CONFIG_PS_WMM = 0x0023, |
|
ACX_ENABLE_RX_DATA_FILTER = 0x0024, |
|
ACX_SET_RX_DATA_FILTER = 0x0025, |
|
ACX_GET_DATA_FILTER_STATISTICS = 0x0026, |
|
ACX_RX_CONFIG_OPT = 0x0027, |
|
ACX_FRAG_CFG = 0x0028, |
|
ACX_BET_ENABLE = 0x0029, |
|
ACX_RSSI_SNR_TRIGGER = 0x002A, |
|
ACX_RSSI_SNR_WEIGHTS = 0x002B, |
|
ACX_KEEP_ALIVE_MODE = 0x002C, |
|
ACX_SET_KEEP_ALIVE_CONFIG = 0x002D, |
|
ACX_BA_SESSION_INIT_POLICY = 0x002E, |
|
ACX_BA_SESSION_RX_SETUP = 0x002F, |
|
ACX_PEER_HT_CAP = 0x0030, |
|
ACX_HT_BSS_OPERATION = 0x0031, |
|
ACX_COEX_ACTIVITY = 0x0032, |
|
ACX_BURST_MODE = 0x0033, |
|
ACX_SET_RATE_MGMT_PARAMS = 0x0034, |
|
ACX_GET_RATE_MGMT_PARAMS = 0x0035, |
|
ACX_SET_RATE_ADAPT_PARAMS = 0x0036, |
|
ACX_SET_DCO_ITRIM_PARAMS = 0x0037, |
|
ACX_GEN_FW_CMD = 0x0038, |
|
ACX_HOST_IF_CFG_BITMAP = 0x0039, |
|
ACX_MAX_TX_FAILURE = 0x003A, |
|
ACX_UPDATE_INCONNECTION_STA_LIST = 0x003B, |
|
DOT11_RX_MSDU_LIFE_TIME = 0x003C, |
|
DOT11_CUR_TX_PWR = 0x003D, |
|
DOT11_RTS_THRESHOLD = 0x003E, |
|
DOT11_GROUP_ADDRESS_TBL = 0x003F, |
|
ACX_PM_CONFIG = 0x0040, |
|
ACX_CONFIG_PS = 0x0041, |
|
ACX_CONFIG_HANGOVER = 0x0042, |
|
ACX_FEATURE_CFG = 0x0043, |
|
ACX_PROTECTION_CFG = 0x0044, |
|
}; |
|
|
|
|
|
int wl1271_acx_wake_up_conditions(struct wl1271 *wl, |
|
struct wl12xx_vif *wlvif, |
|
u8 wake_up_event, u8 listen_interval); |
|
int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth); |
|
int wl1271_acx_tx_power(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
int power); |
|
int wl1271_acx_feature_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
|
int wl1271_acx_mem_map(struct wl1271 *wl, |
|
struct acx_header *mem_map, size_t len); |
|
int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl); |
|
int wl1271_acx_slot(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
enum acx_slot_type slot_time); |
|
int wl1271_acx_group_address_tbl(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
bool enable, void *mc_list, u32 mc_list_len); |
|
int wl1271_acx_service_period_timeout(struct wl1271 *wl, |
|
struct wl12xx_vif *wlvif); |
|
int wl1271_acx_rts_threshold(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
u32 rts_threshold); |
|
int wl1271_acx_dco_itrim_params(struct wl1271 *wl); |
|
int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
bool enable_filter); |
|
int wl1271_acx_beacon_filter_table(struct wl1271 *wl, |
|
struct wl12xx_vif *wlvif); |
|
int wl1271_acx_conn_monit_params(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
bool enable); |
|
int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable); |
|
int wl12xx_acx_sg_cfg(struct wl1271 *wl); |
|
int wl1271_acx_cca_threshold(struct wl1271 *wl); |
|
int wl1271_acx_bcn_dtim_options(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
|
int wl1271_acx_aid(struct wl1271 *wl, struct wl12xx_vif *wlvif, u16 aid); |
|
int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask); |
|
int wl1271_acx_set_preamble(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
enum acx_preamble_type preamble); |
|
int wl1271_acx_cts_protect(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
enum acx_ctsprotect_type ctsprotect); |
|
int wl1271_acx_statistics(struct wl1271 *wl, void *stats); |
|
int wl1271_acx_sta_rate_policies(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
|
int wl1271_acx_ap_rate_policy(struct wl1271 *wl, struct conf_tx_rate_class *c, |
|
u8 idx); |
|
int wl1271_acx_ac_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
u8 ac, u8 cw_min, u16 cw_max, u8 aifsn, u16 txop); |
|
int wl1271_acx_tid_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
u8 queue_id, u8 channel_type, |
|
u8 tsid, u8 ps_scheme, u8 ack_policy, |
|
u32 apsd_conf0, u32 apsd_conf1); |
|
int wl1271_acx_frag_threshold(struct wl1271 *wl, u32 frag_threshold); |
|
int wl1271_acx_tx_config_options(struct wl1271 *wl); |
|
int wl12xx_acx_mem_cfg(struct wl1271 *wl); |
|
int wl1271_acx_init_mem_config(struct wl1271 *wl); |
|
int wl1271_acx_init_rx_interrupt(struct wl1271 *wl); |
|
int wl1271_acx_smart_reflex(struct wl1271 *wl); |
|
int wl1271_acx_bet_enable(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
bool enable); |
|
int wl1271_acx_arp_ip_filter(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
u8 enable, __be32 address); |
|
int wl1271_acx_pm_config(struct wl1271 *wl); |
|
int wl1271_acx_keep_alive_mode(struct wl1271 *wl, struct wl12xx_vif *vif, |
|
bool enable); |
|
int wl1271_acx_keep_alive_config(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
u8 index, u8 tpl_valid); |
|
int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
bool enable, s16 thold, u8 hyst); |
|
int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl, |
|
struct wl12xx_vif *wlvif); |
|
int wl1271_acx_set_ht_capabilities(struct wl1271 *wl, |
|
struct ieee80211_sta_ht_cap *ht_cap, |
|
bool allow_ht_operation, u8 hlid); |
|
int wl1271_acx_set_ht_information(struct wl1271 *wl, |
|
struct wl12xx_vif *wlvif, |
|
u16 ht_operation_mode); |
|
int wl12xx_acx_set_ba_initiator_policy(struct wl1271 *wl, |
|
struct wl12xx_vif *wlvif); |
|
int wl12xx_acx_set_ba_receiver_session(struct wl1271 *wl, u8 tid_index, |
|
u16 ssn, bool enable, u8 peer_hlid, |
|
u8 win_size); |
|
int wl12xx_acx_tsf_info(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
u64 *mactime); |
|
int wl1271_acx_ps_rx_streaming(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
|
bool enable); |
|
int wl1271_acx_ap_max_tx_retry(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
|
int wl12xx_acx_config_ps(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
|
int wl1271_acx_set_inconnection_sta(struct wl1271 *wl, |
|
struct wl12xx_vif *wlvif, u8 *addr); |
|
int wl1271_acx_fm_coex(struct wl1271 *wl); |
|
int wl12xx_acx_set_rate_mgmt_params(struct wl1271 *wl); |
|
int wl12xx_acx_config_hangover(struct wl1271 *wl); |
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int wlcore_acx_average_rssi(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
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s8 *avg_rssi); |
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int wl1271_acx_default_rx_filter_enable(struct wl1271 *wl, bool enable, |
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enum rx_filter_action action); |
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int wl1271_acx_set_rx_filter(struct wl1271 *wl, u8 index, bool enable, |
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struct wl12xx_rx_filter *filter); |
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#endif /* __WL1271_ACX_H__ */
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