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292 lines
8.3 KiB
292 lines
8.3 KiB
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause |
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/* |
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* Copyright (C) 2018-2021 Intel Corporation |
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*/ |
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#include "iwl-trans.h" |
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#include "iwl-fh.h" |
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#include "iwl-context-info-gen3.h" |
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#include "internal.h" |
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#include "iwl-prph.h" |
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static void |
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iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans, |
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struct iwl_prph_scratch_hwm_cfg *dbg_cfg, |
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u32 *control_flags) |
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{ |
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enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; |
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struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; |
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u32 dbg_flags = 0; |
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if (!iwl_trans_dbg_ini_valid(trans)) { |
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struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; |
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iwl_pcie_alloc_fw_monitor(trans, 0); |
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if (fw_mon->size) { |
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dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; |
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IWL_DEBUG_FW(trans, |
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"WRT: Applying DRAM buffer destination\n"); |
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dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); |
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dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); |
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} |
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goto out; |
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} |
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fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id]; |
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switch (le32_to_cpu(fw_mon_cfg->buf_location)) { |
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case IWL_FW_INI_LOCATION_SRAM_PATH: |
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dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL; |
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IWL_DEBUG_FW(trans, |
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"WRT: Applying SMEM buffer destination\n"); |
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break; |
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case IWL_FW_INI_LOCATION_NPK_PATH: |
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dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF; |
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IWL_DEBUG_FW(trans, |
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"WRT: Applying NPK buffer destination\n"); |
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break; |
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case IWL_FW_INI_LOCATION_DRAM_PATH: |
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if (trans->dbg.fw_mon_ini[alloc_id].num_frags) { |
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struct iwl_dram_data *frag = |
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&trans->dbg.fw_mon_ini[alloc_id].frags[0]; |
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dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; |
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dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical); |
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dbg_cfg->hwm_size = cpu_to_le32(frag->size); |
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IWL_DEBUG_FW(trans, |
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"WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n", |
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alloc_id, |
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trans->dbg.fw_mon_ini[alloc_id].num_frags); |
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} |
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break; |
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default: |
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IWL_ERR(trans, "WRT: Invalid buffer destination\n"); |
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} |
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out: |
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if (dbg_flags) |
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*control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags; |
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} |
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int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, |
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const struct fw_img *fw) |
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{ |
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
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struct iwl_context_info_gen3 *ctxt_info_gen3; |
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struct iwl_prph_scratch *prph_scratch; |
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struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; |
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struct iwl_prph_info *prph_info; |
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void *iml_img; |
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u32 control_flags = 0; |
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int ret; |
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int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE, |
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trans->cfg->min_txq_size); |
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switch (trans_pcie->rx_buf_size) { |
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case IWL_AMSDU_DEF: |
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return -EINVAL; |
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case IWL_AMSDU_2K: |
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break; |
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case IWL_AMSDU_4K: |
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control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; |
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break; |
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case IWL_AMSDU_8K: |
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control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; |
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/* if firmware supports the ext size, tell it */ |
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control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K; |
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break; |
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case IWL_AMSDU_12K: |
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control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; |
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/* if firmware supports the ext size, tell it */ |
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control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K; |
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break; |
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} |
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/* Allocate prph scratch */ |
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prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), |
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&trans_pcie->prph_scratch_dma_addr, |
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GFP_KERNEL); |
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if (!prph_scratch) |
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return -ENOMEM; |
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prph_sc_ctrl = &prph_scratch->ctrl_cfg; |
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prph_sc_ctrl->version.version = 0; |
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prph_sc_ctrl->version.mac_id = |
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cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV)); |
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prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); |
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control_flags |= IWL_PRPH_SCRATCH_MTR_MODE; |
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control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT; |
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/* initialize RX default queue */ |
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prph_sc_ctrl->rbd_cfg.free_rbd_addr = |
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cpu_to_le64(trans_pcie->rxq->bd_dma); |
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iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, |
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&control_flags); |
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prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); |
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/* allocate ucode sections in dram and set addresses */ |
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ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); |
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if (ret) |
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goto err_free_prph_scratch; |
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/* Allocate prph information |
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* currently we don't assign to the prph info anything, but it would get |
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* assigned later */ |
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prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info), |
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&trans_pcie->prph_info_dma_addr, |
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GFP_KERNEL); |
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if (!prph_info) { |
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ret = -ENOMEM; |
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goto err_free_prph_scratch; |
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} |
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/* Allocate context info */ |
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ctxt_info_gen3 = dma_alloc_coherent(trans->dev, |
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sizeof(*ctxt_info_gen3), |
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&trans_pcie->ctxt_info_dma_addr, |
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GFP_KERNEL); |
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if (!ctxt_info_gen3) { |
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ret = -ENOMEM; |
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goto err_free_prph_info; |
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} |
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ctxt_info_gen3->prph_info_base_addr = |
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cpu_to_le64(trans_pcie->prph_info_dma_addr); |
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ctxt_info_gen3->prph_scratch_base_addr = |
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cpu_to_le64(trans_pcie->prph_scratch_dma_addr); |
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ctxt_info_gen3->prph_scratch_size = |
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cpu_to_le32(sizeof(*prph_scratch)); |
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ctxt_info_gen3->cr_head_idx_arr_base_addr = |
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cpu_to_le64(trans_pcie->rxq->rb_stts_dma); |
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ctxt_info_gen3->tr_tail_idx_arr_base_addr = |
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cpu_to_le64(trans_pcie->rxq->tr_tail_dma); |
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ctxt_info_gen3->cr_tail_idx_arr_base_addr = |
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cpu_to_le64(trans_pcie->rxq->cr_tail_dma); |
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ctxt_info_gen3->cr_idx_arr_size = |
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cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS); |
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ctxt_info_gen3->tr_idx_arr_size = |
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cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS); |
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ctxt_info_gen3->mtr_base_addr = |
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cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr); |
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ctxt_info_gen3->mcr_base_addr = |
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cpu_to_le64(trans_pcie->rxq->used_bd_dma); |
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ctxt_info_gen3->mtr_size = |
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cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size)); |
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ctxt_info_gen3->mcr_size = |
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cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds)); |
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trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; |
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trans_pcie->prph_info = prph_info; |
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trans_pcie->prph_scratch = prph_scratch; |
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/* Allocate IML */ |
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iml_img = dma_alloc_coherent(trans->dev, trans->iml_len, |
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&trans_pcie->iml_dma_addr, GFP_KERNEL); |
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if (!iml_img) { |
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ret = -ENOMEM; |
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goto err_free_ctxt_info; |
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} |
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memcpy(iml_img, trans->iml, trans->iml_len); |
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iwl_enable_fw_load_int_ctx_info(trans); |
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/* kick FW self load */ |
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iwl_write64(trans, CSR_CTXT_INFO_ADDR, |
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trans_pcie->ctxt_info_dma_addr); |
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iwl_write64(trans, CSR_IML_DATA_ADDR, |
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trans_pcie->iml_dma_addr); |
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iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); |
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iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, |
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CSR_AUTO_FUNC_BOOT_ENA); |
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return 0; |
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err_free_ctxt_info: |
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dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), |
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trans_pcie->ctxt_info_gen3, |
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trans_pcie->ctxt_info_dma_addr); |
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trans_pcie->ctxt_info_gen3 = NULL; |
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err_free_prph_info: |
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dma_free_coherent(trans->dev, |
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sizeof(*prph_info), |
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prph_info, |
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trans_pcie->prph_info_dma_addr); |
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err_free_prph_scratch: |
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dma_free_coherent(trans->dev, |
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sizeof(*prph_scratch), |
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prph_scratch, |
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trans_pcie->prph_scratch_dma_addr); |
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return ret; |
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} |
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void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans) |
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{ |
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
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if (!trans_pcie->ctxt_info_gen3) |
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return; |
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dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), |
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trans_pcie->ctxt_info_gen3, |
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trans_pcie->ctxt_info_dma_addr); |
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trans_pcie->ctxt_info_dma_addr = 0; |
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trans_pcie->ctxt_info_gen3 = NULL; |
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iwl_pcie_ctxt_info_free_fw_img(trans); |
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dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), |
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trans_pcie->prph_scratch, |
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trans_pcie->prph_scratch_dma_addr); |
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trans_pcie->prph_scratch_dma_addr = 0; |
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trans_pcie->prph_scratch = NULL; |
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dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info), |
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trans_pcie->prph_info, |
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trans_pcie->prph_info_dma_addr); |
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trans_pcie->prph_info_dma_addr = 0; |
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trans_pcie->prph_info = NULL; |
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} |
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int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, |
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const void *data, u32 len) |
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{ |
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
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struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = |
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&trans_pcie->prph_scratch->ctrl_cfg; |
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int ret; |
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if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) |
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return 0; |
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/* only allocate the DRAM if not allocated yet */ |
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if (!trans->pnvm_loaded) { |
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if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size)) |
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return -EBUSY; |
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ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len, |
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&trans_pcie->pnvm_dram); |
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if (ret < 0) { |
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IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n", |
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ret); |
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return ret; |
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} |
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} |
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prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = |
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cpu_to_le64(trans_pcie->pnvm_dram.physical); |
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prph_sc_ctrl->pnvm_cfg.pnvm_size = |
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cpu_to_le32(trans_pcie->pnvm_dram.size); |
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return 0; |
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}
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