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115 lines
3.7 KiB
115 lines
3.7 KiB
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
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/* |
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* Copyright (C) 2005-2014, 2019-2020 Intel Corporation |
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* Copyright (C) 2013-2015 Intel Mobile Communications GmbH |
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* Copyright (C) 2016-2017 Intel Deutschland GmbH |
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*/ |
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#ifndef __iwl_fw_api_txq_h__ |
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#define __iwl_fw_api_txq_h__ |
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/* |
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* DQA queue numbers |
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* |
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* @IWL_MVM_DQA_CMD_QUEUE: a queue reserved for sending HCMDs to the FW |
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* @IWL_MVM_DQA_AUX_QUEUE: a queue reserved for aux frames |
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* @IWL_MVM_DQA_P2P_DEVICE_QUEUE: a queue reserved for P2P device frames |
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* @IWL_MVM_DQA_INJECT_MONITOR_QUEUE: a queue reserved for injection using |
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* monitor mode. Note this queue is the same as the queue for P2P device |
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* but we can't have active monitor mode along with P2P device anyway. |
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* @IWL_MVM_DQA_GCAST_QUEUE: a queue reserved for P2P GO/SoftAP GCAST frames |
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* @IWL_MVM_DQA_BSS_CLIENT_QUEUE: a queue reserved for BSS activity, to ensure |
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* that we are never left without the possibility to connect to an AP. |
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* @IWL_MVM_DQA_MIN_MGMT_QUEUE: first TXQ in pool for MGMT and non-QOS frames. |
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* Each MGMT queue is mapped to a single STA |
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* MGMT frames are frames that return true on ieee80211_is_mgmt() |
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* @IWL_MVM_DQA_MAX_MGMT_QUEUE: last TXQ in pool for MGMT frames |
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* @IWL_MVM_DQA_AP_PROBE_RESP_QUEUE: a queue reserved for P2P GO/SoftAP probe |
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* responses |
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* @IWL_MVM_DQA_MIN_DATA_QUEUE: first TXQ in pool for DATA frames. |
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* DATA frames are intended for !ieee80211_is_mgmt() frames, but if |
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* the MGMT TXQ pool is exhausted, mgmt frames can be sent on DATA queues |
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* as well |
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* @IWL_MVM_DQA_MAX_DATA_QUEUE: last TXQ in pool for DATA frames |
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*/ |
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enum iwl_mvm_dqa_txq { |
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IWL_MVM_DQA_CMD_QUEUE = 0, |
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IWL_MVM_DQA_AUX_QUEUE = 1, |
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IWL_MVM_DQA_P2P_DEVICE_QUEUE = 2, |
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IWL_MVM_DQA_INJECT_MONITOR_QUEUE = 2, |
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IWL_MVM_DQA_GCAST_QUEUE = 3, |
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IWL_MVM_DQA_BSS_CLIENT_QUEUE = 4, |
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IWL_MVM_DQA_MIN_MGMT_QUEUE = 5, |
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IWL_MVM_DQA_MAX_MGMT_QUEUE = 8, |
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IWL_MVM_DQA_AP_PROBE_RESP_QUEUE = 9, |
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IWL_MVM_DQA_MIN_DATA_QUEUE = 10, |
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IWL_MVM_DQA_MAX_DATA_QUEUE = 30, |
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}; |
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enum iwl_mvm_tx_fifo { |
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IWL_MVM_TX_FIFO_BK = 0, |
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IWL_MVM_TX_FIFO_BE, |
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IWL_MVM_TX_FIFO_VI, |
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IWL_MVM_TX_FIFO_VO, |
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IWL_MVM_TX_FIFO_MCAST = 5, |
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IWL_MVM_TX_FIFO_CMD = 7, |
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}; |
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enum iwl_gen2_tx_fifo { |
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IWL_GEN2_TX_FIFO_CMD = 0, |
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IWL_GEN2_EDCA_TX_FIFO_BK, |
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IWL_GEN2_EDCA_TX_FIFO_BE, |
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IWL_GEN2_EDCA_TX_FIFO_VI, |
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IWL_GEN2_EDCA_TX_FIFO_VO, |
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IWL_GEN2_TRIG_TX_FIFO_BK, |
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IWL_GEN2_TRIG_TX_FIFO_BE, |
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IWL_GEN2_TRIG_TX_FIFO_VI, |
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IWL_GEN2_TRIG_TX_FIFO_VO, |
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}; |
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/** |
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* enum iwl_tx_queue_cfg_actions - TXQ config options |
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* @TX_QUEUE_CFG_ENABLE_QUEUE: enable a queue |
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* @TX_QUEUE_CFG_TFD_SHORT_FORMAT: use short TFD format |
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*/ |
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enum iwl_tx_queue_cfg_actions { |
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TX_QUEUE_CFG_ENABLE_QUEUE = BIT(0), |
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TX_QUEUE_CFG_TFD_SHORT_FORMAT = BIT(1), |
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}; |
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#define IWL_DEFAULT_QUEUE_SIZE 256 |
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#define IWL_MGMT_QUEUE_SIZE 16 |
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#define IWL_CMD_QUEUE_SIZE 32 |
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/** |
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* struct iwl_tx_queue_cfg_cmd - txq hw scheduler config command |
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* @sta_id: station id |
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* @tid: tid of the queue |
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* @flags: see &enum iwl_tx_queue_cfg_actions |
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* @cb_size: size of TFD cyclic buffer. Value is exponent - 3. |
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* Minimum value 0 (8 TFDs), maximum value 5 (256 TFDs) |
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* @byte_cnt_addr: address of byte count table |
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* @tfdq_addr: address of TFD circular buffer |
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*/ |
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struct iwl_tx_queue_cfg_cmd { |
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u8 sta_id; |
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u8 tid; |
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__le16 flags; |
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__le32 cb_size; |
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__le64 byte_cnt_addr; |
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__le64 tfdq_addr; |
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} __packed; /* TX_QUEUE_CFG_CMD_API_S_VER_2 */ |
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/** |
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* struct iwl_tx_queue_cfg_rsp - response to txq hw scheduler config |
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* @queue_number: queue number assigned to this RA -TID |
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* @flags: set on failure |
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* @write_pointer: initial value for write pointer |
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* @reserved: reserved |
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*/ |
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struct iwl_tx_queue_cfg_rsp { |
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__le16 queue_number; |
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__le16 flags; |
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__le16 write_pointer; |
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__le16 reserved; |
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} __packed; /* TX_QUEUE_CFG_RSP_API_S_VER_2 */ |
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#endif /* __iwl_fw_api_txq_h__ */
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