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1391 lines
35 KiB
1391 lines
35 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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Broadcom B43legacy wireless driver |
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DMA ringbuffer and descriptor allocation/management |
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Copyright (c) 2005, 2006 Michael Buesch <[email protected]> |
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Some code in this file is derived from the b44.c driver |
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Copyright (C) 2002 David S. Miller |
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Copyright (C) Pekka Pietikainen |
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*/ |
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#include "b43legacy.h" |
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#include "dma.h" |
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#include "main.h" |
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#include "debugfs.h" |
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#include "xmit.h" |
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#include <linux/dma-mapping.h> |
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#include <linux/pci.h> |
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#include <linux/delay.h> |
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#include <linux/skbuff.h> |
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#include <linux/slab.h> |
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#include <net/dst.h> |
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/* 32bit DMA ops. */ |
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static |
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struct b43legacy_dmadesc32 *op32_idx2desc(struct b43legacy_dmaring *ring, |
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int slot, |
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struct b43legacy_dmadesc_meta **meta) |
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{ |
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struct b43legacy_dmadesc32 *desc; |
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*meta = &(ring->meta[slot]); |
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desc = ring->descbase; |
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desc = &(desc[slot]); |
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return desc; |
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} |
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static void op32_fill_descriptor(struct b43legacy_dmaring *ring, |
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struct b43legacy_dmadesc32 *desc, |
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dma_addr_t dmaaddr, u16 bufsize, |
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int start, int end, int irq) |
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{ |
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struct b43legacy_dmadesc32 *descbase = ring->descbase; |
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int slot; |
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u32 ctl; |
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u32 addr; |
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u32 addrext; |
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slot = (int)(desc - descbase); |
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B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); |
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addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK); |
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addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK) |
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>> SSB_DMA_TRANSLATION_SHIFT; |
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addr |= ring->dev->dma.translation; |
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ctl = (bufsize - ring->frameoffset) |
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& B43legacy_DMA32_DCTL_BYTECNT; |
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if (slot == ring->nr_slots - 1) |
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ctl |= B43legacy_DMA32_DCTL_DTABLEEND; |
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if (start) |
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ctl |= B43legacy_DMA32_DCTL_FRAMESTART; |
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if (end) |
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ctl |= B43legacy_DMA32_DCTL_FRAMEEND; |
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if (irq) |
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ctl |= B43legacy_DMA32_DCTL_IRQ; |
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ctl |= (addrext << B43legacy_DMA32_DCTL_ADDREXT_SHIFT) |
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& B43legacy_DMA32_DCTL_ADDREXT_MASK; |
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desc->control = cpu_to_le32(ctl); |
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desc->address = cpu_to_le32(addr); |
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} |
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static void op32_poke_tx(struct b43legacy_dmaring *ring, int slot) |
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{ |
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b43legacy_dma_write(ring, B43legacy_DMA32_TXINDEX, |
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(u32)(slot * sizeof(struct b43legacy_dmadesc32))); |
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} |
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static void op32_tx_suspend(struct b43legacy_dmaring *ring) |
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{ |
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b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL, |
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b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL) |
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| B43legacy_DMA32_TXSUSPEND); |
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} |
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static void op32_tx_resume(struct b43legacy_dmaring *ring) |
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{ |
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b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL, |
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b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL) |
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& ~B43legacy_DMA32_TXSUSPEND); |
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} |
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static int op32_get_current_rxslot(struct b43legacy_dmaring *ring) |
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{ |
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u32 val; |
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val = b43legacy_dma_read(ring, B43legacy_DMA32_RXSTATUS); |
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val &= B43legacy_DMA32_RXDPTR; |
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return (val / sizeof(struct b43legacy_dmadesc32)); |
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} |
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static void op32_set_current_rxslot(struct b43legacy_dmaring *ring, |
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int slot) |
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{ |
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b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX, |
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(u32)(slot * sizeof(struct b43legacy_dmadesc32))); |
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} |
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static inline int free_slots(struct b43legacy_dmaring *ring) |
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{ |
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return (ring->nr_slots - ring->used_slots); |
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} |
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static inline int next_slot(struct b43legacy_dmaring *ring, int slot) |
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{ |
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B43legacy_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1)); |
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if (slot == ring->nr_slots - 1) |
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return 0; |
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return slot + 1; |
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} |
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static inline int prev_slot(struct b43legacy_dmaring *ring, int slot) |
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{ |
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B43legacy_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1)); |
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if (slot == 0) |
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return ring->nr_slots - 1; |
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return slot - 1; |
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} |
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#ifdef CONFIG_B43LEGACY_DEBUG |
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static void update_max_used_slots(struct b43legacy_dmaring *ring, |
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int current_used_slots) |
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{ |
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if (current_used_slots <= ring->max_used_slots) |
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return; |
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ring->max_used_slots = current_used_slots; |
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if (b43legacy_debug(ring->dev, B43legacy_DBG_DMAVERBOSE)) |
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b43legacydbg(ring->dev->wl, |
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"max_used_slots increased to %d on %s ring %d\n", |
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ring->max_used_slots, |
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ring->tx ? "TX" : "RX", |
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ring->index); |
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} |
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#else |
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static inline |
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void update_max_used_slots(struct b43legacy_dmaring *ring, |
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int current_used_slots) |
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{ } |
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#endif /* DEBUG */ |
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|
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/* Request a slot for usage. */ |
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static inline |
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int request_slot(struct b43legacy_dmaring *ring) |
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{ |
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int slot; |
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|
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B43legacy_WARN_ON(!ring->tx); |
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B43legacy_WARN_ON(ring->stopped); |
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B43legacy_WARN_ON(free_slots(ring) == 0); |
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slot = next_slot(ring, ring->current_slot); |
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ring->current_slot = slot; |
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ring->used_slots++; |
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|
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update_max_used_slots(ring, ring->used_slots); |
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return slot; |
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} |
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/* Mac80211-queue to b43legacy-ring mapping */ |
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static struct b43legacy_dmaring *priority_to_txring( |
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struct b43legacy_wldev *dev, |
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int queue_priority) |
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{ |
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struct b43legacy_dmaring *ring; |
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|
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/*FIXME: For now we always run on TX-ring-1 */ |
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return dev->dma.tx_ring1; |
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|
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/* 0 = highest priority */ |
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switch (queue_priority) { |
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default: |
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B43legacy_WARN_ON(1); |
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fallthrough; |
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case 0: |
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ring = dev->dma.tx_ring3; |
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break; |
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case 1: |
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ring = dev->dma.tx_ring2; |
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break; |
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case 2: |
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ring = dev->dma.tx_ring1; |
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break; |
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case 3: |
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ring = dev->dma.tx_ring0; |
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break; |
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case 4: |
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ring = dev->dma.tx_ring4; |
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break; |
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case 5: |
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ring = dev->dma.tx_ring5; |
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break; |
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} |
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return ring; |
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} |
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/* Bcm4301-ring to mac80211-queue mapping */ |
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static inline int txring_to_priority(struct b43legacy_dmaring *ring) |
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{ |
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static const u8 idx_to_prio[] = |
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{ 3, 2, 1, 0, 4, 5, }; |
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|
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/*FIXME: have only one queue, for now */ |
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return 0; |
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return idx_to_prio[ring->index]; |
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} |
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static u16 b43legacy_dmacontroller_base(enum b43legacy_dmatype type, |
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int controller_idx) |
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{ |
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static const u16 map32[] = { |
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B43legacy_MMIO_DMA32_BASE0, |
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B43legacy_MMIO_DMA32_BASE1, |
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B43legacy_MMIO_DMA32_BASE2, |
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B43legacy_MMIO_DMA32_BASE3, |
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B43legacy_MMIO_DMA32_BASE4, |
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B43legacy_MMIO_DMA32_BASE5, |
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}; |
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B43legacy_WARN_ON(!(controller_idx >= 0 && |
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controller_idx < ARRAY_SIZE(map32))); |
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return map32[controller_idx]; |
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} |
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|
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static inline |
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dma_addr_t map_descbuffer(struct b43legacy_dmaring *ring, |
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unsigned char *buf, |
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size_t len, |
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int tx) |
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{ |
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dma_addr_t dmaaddr; |
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if (tx) |
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dmaaddr = dma_map_single(ring->dev->dev->dma_dev, |
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buf, len, |
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DMA_TO_DEVICE); |
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else |
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dmaaddr = dma_map_single(ring->dev->dev->dma_dev, |
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buf, len, |
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DMA_FROM_DEVICE); |
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return dmaaddr; |
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} |
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static inline |
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void unmap_descbuffer(struct b43legacy_dmaring *ring, |
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dma_addr_t addr, |
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size_t len, |
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int tx) |
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{ |
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if (tx) |
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dma_unmap_single(ring->dev->dev->dma_dev, |
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addr, len, |
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DMA_TO_DEVICE); |
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else |
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dma_unmap_single(ring->dev->dev->dma_dev, |
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addr, len, |
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DMA_FROM_DEVICE); |
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} |
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static inline |
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void sync_descbuffer_for_cpu(struct b43legacy_dmaring *ring, |
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dma_addr_t addr, |
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size_t len) |
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{ |
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B43legacy_WARN_ON(ring->tx); |
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|
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dma_sync_single_for_cpu(ring->dev->dev->dma_dev, |
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addr, len, DMA_FROM_DEVICE); |
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} |
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static inline |
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void sync_descbuffer_for_device(struct b43legacy_dmaring *ring, |
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dma_addr_t addr, |
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size_t len) |
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{ |
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B43legacy_WARN_ON(ring->tx); |
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|
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dma_sync_single_for_device(ring->dev->dev->dma_dev, |
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addr, len, DMA_FROM_DEVICE); |
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} |
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static inline |
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void free_descriptor_buffer(struct b43legacy_dmaring *ring, |
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struct b43legacy_dmadesc_meta *meta, |
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int irq_context) |
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{ |
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if (meta->skb) { |
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if (irq_context) |
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dev_kfree_skb_irq(meta->skb); |
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else |
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dev_kfree_skb(meta->skb); |
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meta->skb = NULL; |
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} |
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} |
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|
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static int alloc_ringmemory(struct b43legacy_dmaring *ring) |
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{ |
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/* GFP flags must match the flags in free_ringmemory()! */ |
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ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev, |
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B43legacy_DMA_RINGMEMSIZE, |
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&(ring->dmabase), GFP_KERNEL); |
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if (!ring->descbase) |
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return -ENOMEM; |
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|
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return 0; |
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} |
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static void free_ringmemory(struct b43legacy_dmaring *ring) |
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{ |
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dma_free_coherent(ring->dev->dev->dma_dev, B43legacy_DMA_RINGMEMSIZE, |
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ring->descbase, ring->dmabase); |
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} |
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|
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/* Reset the RX DMA channel */ |
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static int b43legacy_dmacontroller_rx_reset(struct b43legacy_wldev *dev, |
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u16 mmio_base, |
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enum b43legacy_dmatype type) |
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{ |
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int i; |
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u32 value; |
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u16 offset; |
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|
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might_sleep(); |
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offset = B43legacy_DMA32_RXCTL; |
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b43legacy_write32(dev, mmio_base + offset, 0); |
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for (i = 0; i < 10; i++) { |
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offset = B43legacy_DMA32_RXSTATUS; |
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value = b43legacy_read32(dev, mmio_base + offset); |
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value &= B43legacy_DMA32_RXSTATE; |
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if (value == B43legacy_DMA32_RXSTAT_DISABLED) { |
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i = -1; |
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break; |
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} |
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msleep(1); |
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} |
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if (i != -1) { |
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b43legacyerr(dev->wl, "DMA RX reset timed out\n"); |
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return -ENODEV; |
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} |
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|
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return 0; |
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} |
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|
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/* Reset the RX DMA channel */ |
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static int b43legacy_dmacontroller_tx_reset(struct b43legacy_wldev *dev, |
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u16 mmio_base, |
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enum b43legacy_dmatype type) |
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{ |
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int i; |
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u32 value; |
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u16 offset; |
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|
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might_sleep(); |
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|
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for (i = 0; i < 10; i++) { |
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offset = B43legacy_DMA32_TXSTATUS; |
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value = b43legacy_read32(dev, mmio_base + offset); |
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value &= B43legacy_DMA32_TXSTATE; |
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if (value == B43legacy_DMA32_TXSTAT_DISABLED || |
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value == B43legacy_DMA32_TXSTAT_IDLEWAIT || |
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value == B43legacy_DMA32_TXSTAT_STOPPED) |
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break; |
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msleep(1); |
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} |
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offset = B43legacy_DMA32_TXCTL; |
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b43legacy_write32(dev, mmio_base + offset, 0); |
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for (i = 0; i < 10; i++) { |
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offset = B43legacy_DMA32_TXSTATUS; |
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value = b43legacy_read32(dev, mmio_base + offset); |
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value &= B43legacy_DMA32_TXSTATE; |
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if (value == B43legacy_DMA32_TXSTAT_DISABLED) { |
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i = -1; |
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break; |
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} |
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msleep(1); |
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} |
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if (i != -1) { |
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b43legacyerr(dev->wl, "DMA TX reset timed out\n"); |
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return -ENODEV; |
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} |
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/* ensure the reset is completed. */ |
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msleep(1); |
|
|
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return 0; |
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} |
|
|
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/* Check if a DMA mapping address is invalid. */ |
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static bool b43legacy_dma_mapping_error(struct b43legacy_dmaring *ring, |
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dma_addr_t addr, |
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size_t buffersize, |
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bool dma_to_device) |
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{ |
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if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr))) |
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return true; |
|
|
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switch (ring->type) { |
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case B43legacy_DMA_30BIT: |
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if ((u64)addr + buffersize > (1ULL << 30)) |
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goto address_error; |
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break; |
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case B43legacy_DMA_32BIT: |
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if ((u64)addr + buffersize > (1ULL << 32)) |
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goto address_error; |
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break; |
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} |
|
|
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/* The address is OK. */ |
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return false; |
|
|
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address_error: |
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/* We can't support this address. Unmap it again. */ |
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unmap_descbuffer(ring, addr, buffersize, dma_to_device); |
|
|
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return true; |
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} |
|
|
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static int setup_rx_descbuffer(struct b43legacy_dmaring *ring, |
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struct b43legacy_dmadesc32 *desc, |
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struct b43legacy_dmadesc_meta *meta, |
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gfp_t gfp_flags) |
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{ |
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struct b43legacy_rxhdr_fw3 *rxhdr; |
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struct b43legacy_hwtxstatus *txstat; |
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dma_addr_t dmaaddr; |
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struct sk_buff *skb; |
|
|
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B43legacy_WARN_ON(ring->tx); |
|
|
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skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags); |
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if (unlikely(!skb)) |
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return -ENOMEM; |
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dmaaddr = map_descbuffer(ring, skb->data, |
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ring->rx_buffersize, 0); |
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if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) { |
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/* ugh. try to realloc in zone_dma */ |
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gfp_flags |= GFP_DMA; |
|
|
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dev_kfree_skb_any(skb); |
|
|
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skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags); |
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if (unlikely(!skb)) |
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return -ENOMEM; |
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dmaaddr = map_descbuffer(ring, skb->data, |
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ring->rx_buffersize, 0); |
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} |
|
|
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if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) { |
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dev_kfree_skb_any(skb); |
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return -EIO; |
|
} |
|
|
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meta->skb = skb; |
|
meta->dmaaddr = dmaaddr; |
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op32_fill_descriptor(ring, desc, dmaaddr, ring->rx_buffersize, 0, 0, 0); |
|
|
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rxhdr = (struct b43legacy_rxhdr_fw3 *)(skb->data); |
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rxhdr->frame_len = 0; |
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txstat = (struct b43legacy_hwtxstatus *)(skb->data); |
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txstat->cookie = 0; |
|
|
|
return 0; |
|
} |
|
|
|
/* Allocate the initial descbuffers. |
|
* This is used for an RX ring only. |
|
*/ |
|
static int alloc_initial_descbuffers(struct b43legacy_dmaring *ring) |
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{ |
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int i; |
|
int err = -ENOMEM; |
|
struct b43legacy_dmadesc32 *desc; |
|
struct b43legacy_dmadesc_meta *meta; |
|
|
|
for (i = 0; i < ring->nr_slots; i++) { |
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desc = op32_idx2desc(ring, i, &meta); |
|
|
|
err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL); |
|
if (err) { |
|
b43legacyerr(ring->dev->wl, |
|
"Failed to allocate initial descbuffers\n"); |
|
goto err_unwind; |
|
} |
|
} |
|
mb(); /* all descbuffer setup before next line */ |
|
ring->used_slots = ring->nr_slots; |
|
err = 0; |
|
out: |
|
return err; |
|
|
|
err_unwind: |
|
for (i--; i >= 0; i--) { |
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desc = op32_idx2desc(ring, i, &meta); |
|
|
|
unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0); |
|
dev_kfree_skb(meta->skb); |
|
} |
|
goto out; |
|
} |
|
|
|
/* Do initial setup of the DMA controller. |
|
* Reset the controller, write the ring busaddress |
|
* and switch the "enable" bit on. |
|
*/ |
|
static int dmacontroller_setup(struct b43legacy_dmaring *ring) |
|
{ |
|
int err = 0; |
|
u32 value; |
|
u32 addrext; |
|
u32 trans = ring->dev->dma.translation; |
|
u32 ringbase = (u32)(ring->dmabase); |
|
|
|
if (ring->tx) { |
|
addrext = (ringbase & SSB_DMA_TRANSLATION_MASK) |
|
>> SSB_DMA_TRANSLATION_SHIFT; |
|
value = B43legacy_DMA32_TXENABLE; |
|
value |= (addrext << B43legacy_DMA32_TXADDREXT_SHIFT) |
|
& B43legacy_DMA32_TXADDREXT_MASK; |
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b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL, value); |
|
b43legacy_dma_write(ring, B43legacy_DMA32_TXRING, |
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(ringbase & ~SSB_DMA_TRANSLATION_MASK) |
|
| trans); |
|
} else { |
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err = alloc_initial_descbuffers(ring); |
|
if (err) |
|
goto out; |
|
|
|
addrext = (ringbase & SSB_DMA_TRANSLATION_MASK) |
|
>> SSB_DMA_TRANSLATION_SHIFT; |
|
value = (ring->frameoffset << |
|
B43legacy_DMA32_RXFROFF_SHIFT); |
|
value |= B43legacy_DMA32_RXENABLE; |
|
value |= (addrext << B43legacy_DMA32_RXADDREXT_SHIFT) |
|
& B43legacy_DMA32_RXADDREXT_MASK; |
|
b43legacy_dma_write(ring, B43legacy_DMA32_RXCTL, value); |
|
b43legacy_dma_write(ring, B43legacy_DMA32_RXRING, |
|
(ringbase & ~SSB_DMA_TRANSLATION_MASK) |
|
| trans); |
|
b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX, 200); |
|
} |
|
|
|
out: |
|
return err; |
|
} |
|
|
|
/* Shutdown the DMA controller. */ |
|
static void dmacontroller_cleanup(struct b43legacy_dmaring *ring) |
|
{ |
|
if (ring->tx) { |
|
b43legacy_dmacontroller_tx_reset(ring->dev, ring->mmio_base, |
|
ring->type); |
|
b43legacy_dma_write(ring, B43legacy_DMA32_TXRING, 0); |
|
} else { |
|
b43legacy_dmacontroller_rx_reset(ring->dev, ring->mmio_base, |
|
ring->type); |
|
b43legacy_dma_write(ring, B43legacy_DMA32_RXRING, 0); |
|
} |
|
} |
|
|
|
static void free_all_descbuffers(struct b43legacy_dmaring *ring) |
|
{ |
|
struct b43legacy_dmadesc_meta *meta; |
|
int i; |
|
|
|
if (!ring->used_slots) |
|
return; |
|
for (i = 0; i < ring->nr_slots; i++) { |
|
op32_idx2desc(ring, i, &meta); |
|
|
|
if (!meta->skb) { |
|
B43legacy_WARN_ON(!ring->tx); |
|
continue; |
|
} |
|
if (ring->tx) |
|
unmap_descbuffer(ring, meta->dmaaddr, |
|
meta->skb->len, 1); |
|
else |
|
unmap_descbuffer(ring, meta->dmaaddr, |
|
ring->rx_buffersize, 0); |
|
free_descriptor_buffer(ring, meta, 0); |
|
} |
|
} |
|
|
|
static enum b43legacy_dmatype b43legacy_engine_type(struct b43legacy_wldev *dev) |
|
{ |
|
u32 tmp; |
|
u16 mmio_base; |
|
|
|
mmio_base = b43legacy_dmacontroller_base(0, 0); |
|
b43legacy_write32(dev, |
|
mmio_base + B43legacy_DMA32_TXCTL, |
|
B43legacy_DMA32_TXADDREXT_MASK); |
|
tmp = b43legacy_read32(dev, mmio_base + |
|
B43legacy_DMA32_TXCTL); |
|
if (tmp & B43legacy_DMA32_TXADDREXT_MASK) |
|
return B43legacy_DMA_32BIT; |
|
return B43legacy_DMA_30BIT; |
|
} |
|
|
|
/* Main initialization function. */ |
|
static |
|
struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev, |
|
int controller_index, |
|
int for_tx, |
|
enum b43legacy_dmatype type) |
|
{ |
|
struct b43legacy_dmaring *ring; |
|
int err; |
|
int nr_slots; |
|
dma_addr_t dma_test; |
|
|
|
ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
|
if (!ring) |
|
goto out; |
|
ring->type = type; |
|
ring->dev = dev; |
|
|
|
nr_slots = B43legacy_RXRING_SLOTS; |
|
if (for_tx) |
|
nr_slots = B43legacy_TXRING_SLOTS; |
|
|
|
ring->meta = kcalloc(nr_slots, sizeof(struct b43legacy_dmadesc_meta), |
|
GFP_KERNEL); |
|
if (!ring->meta) |
|
goto err_kfree_ring; |
|
if (for_tx) { |
|
ring->txhdr_cache = kcalloc(nr_slots, |
|
sizeof(struct b43legacy_txhdr_fw3), |
|
GFP_KERNEL); |
|
if (!ring->txhdr_cache) |
|
goto err_kfree_meta; |
|
|
|
/* test for ability to dma to txhdr_cache */ |
|
dma_test = dma_map_single(dev->dev->dma_dev, ring->txhdr_cache, |
|
sizeof(struct b43legacy_txhdr_fw3), |
|
DMA_TO_DEVICE); |
|
|
|
if (b43legacy_dma_mapping_error(ring, dma_test, |
|
sizeof(struct b43legacy_txhdr_fw3), 1)) { |
|
/* ugh realloc */ |
|
kfree(ring->txhdr_cache); |
|
ring->txhdr_cache = kcalloc(nr_slots, |
|
sizeof(struct b43legacy_txhdr_fw3), |
|
GFP_KERNEL | GFP_DMA); |
|
if (!ring->txhdr_cache) |
|
goto err_kfree_meta; |
|
|
|
dma_test = dma_map_single(dev->dev->dma_dev, |
|
ring->txhdr_cache, |
|
sizeof(struct b43legacy_txhdr_fw3), |
|
DMA_TO_DEVICE); |
|
|
|
if (b43legacy_dma_mapping_error(ring, dma_test, |
|
sizeof(struct b43legacy_txhdr_fw3), 1)) |
|
goto err_kfree_txhdr_cache; |
|
} |
|
|
|
dma_unmap_single(dev->dev->dma_dev, dma_test, |
|
sizeof(struct b43legacy_txhdr_fw3), |
|
DMA_TO_DEVICE); |
|
} |
|
|
|
ring->nr_slots = nr_slots; |
|
ring->mmio_base = b43legacy_dmacontroller_base(type, controller_index); |
|
ring->index = controller_index; |
|
if (for_tx) { |
|
ring->tx = true; |
|
ring->current_slot = -1; |
|
} else { |
|
if (ring->index == 0) { |
|
ring->rx_buffersize = B43legacy_DMA0_RX_BUFFERSIZE; |
|
ring->frameoffset = B43legacy_DMA0_RX_FRAMEOFFSET; |
|
} else if (ring->index == 3) { |
|
ring->rx_buffersize = B43legacy_DMA3_RX_BUFFERSIZE; |
|
ring->frameoffset = B43legacy_DMA3_RX_FRAMEOFFSET; |
|
} else |
|
B43legacy_WARN_ON(1); |
|
} |
|
#ifdef CONFIG_B43LEGACY_DEBUG |
|
ring->last_injected_overflow = jiffies; |
|
#endif |
|
|
|
err = alloc_ringmemory(ring); |
|
if (err) |
|
goto err_kfree_txhdr_cache; |
|
err = dmacontroller_setup(ring); |
|
if (err) |
|
goto err_free_ringmemory; |
|
|
|
out: |
|
return ring; |
|
|
|
err_free_ringmemory: |
|
free_ringmemory(ring); |
|
err_kfree_txhdr_cache: |
|
kfree(ring->txhdr_cache); |
|
err_kfree_meta: |
|
kfree(ring->meta); |
|
err_kfree_ring: |
|
kfree(ring); |
|
ring = NULL; |
|
goto out; |
|
} |
|
|
|
/* Main cleanup function. */ |
|
static void b43legacy_destroy_dmaring(struct b43legacy_dmaring *ring) |
|
{ |
|
if (!ring) |
|
return; |
|
|
|
b43legacydbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots:" |
|
" %d/%d\n", (unsigned int)(ring->type), ring->mmio_base, |
|
(ring->tx) ? "TX" : "RX", ring->max_used_slots, |
|
ring->nr_slots); |
|
/* Device IRQs are disabled prior entering this function, |
|
* so no need to take care of concurrency with rx handler stuff. |
|
*/ |
|
dmacontroller_cleanup(ring); |
|
free_all_descbuffers(ring); |
|
free_ringmemory(ring); |
|
|
|
kfree(ring->txhdr_cache); |
|
kfree(ring->meta); |
|
kfree(ring); |
|
} |
|
|
|
void b43legacy_dma_free(struct b43legacy_wldev *dev) |
|
{ |
|
struct b43legacy_dma *dma; |
|
|
|
if (b43legacy_using_pio(dev)) |
|
return; |
|
dma = &dev->dma; |
|
|
|
b43legacy_destroy_dmaring(dma->rx_ring3); |
|
dma->rx_ring3 = NULL; |
|
b43legacy_destroy_dmaring(dma->rx_ring0); |
|
dma->rx_ring0 = NULL; |
|
|
|
b43legacy_destroy_dmaring(dma->tx_ring5); |
|
dma->tx_ring5 = NULL; |
|
b43legacy_destroy_dmaring(dma->tx_ring4); |
|
dma->tx_ring4 = NULL; |
|
b43legacy_destroy_dmaring(dma->tx_ring3); |
|
dma->tx_ring3 = NULL; |
|
b43legacy_destroy_dmaring(dma->tx_ring2); |
|
dma->tx_ring2 = NULL; |
|
b43legacy_destroy_dmaring(dma->tx_ring1); |
|
dma->tx_ring1 = NULL; |
|
b43legacy_destroy_dmaring(dma->tx_ring0); |
|
dma->tx_ring0 = NULL; |
|
} |
|
|
|
int b43legacy_dma_init(struct b43legacy_wldev *dev) |
|
{ |
|
struct b43legacy_dma *dma = &dev->dma; |
|
struct b43legacy_dmaring *ring; |
|
enum b43legacy_dmatype type = b43legacy_engine_type(dev); |
|
int err; |
|
|
|
err = dma_set_mask_and_coherent(dev->dev->dma_dev, DMA_BIT_MASK(type)); |
|
if (err) { |
|
#ifdef CONFIG_B43LEGACY_PIO |
|
b43legacywarn(dev->wl, "DMA for this device not supported. " |
|
"Falling back to PIO\n"); |
|
dev->__using_pio = true; |
|
return -EAGAIN; |
|
#else |
|
b43legacyerr(dev->wl, "DMA for this device not supported and " |
|
"no PIO support compiled in\n"); |
|
return -EOPNOTSUPP; |
|
#endif |
|
} |
|
dma->translation = ssb_dma_translation(dev->dev); |
|
|
|
err = -ENOMEM; |
|
/* setup TX DMA channels. */ |
|
ring = b43legacy_setup_dmaring(dev, 0, 1, type); |
|
if (!ring) |
|
goto out; |
|
dma->tx_ring0 = ring; |
|
|
|
ring = b43legacy_setup_dmaring(dev, 1, 1, type); |
|
if (!ring) |
|
goto err_destroy_tx0; |
|
dma->tx_ring1 = ring; |
|
|
|
ring = b43legacy_setup_dmaring(dev, 2, 1, type); |
|
if (!ring) |
|
goto err_destroy_tx1; |
|
dma->tx_ring2 = ring; |
|
|
|
ring = b43legacy_setup_dmaring(dev, 3, 1, type); |
|
if (!ring) |
|
goto err_destroy_tx2; |
|
dma->tx_ring3 = ring; |
|
|
|
ring = b43legacy_setup_dmaring(dev, 4, 1, type); |
|
if (!ring) |
|
goto err_destroy_tx3; |
|
dma->tx_ring4 = ring; |
|
|
|
ring = b43legacy_setup_dmaring(dev, 5, 1, type); |
|
if (!ring) |
|
goto err_destroy_tx4; |
|
dma->tx_ring5 = ring; |
|
|
|
/* setup RX DMA channels. */ |
|
ring = b43legacy_setup_dmaring(dev, 0, 0, type); |
|
if (!ring) |
|
goto err_destroy_tx5; |
|
dma->rx_ring0 = ring; |
|
|
|
if (dev->dev->id.revision < 5) { |
|
ring = b43legacy_setup_dmaring(dev, 3, 0, type); |
|
if (!ring) |
|
goto err_destroy_rx0; |
|
dma->rx_ring3 = ring; |
|
} |
|
|
|
b43legacydbg(dev->wl, "%u-bit DMA initialized\n", (unsigned int)type); |
|
err = 0; |
|
out: |
|
return err; |
|
|
|
err_destroy_rx0: |
|
b43legacy_destroy_dmaring(dma->rx_ring0); |
|
dma->rx_ring0 = NULL; |
|
err_destroy_tx5: |
|
b43legacy_destroy_dmaring(dma->tx_ring5); |
|
dma->tx_ring5 = NULL; |
|
err_destroy_tx4: |
|
b43legacy_destroy_dmaring(dma->tx_ring4); |
|
dma->tx_ring4 = NULL; |
|
err_destroy_tx3: |
|
b43legacy_destroy_dmaring(dma->tx_ring3); |
|
dma->tx_ring3 = NULL; |
|
err_destroy_tx2: |
|
b43legacy_destroy_dmaring(dma->tx_ring2); |
|
dma->tx_ring2 = NULL; |
|
err_destroy_tx1: |
|
b43legacy_destroy_dmaring(dma->tx_ring1); |
|
dma->tx_ring1 = NULL; |
|
err_destroy_tx0: |
|
b43legacy_destroy_dmaring(dma->tx_ring0); |
|
dma->tx_ring0 = NULL; |
|
goto out; |
|
} |
|
|
|
/* Generate a cookie for the TX header. */ |
|
static u16 generate_cookie(struct b43legacy_dmaring *ring, |
|
int slot) |
|
{ |
|
u16 cookie = 0x1000; |
|
|
|
/* Use the upper 4 bits of the cookie as |
|
* DMA controller ID and store the slot number |
|
* in the lower 12 bits. |
|
* Note that the cookie must never be 0, as this |
|
* is a special value used in RX path. |
|
*/ |
|
switch (ring->index) { |
|
case 0: |
|
cookie = 0xA000; |
|
break; |
|
case 1: |
|
cookie = 0xB000; |
|
break; |
|
case 2: |
|
cookie = 0xC000; |
|
break; |
|
case 3: |
|
cookie = 0xD000; |
|
break; |
|
case 4: |
|
cookie = 0xE000; |
|
break; |
|
case 5: |
|
cookie = 0xF000; |
|
break; |
|
} |
|
B43legacy_WARN_ON(!(((u16)slot & 0xF000) == 0x0000)); |
|
cookie |= (u16)slot; |
|
|
|
return cookie; |
|
} |
|
|
|
/* Inspect a cookie and find out to which controller/slot it belongs. */ |
|
static |
|
struct b43legacy_dmaring *parse_cookie(struct b43legacy_wldev *dev, |
|
u16 cookie, int *slot) |
|
{ |
|
struct b43legacy_dma *dma = &dev->dma; |
|
struct b43legacy_dmaring *ring = NULL; |
|
|
|
switch (cookie & 0xF000) { |
|
case 0xA000: |
|
ring = dma->tx_ring0; |
|
break; |
|
case 0xB000: |
|
ring = dma->tx_ring1; |
|
break; |
|
case 0xC000: |
|
ring = dma->tx_ring2; |
|
break; |
|
case 0xD000: |
|
ring = dma->tx_ring3; |
|
break; |
|
case 0xE000: |
|
ring = dma->tx_ring4; |
|
break; |
|
case 0xF000: |
|
ring = dma->tx_ring5; |
|
break; |
|
default: |
|
B43legacy_WARN_ON(1); |
|
} |
|
*slot = (cookie & 0x0FFF); |
|
B43legacy_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots)); |
|
|
|
return ring; |
|
} |
|
|
|
static int dma_tx_fragment(struct b43legacy_dmaring *ring, |
|
struct sk_buff **in_skb) |
|
{ |
|
struct sk_buff *skb = *in_skb; |
|
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
|
u8 *header; |
|
int slot, old_top_slot, old_used_slots; |
|
int err; |
|
struct b43legacy_dmadesc32 *desc; |
|
struct b43legacy_dmadesc_meta *meta; |
|
struct b43legacy_dmadesc_meta *meta_hdr; |
|
struct sk_buff *bounce_skb; |
|
|
|
#define SLOTS_PER_PACKET 2 |
|
B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags != 0); |
|
|
|
old_top_slot = ring->current_slot; |
|
old_used_slots = ring->used_slots; |
|
|
|
/* Get a slot for the header. */ |
|
slot = request_slot(ring); |
|
desc = op32_idx2desc(ring, slot, &meta_hdr); |
|
memset(meta_hdr, 0, sizeof(*meta_hdr)); |
|
|
|
header = &(ring->txhdr_cache[slot * sizeof( |
|
struct b43legacy_txhdr_fw3)]); |
|
err = b43legacy_generate_txhdr(ring->dev, header, |
|
skb->data, skb->len, info, |
|
generate_cookie(ring, slot)); |
|
if (unlikely(err)) { |
|
ring->current_slot = old_top_slot; |
|
ring->used_slots = old_used_slots; |
|
return err; |
|
} |
|
|
|
meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header, |
|
sizeof(struct b43legacy_txhdr_fw3), 1); |
|
if (b43legacy_dma_mapping_error(ring, meta_hdr->dmaaddr, |
|
sizeof(struct b43legacy_txhdr_fw3), 1)) { |
|
ring->current_slot = old_top_slot; |
|
ring->used_slots = old_used_slots; |
|
return -EIO; |
|
} |
|
op32_fill_descriptor(ring, desc, meta_hdr->dmaaddr, |
|
sizeof(struct b43legacy_txhdr_fw3), 1, 0, 0); |
|
|
|
/* Get a slot for the payload. */ |
|
slot = request_slot(ring); |
|
desc = op32_idx2desc(ring, slot, &meta); |
|
memset(meta, 0, sizeof(*meta)); |
|
|
|
meta->skb = skb; |
|
meta->is_last_fragment = true; |
|
|
|
meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1); |
|
/* create a bounce buffer in zone_dma on mapping failure. */ |
|
if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) { |
|
bounce_skb = alloc_skb(skb->len, GFP_KERNEL | GFP_DMA); |
|
if (!bounce_skb) { |
|
ring->current_slot = old_top_slot; |
|
ring->used_slots = old_used_slots; |
|
err = -ENOMEM; |
|
goto out_unmap_hdr; |
|
} |
|
|
|
skb_put_data(bounce_skb, skb->data, skb->len); |
|
memcpy(bounce_skb->cb, skb->cb, sizeof(skb->cb)); |
|
bounce_skb->dev = skb->dev; |
|
skb_set_queue_mapping(bounce_skb, skb_get_queue_mapping(skb)); |
|
info = IEEE80211_SKB_CB(bounce_skb); |
|
|
|
dev_kfree_skb_any(skb); |
|
skb = bounce_skb; |
|
*in_skb = bounce_skb; |
|
meta->skb = skb; |
|
meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1); |
|
if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) { |
|
ring->current_slot = old_top_slot; |
|
ring->used_slots = old_used_slots; |
|
err = -EIO; |
|
goto out_free_bounce; |
|
} |
|
} |
|
|
|
op32_fill_descriptor(ring, desc, meta->dmaaddr, |
|
skb->len, 0, 1, 1); |
|
|
|
wmb(); /* previous stuff MUST be done */ |
|
/* Now transfer the whole frame. */ |
|
op32_poke_tx(ring, next_slot(ring, slot)); |
|
return 0; |
|
|
|
out_free_bounce: |
|
dev_kfree_skb_any(skb); |
|
out_unmap_hdr: |
|
unmap_descbuffer(ring, meta_hdr->dmaaddr, |
|
sizeof(struct b43legacy_txhdr_fw3), 1); |
|
return err; |
|
} |
|
|
|
static inline |
|
int should_inject_overflow(struct b43legacy_dmaring *ring) |
|
{ |
|
#ifdef CONFIG_B43LEGACY_DEBUG |
|
if (unlikely(b43legacy_debug(ring->dev, |
|
B43legacy_DBG_DMAOVERFLOW))) { |
|
/* Check if we should inject another ringbuffer overflow |
|
* to test handling of this situation in the stack. */ |
|
unsigned long next_overflow; |
|
|
|
next_overflow = ring->last_injected_overflow + HZ; |
|
if (time_after(jiffies, next_overflow)) { |
|
ring->last_injected_overflow = jiffies; |
|
b43legacydbg(ring->dev->wl, |
|
"Injecting TX ring overflow on " |
|
"DMA controller %d\n", ring->index); |
|
return 1; |
|
} |
|
} |
|
#endif /* CONFIG_B43LEGACY_DEBUG */ |
|
return 0; |
|
} |
|
|
|
int b43legacy_dma_tx(struct b43legacy_wldev *dev, |
|
struct sk_buff *skb) |
|
{ |
|
struct b43legacy_dmaring *ring; |
|
int err = 0; |
|
|
|
ring = priority_to_txring(dev, skb_get_queue_mapping(skb)); |
|
B43legacy_WARN_ON(!ring->tx); |
|
|
|
if (unlikely(ring->stopped)) { |
|
/* We get here only because of a bug in mac80211. |
|
* Because of a race, one packet may be queued after |
|
* the queue is stopped, thus we got called when we shouldn't. |
|
* For now, just refuse the transmit. */ |
|
if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE)) |
|
b43legacyerr(dev->wl, "Packet after queue stopped\n"); |
|
return -ENOSPC; |
|
} |
|
|
|
if (WARN_ON(free_slots(ring) < SLOTS_PER_PACKET)) { |
|
/* If we get here, we have a real error with the queue |
|
* full, but queues not stopped. */ |
|
b43legacyerr(dev->wl, "DMA queue overflow\n"); |
|
return -ENOSPC; |
|
} |
|
|
|
/* dma_tx_fragment might reallocate the skb, so invalidate pointers pointing |
|
* into the skb data or cb now. */ |
|
err = dma_tx_fragment(ring, &skb); |
|
if (unlikely(err == -ENOKEY)) { |
|
/* Drop this packet, as we don't have the encryption key |
|
* anymore and must not transmit it unencrypted. */ |
|
dev_kfree_skb_any(skb); |
|
return 0; |
|
} |
|
if (unlikely(err)) { |
|
b43legacyerr(dev->wl, "DMA tx mapping failure\n"); |
|
return err; |
|
} |
|
if ((free_slots(ring) < SLOTS_PER_PACKET) || |
|
should_inject_overflow(ring)) { |
|
/* This TX ring is full. */ |
|
unsigned int skb_mapping = skb_get_queue_mapping(skb); |
|
ieee80211_stop_queue(dev->wl->hw, skb_mapping); |
|
dev->wl->tx_queue_stopped[skb_mapping] = 1; |
|
ring->stopped = true; |
|
if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE)) |
|
b43legacydbg(dev->wl, "Stopped TX ring %d\n", |
|
ring->index); |
|
} |
|
return err; |
|
} |
|
|
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void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev, |
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const struct b43legacy_txstatus *status) |
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{ |
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struct b43legacy_dmaring *ring; |
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struct b43legacy_dmadesc_meta *meta; |
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int retry_limit; |
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int slot; |
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int firstused; |
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|
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ring = parse_cookie(dev, status->cookie, &slot); |
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if (unlikely(!ring)) |
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return; |
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B43legacy_WARN_ON(!ring->tx); |
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|
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/* Sanity check: TX packets are processed in-order on one ring. |
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* Check if the slot deduced from the cookie really is the first |
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* used slot. */ |
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firstused = ring->current_slot - ring->used_slots + 1; |
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if (firstused < 0) |
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firstused = ring->nr_slots + firstused; |
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if (unlikely(slot != firstused)) { |
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/* This possibly is a firmware bug and will result in |
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* malfunction, memory leaks and/or stall of DMA functionality. |
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*/ |
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b43legacydbg(dev->wl, "Out of order TX status report on DMA " |
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"ring %d. Expected %d, but got %d\n", |
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ring->index, firstused, slot); |
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return; |
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} |
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|
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while (1) { |
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B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); |
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op32_idx2desc(ring, slot, &meta); |
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|
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if (meta->skb) |
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unmap_descbuffer(ring, meta->dmaaddr, |
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meta->skb->len, 1); |
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else |
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unmap_descbuffer(ring, meta->dmaaddr, |
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sizeof(struct b43legacy_txhdr_fw3), |
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1); |
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|
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if (meta->is_last_fragment) { |
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struct ieee80211_tx_info *info; |
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BUG_ON(!meta->skb); |
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info = IEEE80211_SKB_CB(meta->skb); |
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|
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/* preserve the confiured retry limit before clearing the status |
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* The xmit function has overwritten the rc's value with the actual |
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* retry limit done by the hardware */ |
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retry_limit = info->status.rates[0].count; |
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ieee80211_tx_info_clear_status(info); |
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|
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if (status->acked) |
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info->flags |= IEEE80211_TX_STAT_ACK; |
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|
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if (status->rts_count > dev->wl->hw->conf.short_frame_max_tx_count) { |
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/* |
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* If the short retries (RTS, not data frame) have exceeded |
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* the limit, the hw will not have tried the selected rate, |
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* but will have used the fallback rate instead. |
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* Don't let the rate control count attempts for the selected |
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* rate in this case, otherwise the statistics will be off. |
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*/ |
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info->status.rates[0].count = 0; |
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info->status.rates[1].count = status->frame_count; |
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} else { |
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if (status->frame_count > retry_limit) { |
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info->status.rates[0].count = retry_limit; |
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info->status.rates[1].count = status->frame_count - |
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retry_limit; |
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|
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} else { |
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info->status.rates[0].count = status->frame_count; |
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info->status.rates[1].idx = -1; |
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} |
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} |
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|
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/* Call back to inform the ieee80211 subsystem about the |
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* status of the transmission. |
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* Some fields of txstat are already filled in dma_tx(). |
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*/ |
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ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb); |
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/* skb is freed by ieee80211_tx_status_irqsafe() */ |
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meta->skb = NULL; |
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} else { |
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/* No need to call free_descriptor_buffer here, as |
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* this is only the txhdr, which is not allocated. |
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*/ |
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B43legacy_WARN_ON(meta->skb != NULL); |
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} |
|
|
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/* Everything unmapped and free'd. So it's not used anymore. */ |
|
ring->used_slots--; |
|
|
|
if (meta->is_last_fragment) |
|
break; |
|
slot = next_slot(ring, slot); |
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} |
|
dev->stats.last_tx = jiffies; |
|
if (ring->stopped) { |
|
B43legacy_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET); |
|
ring->stopped = false; |
|
} |
|
|
|
if (dev->wl->tx_queue_stopped[ring->queue_prio]) { |
|
dev->wl->tx_queue_stopped[ring->queue_prio] = 0; |
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} else { |
|
/* If the driver queue is running wake the corresponding |
|
* mac80211 queue. */ |
|
ieee80211_wake_queue(dev->wl->hw, ring->queue_prio); |
|
if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE)) |
|
b43legacydbg(dev->wl, "Woke up TX ring %d\n", |
|
ring->index); |
|
} |
|
/* Add work to the queue. */ |
|
ieee80211_queue_work(dev->wl->hw, &dev->wl->tx_work); |
|
} |
|
|
|
static void dma_rx(struct b43legacy_dmaring *ring, |
|
int *slot) |
|
{ |
|
struct b43legacy_dmadesc32 *desc; |
|
struct b43legacy_dmadesc_meta *meta; |
|
struct b43legacy_rxhdr_fw3 *rxhdr; |
|
struct sk_buff *skb; |
|
u16 len; |
|
int err; |
|
dma_addr_t dmaaddr; |
|
|
|
desc = op32_idx2desc(ring, *slot, &meta); |
|
|
|
sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize); |
|
skb = meta->skb; |
|
|
|
if (ring->index == 3) { |
|
/* We received an xmit status. */ |
|
struct b43legacy_hwtxstatus *hw = |
|
(struct b43legacy_hwtxstatus *)skb->data; |
|
int i = 0; |
|
|
|
while (hw->cookie == 0) { |
|
if (i > 100) |
|
break; |
|
i++; |
|
udelay(2); |
|
barrier(); |
|
} |
|
b43legacy_handle_hwtxstatus(ring->dev, hw); |
|
/* recycle the descriptor buffer. */ |
|
sync_descbuffer_for_device(ring, meta->dmaaddr, |
|
ring->rx_buffersize); |
|
|
|
return; |
|
} |
|
rxhdr = (struct b43legacy_rxhdr_fw3 *)skb->data; |
|
len = le16_to_cpu(rxhdr->frame_len); |
|
if (len == 0) { |
|
int i = 0; |
|
|
|
do { |
|
udelay(2); |
|
barrier(); |
|
len = le16_to_cpu(rxhdr->frame_len); |
|
} while (len == 0 && i++ < 5); |
|
if (unlikely(len == 0)) { |
|
/* recycle the descriptor buffer. */ |
|
sync_descbuffer_for_device(ring, meta->dmaaddr, |
|
ring->rx_buffersize); |
|
goto drop; |
|
} |
|
} |
|
if (unlikely(len > ring->rx_buffersize)) { |
|
/* The data did not fit into one descriptor buffer |
|
* and is split over multiple buffers. |
|
* This should never happen, as we try to allocate buffers |
|
* big enough. So simply ignore this packet. |
|
*/ |
|
int cnt = 0; |
|
s32 tmp = len; |
|
|
|
while (1) { |
|
desc = op32_idx2desc(ring, *slot, &meta); |
|
/* recycle the descriptor buffer. */ |
|
sync_descbuffer_for_device(ring, meta->dmaaddr, |
|
ring->rx_buffersize); |
|
*slot = next_slot(ring, *slot); |
|
cnt++; |
|
tmp -= ring->rx_buffersize; |
|
if (tmp <= 0) |
|
break; |
|
} |
|
b43legacyerr(ring->dev->wl, "DMA RX buffer too small " |
|
"(len: %u, buffer: %u, nr-dropped: %d)\n", |
|
len, ring->rx_buffersize, cnt); |
|
goto drop; |
|
} |
|
|
|
dmaaddr = meta->dmaaddr; |
|
err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC); |
|
if (unlikely(err)) { |
|
b43legacydbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer()" |
|
" failed\n"); |
|
sync_descbuffer_for_device(ring, dmaaddr, |
|
ring->rx_buffersize); |
|
goto drop; |
|
} |
|
|
|
unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0); |
|
skb_put(skb, len + ring->frameoffset); |
|
skb_pull(skb, ring->frameoffset); |
|
|
|
b43legacy_rx(ring->dev, skb, rxhdr); |
|
drop: |
|
return; |
|
} |
|
|
|
void b43legacy_dma_rx(struct b43legacy_dmaring *ring) |
|
{ |
|
int slot; |
|
int current_slot; |
|
int used_slots = 0; |
|
|
|
B43legacy_WARN_ON(ring->tx); |
|
current_slot = op32_get_current_rxslot(ring); |
|
B43legacy_WARN_ON(!(current_slot >= 0 && current_slot < |
|
ring->nr_slots)); |
|
|
|
slot = ring->current_slot; |
|
for (; slot != current_slot; slot = next_slot(ring, slot)) { |
|
dma_rx(ring, &slot); |
|
update_max_used_slots(ring, ++used_slots); |
|
} |
|
op32_set_current_rxslot(ring, slot); |
|
ring->current_slot = slot; |
|
} |
|
|
|
static void b43legacy_dma_tx_suspend_ring(struct b43legacy_dmaring *ring) |
|
{ |
|
B43legacy_WARN_ON(!ring->tx); |
|
op32_tx_suspend(ring); |
|
} |
|
|
|
static void b43legacy_dma_tx_resume_ring(struct b43legacy_dmaring *ring) |
|
{ |
|
B43legacy_WARN_ON(!ring->tx); |
|
op32_tx_resume(ring); |
|
} |
|
|
|
void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev) |
|
{ |
|
b43legacy_power_saving_ctl_bits(dev, -1, 1); |
|
b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring0); |
|
b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring1); |
|
b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring2); |
|
b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring3); |
|
b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring4); |
|
b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring5); |
|
} |
|
|
|
void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev) |
|
{ |
|
b43legacy_dma_tx_resume_ring(dev->dma.tx_ring5); |
|
b43legacy_dma_tx_resume_ring(dev->dma.tx_ring4); |
|
b43legacy_dma_tx_resume_ring(dev->dma.tx_ring3); |
|
b43legacy_dma_tx_resume_ring(dev->dma.tx_ring2); |
|
b43legacy_dma_tx_resume_ring(dev->dma.tx_ring1); |
|
b43legacy_dma_tx_resume_ring(dev->dma.tx_ring0); |
|
b43legacy_power_saving_ctl_bits(dev, -1, -1); |
|
}
|
|
|