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859 lines
27 KiB
859 lines
27 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef B43legacy_H_ |
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#define B43legacy_H_ |
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#include <linux/hw_random.h> |
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#include <linux/kernel.h> |
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#include <linux/spinlock.h> |
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#include <linux/interrupt.h> |
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#include <linux/stringify.h> |
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#include <linux/netdevice.h> |
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#include <linux/pci.h> |
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#include <linux/atomic.h> |
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#include <linux/io.h> |
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#include <linux/ssb/ssb.h> |
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#include <linux/ssb/ssb_driver_chipcommon.h> |
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#include <linux/completion.h> |
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#include <net/mac80211.h> |
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#include "debugfs.h" |
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#include "leds.h" |
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#include "rfkill.h" |
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#include "phy.h" |
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#define B43legacy_IRQWAIT_MAX_RETRIES 20 |
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/* MMIO offsets */ |
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#define B43legacy_MMIO_DMA0_REASON 0x20 |
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#define B43legacy_MMIO_DMA0_IRQ_MASK 0x24 |
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#define B43legacy_MMIO_DMA1_REASON 0x28 |
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#define B43legacy_MMIO_DMA1_IRQ_MASK 0x2C |
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#define B43legacy_MMIO_DMA2_REASON 0x30 |
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#define B43legacy_MMIO_DMA2_IRQ_MASK 0x34 |
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#define B43legacy_MMIO_DMA3_REASON 0x38 |
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#define B43legacy_MMIO_DMA3_IRQ_MASK 0x3C |
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#define B43legacy_MMIO_DMA4_REASON 0x40 |
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#define B43legacy_MMIO_DMA4_IRQ_MASK 0x44 |
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#define B43legacy_MMIO_DMA5_REASON 0x48 |
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#define B43legacy_MMIO_DMA5_IRQ_MASK 0x4C |
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#define B43legacy_MMIO_MACCTL 0x120 /* MAC control */ |
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#define B43legacy_MMIO_MACCMD 0x124 /* MAC command */ |
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#define B43legacy_MMIO_GEN_IRQ_REASON 0x128 |
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#define B43legacy_MMIO_GEN_IRQ_MASK 0x12C |
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#define B43legacy_MMIO_RAM_CONTROL 0x130 |
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#define B43legacy_MMIO_RAM_DATA 0x134 |
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#define B43legacy_MMIO_PS_STATUS 0x140 |
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#define B43legacy_MMIO_RADIO_HWENABLED_HI 0x158 |
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#define B43legacy_MMIO_SHM_CONTROL 0x160 |
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#define B43legacy_MMIO_SHM_DATA 0x164 |
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#define B43legacy_MMIO_SHM_DATA_UNALIGNED 0x166 |
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#define B43legacy_MMIO_XMITSTAT_0 0x170 |
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#define B43legacy_MMIO_XMITSTAT_1 0x174 |
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#define B43legacy_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */ |
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#define B43legacy_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */ |
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#define B43legacy_MMIO_TSF_CFP_REP 0x188 |
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#define B43legacy_MMIO_TSF_CFP_START 0x18C |
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/* 32-bit DMA */ |
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#define B43legacy_MMIO_DMA32_BASE0 0x200 |
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#define B43legacy_MMIO_DMA32_BASE1 0x220 |
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#define B43legacy_MMIO_DMA32_BASE2 0x240 |
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#define B43legacy_MMIO_DMA32_BASE3 0x260 |
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#define B43legacy_MMIO_DMA32_BASE4 0x280 |
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#define B43legacy_MMIO_DMA32_BASE5 0x2A0 |
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/* 64-bit DMA */ |
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#define B43legacy_MMIO_DMA64_BASE0 0x200 |
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#define B43legacy_MMIO_DMA64_BASE1 0x240 |
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#define B43legacy_MMIO_DMA64_BASE2 0x280 |
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#define B43legacy_MMIO_DMA64_BASE3 0x2C0 |
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#define B43legacy_MMIO_DMA64_BASE4 0x300 |
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#define B43legacy_MMIO_DMA64_BASE5 0x340 |
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/* PIO */ |
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#define B43legacy_MMIO_PIO1_BASE 0x300 |
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#define B43legacy_MMIO_PIO2_BASE 0x310 |
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#define B43legacy_MMIO_PIO3_BASE 0x320 |
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#define B43legacy_MMIO_PIO4_BASE 0x330 |
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#define B43legacy_MMIO_PHY_VER 0x3E0 |
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#define B43legacy_MMIO_PHY_RADIO 0x3E2 |
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#define B43legacy_MMIO_PHY0 0x3E6 |
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#define B43legacy_MMIO_ANTENNA 0x3E8 |
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#define B43legacy_MMIO_CHANNEL 0x3F0 |
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#define B43legacy_MMIO_CHANNEL_EXT 0x3F4 |
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#define B43legacy_MMIO_RADIO_CONTROL 0x3F6 |
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#define B43legacy_MMIO_RADIO_DATA_HIGH 0x3F8 |
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#define B43legacy_MMIO_RADIO_DATA_LOW 0x3FA |
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#define B43legacy_MMIO_PHY_CONTROL 0x3FC |
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#define B43legacy_MMIO_PHY_DATA 0x3FE |
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#define B43legacy_MMIO_MACFILTER_CONTROL 0x420 |
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#define B43legacy_MMIO_MACFILTER_DATA 0x422 |
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#define B43legacy_MMIO_RCMTA_COUNT 0x43C /* Receive Match Transmitter Addr */ |
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#define B43legacy_MMIO_RADIO_HWENABLED_LO 0x49A |
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#define B43legacy_MMIO_GPIO_CONTROL 0x49C |
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#define B43legacy_MMIO_GPIO_MASK 0x49E |
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#define B43legacy_MMIO_TSF_CFP_PRETBTT 0x612 |
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#define B43legacy_MMIO_TSF_0 0x632 /* core rev < 3 only */ |
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#define B43legacy_MMIO_TSF_1 0x634 /* core rev < 3 only */ |
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#define B43legacy_MMIO_TSF_2 0x636 /* core rev < 3 only */ |
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#define B43legacy_MMIO_TSF_3 0x638 /* core rev < 3 only */ |
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#define B43legacy_MMIO_RNG 0x65A |
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#define B43legacy_MMIO_POWERUP_DELAY 0x6A8 |
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/* SPROM boardflags_lo values */ |
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#define B43legacy_BFL_PACTRL 0x0002 |
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#define B43legacy_BFL_RSSI 0x0008 |
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#define B43legacy_BFL_EXTLNA 0x1000 |
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/* GPIO register offset, in both ChipCommon and PCI core. */ |
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#define B43legacy_GPIO_CONTROL 0x6c |
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/* SHM Routing */ |
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#define B43legacy_SHM_SHARED 0x0001 |
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#define B43legacy_SHM_WIRELESS 0x0002 |
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#define B43legacy_SHM_HW 0x0004 |
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#define B43legacy_SHM_UCODE 0x0300 |
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/* SHM Routing modifiers */ |
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#define B43legacy_SHM_AUTOINC_R 0x0200 /* Read Auto-increment */ |
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#define B43legacy_SHM_AUTOINC_W 0x0100 /* Write Auto-increment */ |
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#define B43legacy_SHM_AUTOINC_RW (B43legacy_SHM_AUTOINC_R | \ |
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B43legacy_SHM_AUTOINC_W) |
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/* Misc SHM_SHARED offsets */ |
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#define B43legacy_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */ |
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#define B43legacy_SHM_SH_HOSTFLO 0x005E /* Hostflags ucode opts (low) */ |
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#define B43legacy_SHM_SH_HOSTFHI 0x0060 /* Hostflags ucode opts (high) */ |
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/* SHM_SHARED crypto engine */ |
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#define B43legacy_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block */ |
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/* SHM_SHARED beacon/AP variables */ |
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#define B43legacy_SHM_SH_DTIMP 0x0012 /* DTIM period */ |
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#define B43legacy_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */ |
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#define B43legacy_SHM_SH_BTL1 0x001A /* Beacon template length 1 */ |
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#define B43legacy_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */ |
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#define B43legacy_SHM_SH_TIMPOS 0x001E /* TIM position in beacon */ |
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#define B43legacy_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word */ |
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/* SHM_SHARED ACK/CTS control */ |
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#define B43legacy_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word */ |
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/* SHM_SHARED probe response variables */ |
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#define B43legacy_SHM_SH_PRTLEN 0x004A /* Probe Response template length */ |
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#define B43legacy_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */ |
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#define B43legacy_SHM_SH_PRPHYCTL 0x0188 /* Probe Resp PHY TX control */ |
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/* SHM_SHARED rate tables */ |
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#define B43legacy_SHM_SH_OFDMDIRECT 0x0480 /* Pointer to OFDM direct map */ |
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#define B43legacy_SHM_SH_OFDMBASIC 0x04A0 /* Pointer to OFDM basic rate map */ |
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#define B43legacy_SHM_SH_CCKDIRECT 0x04C0 /* Pointer to CCK direct map */ |
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#define B43legacy_SHM_SH_CCKBASIC 0x04E0 /* Pointer to CCK basic rate map */ |
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/* SHM_SHARED microcode soft registers */ |
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#define B43legacy_SHM_SH_UCODEREV 0x0000 /* Microcode revision */ |
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#define B43legacy_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */ |
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#define B43legacy_SHM_SH_UCODEDATE 0x0004 /* Microcode date */ |
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#define B43legacy_SHM_SH_UCODETIME 0x0006 /* Microcode time */ |
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#define B43legacy_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */ |
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#define B43legacy_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */ |
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#define B43legacy_UCODEFLAGS_OFFSET 0x005E |
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/* Hardware Radio Enable masks */ |
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#define B43legacy_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16) |
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#define B43legacy_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4) |
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/* HostFlags. See b43legacy_hf_read/write() */ |
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#define B43legacy_HF_SYMW 0x00000002 /* G-PHY SYM workaround */ |
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#define B43legacy_HF_GDCW 0x00000020 /* G-PHY DV cancel filter */ |
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#define B43legacy_HF_OFDMPABOOST 0x00000040 /* Enable PA boost OFDM */ |
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#define B43legacy_HF_EDCF 0x00000100 /* on if WME/MAC suspended */ |
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/* MacFilter offsets. */ |
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#define B43legacy_MACFILTER_SELF 0x0000 |
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#define B43legacy_MACFILTER_BSSID 0x0003 |
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#define B43legacy_MACFILTER_MAC 0x0010 |
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/* PHYVersioning */ |
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#define B43legacy_PHYTYPE_B 0x01 |
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#define B43legacy_PHYTYPE_G 0x02 |
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/* PHYRegisters */ |
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#define B43legacy_PHY_G_LO_CONTROL 0x0810 |
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#define B43legacy_PHY_ILT_G_CTRL 0x0472 |
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#define B43legacy_PHY_ILT_G_DATA1 0x0473 |
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#define B43legacy_PHY_ILT_G_DATA2 0x0474 |
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#define B43legacy_PHY_G_PCTL 0x0029 |
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#define B43legacy_PHY_RADIO_BITFIELD 0x0401 |
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#define B43legacy_PHY_G_CRS 0x0429 |
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#define B43legacy_PHY_NRSSILT_CTRL 0x0803 |
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#define B43legacy_PHY_NRSSILT_DATA 0x0804 |
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/* RadioRegisters */ |
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#define B43legacy_RADIOCTL_ID 0x01 |
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/* MAC Control bitfield */ |
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#define B43legacy_MACCTL_ENABLED 0x00000001 /* MAC Enabled */ |
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#define B43legacy_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */ |
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#define B43legacy_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */ |
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#define B43legacy_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */ |
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#define B43legacy_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */ |
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#define B43legacy_MACCTL_BE 0x00010000 /* Big Endian mode */ |
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#define B43legacy_MACCTL_INFRA 0x00020000 /* Infrastructure mode */ |
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#define B43legacy_MACCTL_AP 0x00040000 /* AccessPoint mode */ |
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#define B43legacy_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */ |
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#define B43legacy_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */ |
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#define B43legacy_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep bad PLCP frames */ |
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#define B43legacy_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */ |
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#define B43legacy_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */ |
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#define B43legacy_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */ |
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#define B43legacy_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */ |
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#define B43legacy_MACCTL_AWAKE 0x04000000 /* Device is awake */ |
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#define B43legacy_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */ |
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#define B43legacy_MACCTL_GMODE 0x80000000 /* G Mode */ |
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/* MAC Command bitfield */ |
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#define B43legacy_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */ |
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#define B43legacy_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */ |
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#define B43legacy_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */ |
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#define B43legacy_MACCMD_CCA 0x00000008 /* Clear channel assessment */ |
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#define B43legacy_MACCMD_BGNOISE 0x00000010 /* Background noise */ |
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/* 802.11 core specific TM State Low flags */ |
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#define B43legacy_TMSLOW_GMODE 0x20000000 /* G Mode Enable */ |
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#define B43legacy_TMSLOW_PLLREFSEL 0x00200000 /* PLL Freq Ref Select */ |
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#define B43legacy_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Ctrl Enbl */ |
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#define B43legacy_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */ |
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#define B43legacy_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */ |
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/* 802.11 core specific TM State High flags */ |
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#define B43legacy_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available */ |
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#define B43legacy_TMSHIGH_GPHY 0x00010000 /* G-PHY avail (rev >= 5) */ |
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#define B43legacy_UCODEFLAG_AUTODIV 0x0001 |
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/* Generic-Interrupt reasons. */ |
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#define B43legacy_IRQ_MAC_SUSPENDED 0x00000001 |
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#define B43legacy_IRQ_BEACON 0x00000002 |
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#define B43legacy_IRQ_TBTT_INDI 0x00000004 /* Target Beacon Transmit Time */ |
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#define B43legacy_IRQ_BEACON_TX_OK 0x00000008 |
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#define B43legacy_IRQ_BEACON_CANCEL 0x00000010 |
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#define B43legacy_IRQ_ATIM_END 0x00000020 |
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#define B43legacy_IRQ_PMQ 0x00000040 |
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#define B43legacy_IRQ_PIO_WORKAROUND 0x00000100 |
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#define B43legacy_IRQ_MAC_TXERR 0x00000200 |
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#define B43legacy_IRQ_PHY_TXERR 0x00000800 |
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#define B43legacy_IRQ_PMEVENT 0x00001000 |
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#define B43legacy_IRQ_TIMER0 0x00002000 |
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#define B43legacy_IRQ_TIMER1 0x00004000 |
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#define B43legacy_IRQ_DMA 0x00008000 |
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#define B43legacy_IRQ_TXFIFO_FLUSH_OK 0x00010000 |
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#define B43legacy_IRQ_CCA_MEASURE_OK 0x00020000 |
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#define B43legacy_IRQ_NOISESAMPLE_OK 0x00040000 |
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#define B43legacy_IRQ_UCODE_DEBUG 0x08000000 |
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#define B43legacy_IRQ_RFKILL 0x10000000 |
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#define B43legacy_IRQ_TX_OK 0x20000000 |
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#define B43legacy_IRQ_PHY_G_CHANGED 0x40000000 |
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#define B43legacy_IRQ_TIMEOUT 0x80000000 |
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#define B43legacy_IRQ_ALL 0xFFFFFFFF |
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#define B43legacy_IRQ_MASKTEMPLATE (B43legacy_IRQ_MAC_SUSPENDED | \ |
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B43legacy_IRQ_TBTT_INDI | \ |
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B43legacy_IRQ_ATIM_END | \ |
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B43legacy_IRQ_PMQ | \ |
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B43legacy_IRQ_MAC_TXERR | \ |
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B43legacy_IRQ_PHY_TXERR | \ |
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B43legacy_IRQ_DMA | \ |
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B43legacy_IRQ_TXFIFO_FLUSH_OK | \ |
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B43legacy_IRQ_NOISESAMPLE_OK | \ |
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B43legacy_IRQ_UCODE_DEBUG | \ |
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B43legacy_IRQ_RFKILL | \ |
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B43legacy_IRQ_TX_OK) |
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/* Device specific rate values. |
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* The actual values defined here are (rate_in_mbps * 2). |
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* Some code depends on this. Don't change it. */ |
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#define B43legacy_CCK_RATE_1MB 2 |
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#define B43legacy_CCK_RATE_2MB 4 |
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#define B43legacy_CCK_RATE_5MB 11 |
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#define B43legacy_CCK_RATE_11MB 22 |
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#define B43legacy_OFDM_RATE_6MB 12 |
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#define B43legacy_OFDM_RATE_9MB 18 |
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#define B43legacy_OFDM_RATE_12MB 24 |
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#define B43legacy_OFDM_RATE_18MB 36 |
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#define B43legacy_OFDM_RATE_24MB 48 |
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#define B43legacy_OFDM_RATE_36MB 72 |
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#define B43legacy_OFDM_RATE_48MB 96 |
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#define B43legacy_OFDM_RATE_54MB 108 |
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/* Convert a b43legacy rate value to a rate in 100kbps */ |
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#define B43legacy_RATE_TO_100KBPS(rate) (((rate) * 10) / 2) |
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#define B43legacy_DEFAULT_SHORT_RETRY_LIMIT 7 |
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#define B43legacy_DEFAULT_LONG_RETRY_LIMIT 4 |
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#define B43legacy_PHY_TX_BADNESS_LIMIT 1000 |
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/* Max size of a security key */ |
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#define B43legacy_SEC_KEYSIZE 16 |
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/* Security algorithms. */ |
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enum { |
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B43legacy_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */ |
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B43legacy_SEC_ALGO_WEP40, |
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B43legacy_SEC_ALGO_TKIP, |
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B43legacy_SEC_ALGO_AES, |
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B43legacy_SEC_ALGO_WEP104, |
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B43legacy_SEC_ALGO_AES_LEGACY, |
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}; |
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/* Core Information Registers */ |
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#define B43legacy_CIR_BASE 0xf00 |
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#define B43legacy_CIR_SBTPSFLAG (B43legacy_CIR_BASE + 0x18) |
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#define B43legacy_CIR_SBIMSTATE (B43legacy_CIR_BASE + 0x90) |
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#define B43legacy_CIR_SBINTVEC (B43legacy_CIR_BASE + 0x94) |
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#define B43legacy_CIR_SBTMSTATELOW (B43legacy_CIR_BASE + 0x98) |
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#define B43legacy_CIR_SBTMSTATEHIGH (B43legacy_CIR_BASE + 0x9c) |
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#define B43legacy_CIR_SBIMCONFIGLOW (B43legacy_CIR_BASE + 0xa8) |
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#define B43legacy_CIR_SB_ID_HI (B43legacy_CIR_BASE + 0xfc) |
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/* sbtmstatehigh state flags */ |
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#define B43legacy_SBTMSTATEHIGH_SERROR 0x00000001 |
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#define B43legacy_SBTMSTATEHIGH_BUSY 0x00000004 |
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#define B43legacy_SBTMSTATEHIGH_TIMEOUT 0x00000020 |
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#define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL 0x00010000 |
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#define B43legacy_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000 |
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#define B43legacy_SBTMSTATEHIGH_DMA64BIT 0x10000000 |
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#define B43legacy_SBTMSTATEHIGH_GATEDCLK 0x20000000 |
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#define B43legacy_SBTMSTATEHIGH_BISTFAILED 0x40000000 |
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#define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE 0x80000000 |
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/* sbimstate flags */ |
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#define B43legacy_SBIMSTATE_IB_ERROR 0x20000 |
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#define B43legacy_SBIMSTATE_TIMEOUT 0x40000 |
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#define PFX KBUILD_MODNAME ": " |
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#ifdef assert |
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# undef assert |
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#endif |
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#ifdef CONFIG_B43LEGACY_DEBUG |
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# define B43legacy_WARN_ON(x) WARN_ON(x) |
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# define B43legacy_BUG_ON(expr) \ |
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do { \ |
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if (unlikely((expr))) { \ |
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printk(KERN_INFO PFX "Test (%s) failed\n", \ |
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#expr); \ |
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BUG_ON(expr); \ |
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} \ |
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} while (0) |
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# define B43legacy_DEBUG 1 |
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#else |
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/* This will evaluate the argument even if debugging is disabled. */ |
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static inline bool __b43legacy_warn_on_dummy(bool x) { return x; } |
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# define B43legacy_WARN_ON(x) __b43legacy_warn_on_dummy(unlikely(!!(x))) |
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# define B43legacy_BUG_ON(x) do { /* nothing */ } while (0) |
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# define B43legacy_DEBUG 0 |
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#endif |
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struct net_device; |
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struct pci_dev; |
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struct b43legacy_dmaring; |
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struct b43legacy_pioqueue; |
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/* The firmware file header */ |
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#define B43legacy_FW_TYPE_UCODE 'u' |
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#define B43legacy_FW_TYPE_PCM 'p' |
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#define B43legacy_FW_TYPE_IV 'i' |
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struct b43legacy_fw_header { |
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/* File type */ |
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u8 type; |
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/* File format version */ |
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u8 ver; |
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u8 __padding[2]; |
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/* Size of the data. For ucode and PCM this is in bytes. |
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* For IV this is number-of-ivs. */ |
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__be32 size; |
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} __packed; |
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/* Initial Value file format */ |
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#define B43legacy_IV_OFFSET_MASK 0x7FFF |
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#define B43legacy_IV_32BIT 0x8000 |
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struct b43legacy_iv { |
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__be16 offset_size; |
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union { |
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__be16 d16; |
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__be32 d32; |
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} data __packed; |
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} __packed; |
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#define B43legacy_PHYMODE(phytype) (1 << (phytype)) |
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#define B43legacy_PHYMODE_B B43legacy_PHYMODE \ |
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((B43legacy_PHYTYPE_B)) |
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#define B43legacy_PHYMODE_G B43legacy_PHYMODE \ |
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((B43legacy_PHYTYPE_G)) |
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|
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/* Value pair to measure the LocalOscillator. */ |
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struct b43legacy_lopair { |
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s8 low; |
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s8 high; |
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u8 used:1; |
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}; |
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#define B43legacy_LO_COUNT (14*4) |
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struct b43legacy_phy { |
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/* Possible PHYMODEs on this PHY */ |
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u8 possible_phymodes; |
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/* GMODE bit enabled in MACCTL? */ |
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bool gmode; |
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|
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/* Analog Type */ |
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u8 analog; |
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/* B43legacy_PHYTYPE_ */ |
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u8 type; |
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/* PHY revision number. */ |
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u8 rev; |
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u16 antenna_diversity; |
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u16 savedpctlreg; |
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/* Radio versioning */ |
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u16 radio_manuf; /* Radio manufacturer */ |
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u16 radio_ver; /* Radio version */ |
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u8 calibrated:1; |
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u8 radio_rev; /* Radio revision */ |
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|
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bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */ |
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|
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/* ACI (adjacent channel interference) flags. */ |
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bool aci_enable; |
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bool aci_wlan_automatic; |
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bool aci_hw_rssi; |
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|
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/* Radio switched on/off */ |
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bool radio_on; |
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struct { |
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/* Values saved when turning the radio off. |
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* They are needed when turning it on again. */ |
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bool valid; |
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u16 rfover; |
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u16 rfoverval; |
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} radio_off_context; |
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u16 minlowsig[2]; |
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u16 minlowsigpos[2]; |
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/* LO Measurement Data. |
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* Use b43legacy_get_lopair() to get a value. |
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*/ |
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struct b43legacy_lopair *_lo_pairs; |
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/* TSSI to dBm table in use */ |
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const s8 *tssi2dbm; |
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/* idle TSSI value */ |
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s8 idle_tssi; |
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/* Target idle TSSI */ |
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int tgt_idle_tssi; |
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/* Current idle TSSI */ |
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int cur_idle_tssi; |
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/* LocalOscillator control values. */ |
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struct b43legacy_txpower_lo_control *lo_control; |
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/* Values from b43legacy_calc_loopback_gain() */ |
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s16 max_lb_gain; /* Maximum Loopback gain in hdB */ |
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s16 trsw_rx_gain; /* TRSW RX gain in hdB */ |
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s16 lna_lod_gain; /* LNA lod */ |
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s16 lna_gain; /* LNA */ |
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s16 pga_gain; /* PGA */ |
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|
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/* Desired TX power level (in dBm). This is set by the user and |
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* adjusted in b43legacy_phy_xmitpower(). */ |
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u8 power_level; |
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|
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/* Values from b43legacy_calc_loopback_gain() */ |
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u16 loopback_gain[2]; |
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/* TX Power control values. */ |
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/* B/G PHY */ |
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struct { |
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/* Current Radio Attenuation for TXpower recalculation. */ |
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u16 rfatt; |
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/* Current Baseband Attenuation for TXpower recalculation. */ |
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u16 bbatt; |
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/* Current TXpower control value for TXpower recalculation. */ |
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u16 txctl1; |
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u16 txctl2; |
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}; |
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/* A PHY */ |
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struct { |
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u16 txpwr_offset; |
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}; |
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/* Current Interference Mitigation mode */ |
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int interfmode; |
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/* Stack of saved values from the Interference Mitigation code. |
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* Each value in the stack is laid out as follows: |
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* bit 0-11: offset |
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* bit 12-15: register ID |
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* bit 16-32: value |
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* register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT |
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*/ |
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#define B43legacy_INTERFSTACK_SIZE 26 |
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u32 interfstack[B43legacy_INTERFSTACK_SIZE]; |
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|
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/* Saved values from the NRSSI Slope calculation */ |
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s16 nrssi[2]; |
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s32 nrssislope; |
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/* In memory nrssi lookup table. */ |
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s8 nrssi_lt[64]; |
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/* current channel */ |
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u8 channel; |
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u16 lofcal; |
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u16 initval; |
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/* PHY TX errors counter. */ |
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atomic_t txerr_cnt; |
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#if B43legacy_DEBUG |
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/* Manual TX-power control enabled? */ |
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bool manual_txpower_control; |
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/* PHY registers locked by b43legacy_phy_lock()? */ |
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bool phy_locked; |
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#endif /* B43legacy_DEBUG */ |
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}; |
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/* Data structures for DMA transmission, per 80211 core. */ |
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struct b43legacy_dma { |
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struct b43legacy_dmaring *tx_ring0; |
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struct b43legacy_dmaring *tx_ring1; |
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struct b43legacy_dmaring *tx_ring2; |
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struct b43legacy_dmaring *tx_ring3; |
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struct b43legacy_dmaring *tx_ring4; |
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struct b43legacy_dmaring *tx_ring5; |
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struct b43legacy_dmaring *rx_ring0; |
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struct b43legacy_dmaring *rx_ring3; /* only on core.rev < 5 */ |
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|
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u32 translation; /* Routing bits */ |
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}; |
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/* Data structures for PIO transmission, per 80211 core. */ |
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struct b43legacy_pio { |
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struct b43legacy_pioqueue *queue0; |
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struct b43legacy_pioqueue *queue1; |
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struct b43legacy_pioqueue *queue2; |
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struct b43legacy_pioqueue *queue3; |
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}; |
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/* Context information for a noise calculation (Link Quality). */ |
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struct b43legacy_noise_calculation { |
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u8 channel_at_start; |
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bool calculation_running; |
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u8 nr_samples; |
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s8 samples[8][4]; |
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}; |
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struct b43legacy_stats { |
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u8 link_noise; |
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/* Store the last TX/RX times here for updating the leds. */ |
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unsigned long last_tx; |
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unsigned long last_rx; |
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}; |
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struct b43legacy_key { |
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void *keyconf; |
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bool enabled; |
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u8 algorithm; |
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}; |
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#define B43legacy_QOS_QUEUE_NUM 4 |
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struct b43legacy_wldev; |
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|
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/* QOS parameters for a queue. */ |
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struct b43legacy_qos_params { |
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/* The QOS parameters */ |
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struct ieee80211_tx_queue_params p; |
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}; |
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/* Data structure for the WLAN parts (802.11 cores) of the b43legacy chip. */ |
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struct b43legacy_wl { |
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/* Pointer to the active wireless device on this chip */ |
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struct b43legacy_wldev *current_dev; |
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/* Pointer to the ieee80211 hardware data structure */ |
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struct ieee80211_hw *hw; |
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spinlock_t irq_lock; /* locks IRQ */ |
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struct mutex mutex; /* locks wireless core state */ |
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spinlock_t leds_lock; /* lock for leds */ |
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/* firmware loading work */ |
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struct work_struct firmware_load; |
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/* We can only have one operating interface (802.11 core) |
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* at a time. General information about this interface follows. |
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*/ |
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struct ieee80211_vif *vif; |
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/* MAC address (can be NULL). */ |
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u8 mac_addr[ETH_ALEN]; |
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/* Current BSSID (can be NULL). */ |
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u8 bssid[ETH_ALEN]; |
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/* Interface type. (IEEE80211_IF_TYPE_XXX) */ |
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int if_type; |
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/* Is the card operating in AP, STA or IBSS mode? */ |
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bool operating; |
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/* filter flags */ |
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unsigned int filter_flags; |
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/* Stats about the wireless interface */ |
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struct ieee80211_low_level_stats ieee_stats; |
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#ifdef CONFIG_B43LEGACY_HWRNG |
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struct hwrng rng; |
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u8 rng_initialized; |
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char rng_name[30 + 1]; |
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#endif |
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/* List of all wireless devices on this chip */ |
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struct list_head devlist; |
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u8 nr_devs; |
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bool radiotap_enabled; |
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bool radio_enabled; |
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/* The beacon we are currently using (AP or IBSS mode). |
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* This beacon stuff is protected by the irq_lock. */ |
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struct sk_buff *current_beacon; |
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bool beacon0_uploaded; |
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bool beacon1_uploaded; |
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bool beacon_templates_virgin; /* Never wrote the templates? */ |
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struct work_struct beacon_update_trigger; |
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/* The current QOS parameters for the 4 queues. */ |
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struct b43legacy_qos_params qos_params[B43legacy_QOS_QUEUE_NUM]; |
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/* Packet transmit work */ |
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struct work_struct tx_work; |
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/* Queue of packets to be transmitted. */ |
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struct sk_buff_head tx_queue[B43legacy_QOS_QUEUE_NUM]; |
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/* Flag that implement the queues stopping. */ |
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bool tx_queue_stopped[B43legacy_QOS_QUEUE_NUM]; |
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}; |
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/* Pointers to the firmware data and meta information about it. */ |
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struct b43legacy_firmware { |
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/* Microcode */ |
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const struct firmware *ucode; |
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/* PCM code */ |
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const struct firmware *pcm; |
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/* Initial MMIO values for the firmware */ |
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const struct firmware *initvals; |
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/* Initial MMIO values for the firmware, band-specific */ |
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const struct firmware *initvals_band; |
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/* Firmware revision */ |
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u16 rev; |
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/* Firmware patchlevel */ |
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u16 patch; |
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}; |
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/* Device (802.11 core) initialization status. */ |
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enum { |
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B43legacy_STAT_UNINIT = 0, /* Uninitialized. */ |
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B43legacy_STAT_INITIALIZED = 1, /* Initialized, not yet started. */ |
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B43legacy_STAT_STARTED = 2, /* Up and running. */ |
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}; |
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#define b43legacy_status(wldev) atomic_read(&(wldev)->__init_status) |
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#define b43legacy_set_status(wldev, stat) do { \ |
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atomic_set(&(wldev)->__init_status, (stat)); \ |
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smp_wmb(); \ |
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} while (0) |
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|
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/* *** --- HOW LOCKING WORKS IN B43legacy --- *** |
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* |
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* You should always acquire both, wl->mutex and wl->irq_lock unless: |
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* - You don't need to acquire wl->irq_lock, if the interface is stopped. |
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* - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet |
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* and packet TX path (and _ONLY_ there.) |
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*/ |
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/* Data structure for one wireless device (802.11 core) */ |
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struct b43legacy_wldev { |
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struct ssb_device *dev; |
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struct b43legacy_wl *wl; |
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|
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/* The device initialization status. |
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* Use b43legacy_status() to query. */ |
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atomic_t __init_status; |
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/* Saved init status for handling suspend. */ |
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int suspend_init_status; |
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bool __using_pio; /* Using pio rather than dma. */ |
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bool bad_frames_preempt;/* Use "Bad Frames Preemption". */ |
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bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM). */ |
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bool short_preamble; /* TRUE if using short preamble. */ |
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bool radio_hw_enable; /* State of radio hardware enable bit. */ |
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/* PHY/Radio device. */ |
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struct b43legacy_phy phy; |
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union { |
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/* DMA engines. */ |
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struct b43legacy_dma dma; |
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/* PIO engines. */ |
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struct b43legacy_pio pio; |
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}; |
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/* Various statistics about the physical device. */ |
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struct b43legacy_stats stats; |
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/* The device LEDs. */ |
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struct b43legacy_led led_tx; |
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struct b43legacy_led led_rx; |
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struct b43legacy_led led_assoc; |
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struct b43legacy_led led_radio; |
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|
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/* Reason code of the last interrupt. */ |
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u32 irq_reason; |
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u32 dma_reason[6]; |
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/* The currently active generic-interrupt mask. */ |
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u32 irq_mask; |
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/* Link Quality calculation context. */ |
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struct b43legacy_noise_calculation noisecalc; |
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/* if > 0 MAC is suspended. if == 0 MAC is enabled. */ |
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int mac_suspended; |
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/* Interrupt Service Routine tasklet (bottom-half) */ |
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struct tasklet_struct isr_tasklet; |
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|
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/* Periodic tasks */ |
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struct delayed_work periodic_work; |
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unsigned int periodic_state; |
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struct work_struct restart_work; |
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/* encryption/decryption */ |
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u16 ktp; /* Key table pointer */ |
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u8 max_nr_keys; |
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struct b43legacy_key key[58]; |
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/* Firmware data */ |
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struct b43legacy_firmware fw; |
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const struct firmware *fwp; /* needed to pass fw pointer */ |
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|
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/* completion struct for firmware loading */ |
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struct completion fw_load_complete; |
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/* Devicelist in struct b43legacy_wl (all 802.11 cores) */ |
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struct list_head list; |
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|
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/* Debugging stuff follows. */ |
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#ifdef CONFIG_B43LEGACY_DEBUG |
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struct b43legacy_dfsentry *dfsentry; |
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#endif |
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}; |
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static inline |
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struct b43legacy_wl *hw_to_b43legacy_wl(struct ieee80211_hw *hw) |
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{ |
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return hw->priv; |
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} |
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|
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/* Helper function, which returns a boolean. |
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* TRUE, if PIO is used; FALSE, if DMA is used. |
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*/ |
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#if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO) |
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static inline |
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int b43legacy_using_pio(struct b43legacy_wldev *dev) |
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{ |
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return dev->__using_pio; |
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} |
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#elif defined(CONFIG_B43LEGACY_DMA) |
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static inline |
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int b43legacy_using_pio(struct b43legacy_wldev *dev) |
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{ |
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return 0; |
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} |
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#elif defined(CONFIG_B43LEGACY_PIO) |
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static inline |
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int b43legacy_using_pio(struct b43legacy_wldev *dev) |
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{ |
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return 1; |
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} |
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#else |
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# error "Using neither DMA nor PIO? Confused..." |
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#endif |
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static inline |
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struct b43legacy_wldev *dev_to_b43legacy_wldev(struct device *dev) |
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{ |
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struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); |
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return ssb_get_drvdata(ssb_dev); |
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} |
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|
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/* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */ |
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static inline |
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int b43legacy_is_mode(struct b43legacy_wl *wl, int type) |
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{ |
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return (wl->operating && |
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wl->if_type == type); |
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} |
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static inline |
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bool is_bcm_board_vendor(struct b43legacy_wldev *dev) |
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{ |
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return (dev->dev->bus->boardinfo.vendor == PCI_VENDOR_ID_BROADCOM); |
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} |
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static inline |
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u16 b43legacy_read16(struct b43legacy_wldev *dev, u16 offset) |
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{ |
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return ssb_read16(dev->dev, offset); |
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} |
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static inline |
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void b43legacy_write16(struct b43legacy_wldev *dev, u16 offset, u16 value) |
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{ |
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ssb_write16(dev->dev, offset, value); |
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} |
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|
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static inline |
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u32 b43legacy_read32(struct b43legacy_wldev *dev, u16 offset) |
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{ |
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return ssb_read32(dev->dev, offset); |
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} |
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|
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static inline |
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void b43legacy_write32(struct b43legacy_wldev *dev, u16 offset, u32 value) |
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{ |
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ssb_write32(dev->dev, offset, value); |
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} |
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|
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static inline |
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struct b43legacy_lopair *b43legacy_get_lopair(struct b43legacy_phy *phy, |
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u16 radio_attenuation, |
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u16 baseband_attenuation) |
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{ |
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return phy->_lo_pairs + (radio_attenuation |
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+ 14 * (baseband_attenuation / 2)); |
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} |
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/* Message printing */ |
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__printf(2, 3) |
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void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...); |
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__printf(2, 3) |
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void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...); |
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__printf(2, 3) |
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void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...); |
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#if B43legacy_DEBUG |
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__printf(2, 3) |
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void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...); |
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#else /* DEBUG */ |
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# define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0) |
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#endif /* DEBUG */ |
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|
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/* Macros for printing a value in Q5.2 format */ |
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#define Q52_FMT "%u.%u" |
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#define Q52_ARG(q52) ((q52) / 4), (((q52) & 3) * 100 / 4) |
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|
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#endif /* B43legacy_H_ */
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