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31 lines
874 B
31 lines
874 B
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
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/* |
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* Driver for Microsemi VSC85xx PHYs |
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* |
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* Copyright (c) 2021 Microsemi Corporation |
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*/ |
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#ifndef _MSCC_SERDES_PHY_H_ |
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#define _MSCC_SERDES_PHY_H_ |
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#define PHY_S6G_PLL5G_CFG2_GAIN_MASK GENMASK(9, 5) |
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#define PHY_S6G_PLL5G_CFG2_ENA_GAIN 1 |
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#define PHY_S6G_DES_PHY_CTRL_POS 13 |
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#define PHY_S6G_DES_MBTR_CTRL_POS 10 |
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#define PHY_S6G_DES_CPMD_SEL_POS 8 |
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#define PHY_S6G_DES_BW_HYST_POS 5 |
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#define PHY_S6G_DES_BW_ANA_POS 1 |
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#define PHY_S6G_DES_CFG 0x21 |
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#define PHY_S6G_IB_CFG0 0x22 |
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#define PHY_S6G_IB_CFG1 0x23 |
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#define PHY_S6G_IB_CFG2 0x24 |
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#define PHY_S6G_IB_CFG3 0x25 |
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#define PHY_S6G_IB_CFG4 0x26 |
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#define PHY_S6G_GP_CFG 0x2E |
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#define PHY_S6G_DFT_CFG0 0x35 |
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#define PHY_S6G_IB_DFT_CFG2 0x37 |
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int vsc85xx_sd6g_config_v2(struct phy_device *phydev); |
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#endif /* _MSCC_PHY_SERDES_H_ */
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