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924 lines
23 KiB
924 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* drivers/net/phy/broadcom.c |
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* |
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* Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet |
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* transceivers. |
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* |
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* Copyright (c) 2006 Maciej W. Rozycki |
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* |
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* Inspired by code written by Amy Fong. |
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*/ |
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#include "bcm-phy-lib.h" |
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#include <linux/module.h> |
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#include <linux/phy.h> |
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#include <linux/brcmphy.h> |
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#include <linux/of.h> |
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#define BRCM_PHY_MODEL(phydev) \ |
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((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask) |
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#define BRCM_PHY_REV(phydev) \ |
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((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask)) |
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MODULE_DESCRIPTION("Broadcom PHY driver"); |
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MODULE_AUTHOR("Maciej W. Rozycki"); |
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MODULE_LICENSE("GPL"); |
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static int bcm54xx_config_clock_delay(struct phy_device *phydev) |
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{ |
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int rc, val; |
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|
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/* handling PHY's internal RX clock delay */ |
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val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); |
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val |= MII_BCM54XX_AUXCTL_MISC_WREN; |
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII || |
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { |
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/* Disable RGMII RXC-RXD skew */ |
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val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; |
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} |
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || |
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phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { |
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/* Enable RGMII RXC-RXD skew */ |
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val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; |
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} |
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rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, |
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val); |
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if (rc < 0) |
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return rc; |
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/* handling PHY's internal TX clock delay */ |
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val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL); |
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII || |
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phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { |
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/* Disable internal TX clock delay */ |
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val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN; |
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} |
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || |
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { |
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/* Enable internal TX clock delay */ |
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val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN; |
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} |
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rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val); |
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if (rc < 0) |
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return rc; |
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return 0; |
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} |
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static int bcm54210e_config_init(struct phy_device *phydev) |
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{ |
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int val; |
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bcm54xx_config_clock_delay(phydev); |
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if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) { |
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val = phy_read(phydev, MII_CTRL1000); |
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val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; |
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phy_write(phydev, MII_CTRL1000, val); |
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} |
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return 0; |
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} |
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static int bcm54213pe_config_init(struct phy_device *phydev) |
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{ |
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return bcm54210e_config_init(phydev); |
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} |
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static int bcm54612e_config_init(struct phy_device *phydev) |
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{ |
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int reg; |
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bcm54xx_config_clock_delay(phydev); |
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/* Enable CLK125 MUX on LED4 if ref clock is enabled. */ |
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if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { |
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int err; |
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reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0); |
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err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0, |
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BCM54612E_LED4_CLK125OUT_EN | reg); |
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if (err < 0) |
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return err; |
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} |
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return 0; |
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} |
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static int bcm54616s_config_init(struct phy_device *phydev) |
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{ |
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int rc, val; |
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if (phydev->interface != PHY_INTERFACE_MODE_SGMII && |
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phydev->interface != PHY_INTERFACE_MODE_1000BASEX) |
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return 0; |
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/* Ensure proper interface mode is selected. */ |
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/* Disable RGMII mode */ |
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val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); |
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if (val < 0) |
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return val; |
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val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN; |
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val |= MII_BCM54XX_AUXCTL_MISC_WREN; |
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rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, |
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val); |
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if (rc < 0) |
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return rc; |
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/* Select 1000BASE-X register set (primary SerDes) */ |
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val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE); |
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if (val < 0) |
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return val; |
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val |= BCM54XX_SHD_MODE_1000BX; |
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rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); |
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if (rc < 0) |
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return rc; |
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/* Power down SerDes interface */ |
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rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); |
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if (rc < 0) |
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return rc; |
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/* Select proper interface mode */ |
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val &= ~BCM54XX_SHD_INTF_SEL_MASK; |
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val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ? |
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BCM54XX_SHD_INTF_SEL_SGMII : |
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BCM54XX_SHD_INTF_SEL_GBIC; |
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rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); |
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if (rc < 0) |
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return rc; |
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/* Power up SerDes interface */ |
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rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); |
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if (rc < 0) |
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return rc; |
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/* Select copper register set */ |
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val &= ~BCM54XX_SHD_MODE_1000BX; |
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rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); |
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if (rc < 0) |
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return rc; |
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/* Power up copper interface */ |
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return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); |
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} |
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/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */ |
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static int bcm50610_a0_workaround(struct phy_device *phydev) |
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{ |
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int err; |
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err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0, |
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MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN | |
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MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF); |
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if (err < 0) |
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return err; |
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err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3, |
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MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ); |
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if (err < 0) |
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return err; |
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err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, |
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MII_BCM54XX_EXP_EXP75_VDACCTRL); |
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if (err < 0) |
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return err; |
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err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96, |
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MII_BCM54XX_EXP_EXP96_MYST); |
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if (err < 0) |
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return err; |
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err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97, |
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MII_BCM54XX_EXP_EXP97_MYST); |
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return err; |
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} |
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static int bcm54xx_phydsp_config(struct phy_device *phydev) |
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{ |
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int err, err2; |
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/* Enable the SMDSP clock */ |
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err = bcm54xx_auxctl_write(phydev, |
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MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL, |
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MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA | |
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MII_BCM54XX_AUXCTL_ACTL_TX_6DB); |
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if (err < 0) |
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return err; |
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if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 || |
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BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) { |
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/* Clear bit 9 to fix a phy interop issue. */ |
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err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, |
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MII_BCM54XX_EXP_EXP08_RJCT_2MHZ); |
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if (err < 0) |
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goto error; |
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if (phydev->drv->phy_id == PHY_ID_BCM50610) { |
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err = bcm50610_a0_workaround(phydev); |
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if (err < 0) |
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goto error; |
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} |
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} |
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if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) { |
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int val; |
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val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75); |
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if (val < 0) |
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goto error; |
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val |= MII_BCM54XX_EXP_EXP75_CM_OSC; |
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err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val); |
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} |
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error: |
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/* Disable the SMDSP clock */ |
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err2 = bcm54xx_auxctl_write(phydev, |
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MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL, |
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MII_BCM54XX_AUXCTL_ACTL_TX_6DB); |
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/* Return the first error reported. */ |
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return err ? err : err2; |
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} |
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static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev) |
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{ |
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u32 orig; |
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int val; |
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bool clk125en = true; |
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/* Abort if we are using an untested phy. */ |
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if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 && |
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BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 && |
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BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M && |
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BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54210E && |
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BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 && |
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BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811 && |
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BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54213PE) |
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return; |
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val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3); |
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if (val < 0) |
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return; |
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orig = val; |
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if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 || |
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BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) && |
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BRCM_PHY_REV(phydev) >= 0x3) { |
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/* |
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* Here, bit 0 _disables_ CLK125 when set. |
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* This bit is set by default. |
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*/ |
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clk125en = false; |
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} else { |
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if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) { |
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if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) { |
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/* Here, bit 0 _enables_ CLK125 when set */ |
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val &= ~BCM54XX_SHD_SCR3_DEF_CLK125; |
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} |
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clk125en = false; |
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} |
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} |
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if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) |
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val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS; |
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else |
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val |= BCM54XX_SHD_SCR3_DLLAPD_DIS; |
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if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) { |
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if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E || |
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BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 || |
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BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) |
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val |= BCM54XX_SHD_SCR3_RXCTXC_DIS; |
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else |
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val |= BCM54XX_SHD_SCR3_TRDDAPD; |
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} |
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if (orig != val) |
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bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val); |
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val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD); |
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if (val < 0) |
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return; |
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orig = val; |
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if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) |
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val |= BCM54XX_SHD_APD_EN; |
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else |
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val &= ~BCM54XX_SHD_APD_EN; |
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if (orig != val) |
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bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val); |
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} |
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static int bcm54xx_config_init(struct phy_device *phydev) |
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{ |
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int reg, err, val; |
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u32 led_modes[] = {BCM_LED_MULTICOLOR_LINK_ACT, |
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BCM_LED_MULTICOLOR_LINK}; |
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struct device_node *np = phydev->mdio.dev.of_node; |
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reg = phy_read(phydev, MII_BCM54XX_ECR); |
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if (reg < 0) |
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return reg; |
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/* Mask interrupts globally. */ |
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reg |= MII_BCM54XX_ECR_IM; |
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err = phy_write(phydev, MII_BCM54XX_ECR, reg); |
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if (err < 0) |
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return err; |
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/* Unmask events we are interested in. */ |
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reg = ~(MII_BCM54XX_INT_DUPLEX | |
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MII_BCM54XX_INT_SPEED | |
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MII_BCM54XX_INT_LINK); |
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err = phy_write(phydev, MII_BCM54XX_IMR, reg); |
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if (err < 0) |
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return err; |
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if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 || |
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BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) && |
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(phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE)) |
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bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0); |
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bcm54xx_adjust_rxrefclk(phydev); |
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switch (BRCM_PHY_MODEL(phydev)) { |
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case PHY_ID_BCM50610: |
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case PHY_ID_BCM50610M: |
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err = bcm54xx_config_clock_delay(phydev); |
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break; |
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case PHY_ID_BCM54210E: |
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err = bcm54210e_config_init(phydev); |
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break; |
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case PHY_ID_BCM54612E: |
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err = bcm54612e_config_init(phydev); |
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break; |
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case PHY_ID_BCM54213PE: |
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err = bcm54213pe_config_init(phydev); |
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break; |
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case PHY_ID_BCM54616S: |
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err = bcm54616s_config_init(phydev); |
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break; |
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case PHY_ID_BCM54810: |
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/* For BCM54810, we need to disable BroadR-Reach function */ |
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val = bcm_phy_read_exp(phydev, |
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BCM54810_EXP_BROADREACH_LRE_MISC_CTL); |
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val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN; |
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err = bcm_phy_write_exp(phydev, |
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BCM54810_EXP_BROADREACH_LRE_MISC_CTL, |
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val); |
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break; |
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} |
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if (err) |
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return err; |
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bcm54xx_phydsp_config(phydev); |
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of_property_read_u32_array(np, "led-modes", led_modes, 2); |
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/* For non-SFP setups, encode link speed into LED1 and LED3 pair |
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* (green/amber). |
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* Don't do this for devices on an SFP module, since some of these |
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* use the LED outputs to control the SFP LOS signal, and changing |
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* these settings will cause LOS to malfunction. |
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*/ |
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if (!phy_on_sfp(phydev)) { |
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val = BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) | |
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BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1); |
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bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val); |
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val = BCM_LED_MULTICOLOR_IN_PHASE | |
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BCM5482_SHD_LEDS1_LED1(led_modes[0]) | |
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BCM5482_SHD_LEDS1_LED3(led_modes[1]); |
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bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val); |
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} |
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return 0; |
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} |
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static int bcm54xx_resume(struct phy_device *phydev) |
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{ |
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int ret; |
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|
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/* Writes to register other than BMCR would be ignored |
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* unless we clear the PDOWN bit first |
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*/ |
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ret = genphy_resume(phydev); |
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if (ret < 0) |
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return ret; |
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/* Upon exiting power down, the PHY remains in an internal reset state |
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* for 40us |
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*/ |
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fsleep(40); |
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return bcm54xx_config_init(phydev); |
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} |
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static int bcm54811_config_init(struct phy_device *phydev) |
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{ |
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int err, reg; |
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/* Disable BroadR-Reach function. */ |
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reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL); |
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reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN; |
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err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL, |
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reg); |
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if (err < 0) |
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return err; |
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err = bcm54xx_config_init(phydev); |
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/* Enable CLK125 MUX on LED4 if ref clock is enabled. */ |
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if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { |
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reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0); |
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err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0, |
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BCM54612E_LED4_CLK125OUT_EN | reg); |
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if (err < 0) |
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return err; |
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} |
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return err; |
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} |
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static int bcm5481_config_aneg(struct phy_device *phydev) |
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{ |
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struct device_node *np = phydev->mdio.dev.of_node; |
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int ret; |
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/* Aneg firstly. */ |
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ret = genphy_config_aneg(phydev); |
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|
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/* Then we can set up the delay. */ |
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bcm54xx_config_clock_delay(phydev); |
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if (of_property_read_bool(np, "enet-phy-lane-swap")) { |
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/* Lane Swap - Undocumented register...magic! */ |
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ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9, |
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0x11B); |
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if (ret < 0) |
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return ret; |
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} |
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return ret; |
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} |
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struct bcm54616s_phy_priv { |
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bool mode_1000bx_en; |
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}; |
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static int bcm54616s_probe(struct phy_device *phydev) |
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{ |
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struct bcm54616s_phy_priv *priv; |
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int val; |
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priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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phydev->priv = priv; |
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val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE); |
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if (val < 0) |
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return val; |
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|
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/* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0] |
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* is 01b, and the link between PHY and its link partner can be |
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* either 1000Base-X or 100Base-FX. |
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* RGMII-1000Base-X is properly supported, but RGMII-100Base-FX |
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* support is still missing as of now. |
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*/ |
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if ((val & BCM54XX_SHD_INTF_SEL_MASK) == BCM54XX_SHD_INTF_SEL_RGMII) { |
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val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL); |
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if (val < 0) |
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return val; |
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|
|
/* Bit 0 of the SerDes 100-FX Control register, when set |
|
* to 1, sets the MII/RGMII -> 100BASE-FX configuration. |
|
* When this bit is set to 0, it sets the GMII/RGMII -> |
|
* 1000BASE-X configuration. |
|
*/ |
|
if (!(val & BCM54616S_100FX_MODE)) |
|
priv->mode_1000bx_en = true; |
|
|
|
phydev->port = PORT_FIBRE; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int bcm54616s_config_aneg(struct phy_device *phydev) |
|
{ |
|
struct bcm54616s_phy_priv *priv = phydev->priv; |
|
int ret; |
|
|
|
/* Aneg firstly. */ |
|
if (priv->mode_1000bx_en) |
|
ret = genphy_c37_config_aneg(phydev); |
|
else |
|
ret = genphy_config_aneg(phydev); |
|
|
|
/* Then we can set up the delay. */ |
|
bcm54xx_config_clock_delay(phydev); |
|
|
|
return ret; |
|
} |
|
|
|
static int bcm54616s_read_status(struct phy_device *phydev) |
|
{ |
|
struct bcm54616s_phy_priv *priv = phydev->priv; |
|
int err; |
|
|
|
if (priv->mode_1000bx_en) |
|
err = genphy_c37_read_status(phydev); |
|
else |
|
err = genphy_read_status(phydev); |
|
|
|
return err; |
|
} |
|
|
|
static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set) |
|
{ |
|
int val; |
|
|
|
val = phy_read(phydev, reg); |
|
if (val < 0) |
|
return val; |
|
|
|
return phy_write(phydev, reg, val | set); |
|
} |
|
|
|
static int brcm_fet_config_init(struct phy_device *phydev) |
|
{ |
|
int reg, err, err2, brcmtest; |
|
|
|
/* Reset the PHY to bring it to a known state. */ |
|
err = phy_write(phydev, MII_BMCR, BMCR_RESET); |
|
if (err < 0) |
|
return err; |
|
|
|
reg = phy_read(phydev, MII_BRCM_FET_INTREG); |
|
if (reg < 0) |
|
return reg; |
|
|
|
/* Unmask events we are interested in and mask interrupts globally. */ |
|
reg = MII_BRCM_FET_IR_DUPLEX_EN | |
|
MII_BRCM_FET_IR_SPEED_EN | |
|
MII_BRCM_FET_IR_LINK_EN | |
|
MII_BRCM_FET_IR_ENABLE | |
|
MII_BRCM_FET_IR_MASK; |
|
|
|
err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); |
|
if (err < 0) |
|
return err; |
|
|
|
/* Enable shadow register access */ |
|
brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); |
|
if (brcmtest < 0) |
|
return brcmtest; |
|
|
|
reg = brcmtest | MII_BRCM_FET_BT_SRE; |
|
|
|
err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); |
|
if (err < 0) |
|
return err; |
|
|
|
/* Set the LED mode */ |
|
reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4); |
|
if (reg < 0) { |
|
err = reg; |
|
goto done; |
|
} |
|
|
|
reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK; |
|
reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1; |
|
|
|
err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); |
|
if (err < 0) |
|
goto done; |
|
|
|
/* Enable auto MDIX */ |
|
err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL, |
|
MII_BRCM_FET_SHDW_MC_FAME); |
|
if (err < 0) |
|
goto done; |
|
|
|
if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) { |
|
/* Enable auto power down */ |
|
err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, |
|
MII_BRCM_FET_SHDW_AS2_APDE); |
|
} |
|
|
|
done: |
|
/* Disable shadow register access */ |
|
err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); |
|
if (!err) |
|
err = err2; |
|
|
|
return err; |
|
} |
|
|
|
static int brcm_fet_ack_interrupt(struct phy_device *phydev) |
|
{ |
|
int reg; |
|
|
|
/* Clear pending interrupts. */ |
|
reg = phy_read(phydev, MII_BRCM_FET_INTREG); |
|
if (reg < 0) |
|
return reg; |
|
|
|
return 0; |
|
} |
|
|
|
static int brcm_fet_config_intr(struct phy_device *phydev) |
|
{ |
|
int reg, err; |
|
|
|
reg = phy_read(phydev, MII_BRCM_FET_INTREG); |
|
if (reg < 0) |
|
return reg; |
|
|
|
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
|
err = brcm_fet_ack_interrupt(phydev); |
|
if (err) |
|
return err; |
|
|
|
reg &= ~MII_BRCM_FET_IR_MASK; |
|
err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); |
|
} else { |
|
reg |= MII_BRCM_FET_IR_MASK; |
|
err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); |
|
if (err) |
|
return err; |
|
|
|
err = brcm_fet_ack_interrupt(phydev); |
|
} |
|
|
|
return err; |
|
} |
|
|
|
static irqreturn_t brcm_fet_handle_interrupt(struct phy_device *phydev) |
|
{ |
|
int irq_status; |
|
|
|
irq_status = phy_read(phydev, MII_BRCM_FET_INTREG); |
|
if (irq_status < 0) { |
|
phy_error(phydev); |
|
return IRQ_NONE; |
|
} |
|
|
|
if (irq_status == 0) |
|
return IRQ_NONE; |
|
|
|
phy_trigger_machine(phydev); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
struct bcm53xx_phy_priv { |
|
u64 *stats; |
|
}; |
|
|
|
static int bcm53xx_phy_probe(struct phy_device *phydev) |
|
{ |
|
struct bcm53xx_phy_priv *priv; |
|
|
|
priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); |
|
if (!priv) |
|
return -ENOMEM; |
|
|
|
phydev->priv = priv; |
|
|
|
priv->stats = devm_kcalloc(&phydev->mdio.dev, |
|
bcm_phy_get_sset_count(phydev), sizeof(u64), |
|
GFP_KERNEL); |
|
if (!priv->stats) |
|
return -ENOMEM; |
|
|
|
return 0; |
|
} |
|
|
|
static void bcm53xx_phy_get_stats(struct phy_device *phydev, |
|
struct ethtool_stats *stats, u64 *data) |
|
{ |
|
struct bcm53xx_phy_priv *priv = phydev->priv; |
|
|
|
bcm_phy_get_stats(phydev, priv->stats, stats, data); |
|
} |
|
|
|
static struct phy_driver broadcom_drivers[] = { |
|
{ |
|
.phy_id = PHY_ID_BCM5411, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM5411", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
}, { |
|
.phy_id = PHY_ID_BCM5421, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM5421", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
}, { |
|
.phy_id = PHY_ID_BCM54210E, |
|
.phy_id_mask = 0xffffffff, |
|
.name = "Broadcom BCM54210E", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
}, { |
|
.phy_id = PHY_ID_BCM54213PE, |
|
.phy_id_mask = 0xffffffff, |
|
.name = "Broadcom BCM54213PE", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_intr = bcm_phy_config_intr, |
|
}, { |
|
.phy_id = PHY_ID_BCM5461, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM5461", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
}, { |
|
.phy_id = PHY_ID_BCM54612E, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM54612E", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
}, { |
|
.phy_id = PHY_ID_BCM54616S, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM54616S", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_aneg = bcm54616s_config_aneg, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
.read_status = bcm54616s_read_status, |
|
.probe = bcm54616s_probe, |
|
}, { |
|
.phy_id = PHY_ID_BCM5464, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM5464", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
.suspend = genphy_suspend, |
|
.resume = genphy_resume, |
|
}, { |
|
.phy_id = PHY_ID_BCM5481, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM5481", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_aneg = bcm5481_config_aneg, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
}, { |
|
.phy_id = PHY_ID_BCM54810, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM54810", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_aneg = bcm5481_config_aneg, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
.suspend = genphy_suspend, |
|
.resume = bcm54xx_resume, |
|
}, { |
|
.phy_id = PHY_ID_BCM54811, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM54811", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54811_config_init, |
|
.config_aneg = bcm5481_config_aneg, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
.suspend = genphy_suspend, |
|
.resume = bcm54xx_resume, |
|
}, { |
|
.phy_id = PHY_ID_BCM5482, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM5482", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
}, { |
|
.phy_id = PHY_ID_BCM50610, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM50610", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
}, { |
|
.phy_id = PHY_ID_BCM50610M, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM50610M", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
}, { |
|
.phy_id = PHY_ID_BCM57780, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM57780", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
}, { |
|
.phy_id = PHY_ID_BCMAC131, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCMAC131", |
|
/* PHY_BASIC_FEATURES */ |
|
.config_init = brcm_fet_config_init, |
|
.config_intr = brcm_fet_config_intr, |
|
.handle_interrupt = brcm_fet_handle_interrupt, |
|
}, { |
|
.phy_id = PHY_ID_BCM5241, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM5241", |
|
/* PHY_BASIC_FEATURES */ |
|
.config_init = brcm_fet_config_init, |
|
.config_intr = brcm_fet_config_intr, |
|
.handle_interrupt = brcm_fet_handle_interrupt, |
|
}, { |
|
.phy_id = PHY_ID_BCM5395, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM5395", |
|
.flags = PHY_IS_INTERNAL, |
|
/* PHY_GBIT_FEATURES */ |
|
.get_sset_count = bcm_phy_get_sset_count, |
|
.get_strings = bcm_phy_get_strings, |
|
.get_stats = bcm53xx_phy_get_stats, |
|
.probe = bcm53xx_phy_probe, |
|
}, { |
|
.phy_id = PHY_ID_BCM53125, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM53125", |
|
.flags = PHY_IS_INTERNAL, |
|
/* PHY_GBIT_FEATURES */ |
|
.get_sset_count = bcm_phy_get_sset_count, |
|
.get_strings = bcm_phy_get_strings, |
|
.get_stats = bcm53xx_phy_get_stats, |
|
.probe = bcm53xx_phy_probe, |
|
.config_init = bcm54xx_config_init, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
}, { |
|
.phy_id = PHY_ID_BCM89610, |
|
.phy_id_mask = 0xfffffff0, |
|
.name = "Broadcom BCM89610", |
|
/* PHY_GBIT_FEATURES */ |
|
.config_init = bcm54xx_config_init, |
|
.config_intr = bcm_phy_config_intr, |
|
.handle_interrupt = bcm_phy_handle_interrupt, |
|
} }; |
|
|
|
module_phy_driver(broadcom_drivers); |
|
|
|
static struct mdio_device_id __maybe_unused broadcom_tbl[] = { |
|
{ PHY_ID_BCM5411, 0xfffffff0 }, |
|
{ PHY_ID_BCM5421, 0xfffffff0 }, |
|
{ PHY_ID_BCM54210E, 0xffffffff }, |
|
{ PHY_ID_BCM54213PE, 0xffffffff }, |
|
{ PHY_ID_BCM5461, 0xfffffff0 }, |
|
{ PHY_ID_BCM54612E, 0xfffffff0 }, |
|
{ PHY_ID_BCM54616S, 0xfffffff0 }, |
|
{ PHY_ID_BCM5464, 0xfffffff0 }, |
|
{ PHY_ID_BCM5481, 0xfffffff0 }, |
|
{ PHY_ID_BCM54810, 0xfffffff0 }, |
|
{ PHY_ID_BCM54811, 0xfffffff0 }, |
|
{ PHY_ID_BCM5482, 0xfffffff0 }, |
|
{ PHY_ID_BCM50610, 0xfffffff0 }, |
|
{ PHY_ID_BCM50610M, 0xfffffff0 }, |
|
{ PHY_ID_BCM57780, 0xfffffff0 }, |
|
{ PHY_ID_BCMAC131, 0xfffffff0 }, |
|
{ PHY_ID_BCM5241, 0xfffffff0 }, |
|
{ PHY_ID_BCM5395, 0xfffffff0 }, |
|
{ PHY_ID_BCM53125, 0xfffffff0 }, |
|
{ PHY_ID_BCM89610, 0xfffffff0 }, |
|
{ } |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(mdio, broadcom_tbl);
|
|
|