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716 lines
17 KiB
716 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2020 Synopsys, Inc. and/or its affiliates. |
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* Synopsys DesignWare XPCS helpers |
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* |
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* Author: Jose Abreu <[email protected]> |
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*/ |
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#include <linux/delay.h> |
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#include <linux/pcs/pcs-xpcs.h> |
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#include <linux/mdio.h> |
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#include <linux/phylink.h> |
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#include <linux/workqueue.h> |
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#define SYNOPSYS_XPCS_USXGMII_ID 0x7996ced0 |
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#define SYNOPSYS_XPCS_10GKR_ID 0x7996ced0 |
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#define SYNOPSYS_XPCS_XLGMII_ID 0x7996ced0 |
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#define SYNOPSYS_XPCS_MASK 0xffffffff |
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/* Vendor regs access */ |
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#define DW_VENDOR BIT(15) |
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/* VR_XS_PCS */ |
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#define DW_USXGMII_RST BIT(10) |
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#define DW_USXGMII_EN BIT(9) |
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#define DW_VR_XS_PCS_DIG_STS 0x0010 |
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#define DW_RXFIFO_ERR GENMASK(6, 5) |
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/* SR_MII */ |
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#define DW_USXGMII_FULL BIT(8) |
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#define DW_USXGMII_SS_MASK (BIT(13) | BIT(6) | BIT(5)) |
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#define DW_USXGMII_10000 (BIT(13) | BIT(6)) |
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#define DW_USXGMII_5000 (BIT(13) | BIT(5)) |
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#define DW_USXGMII_2500 (BIT(5)) |
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#define DW_USXGMII_1000 (BIT(6)) |
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#define DW_USXGMII_100 (BIT(13)) |
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#define DW_USXGMII_10 (0) |
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/* SR_AN */ |
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#define DW_SR_AN_ADV1 0x10 |
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#define DW_SR_AN_ADV2 0x11 |
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#define DW_SR_AN_ADV3 0x12 |
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#define DW_SR_AN_LP_ABL1 0x13 |
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#define DW_SR_AN_LP_ABL2 0x14 |
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#define DW_SR_AN_LP_ABL3 0x15 |
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/* Clause 73 Defines */ |
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/* AN_LP_ABL1 */ |
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#define DW_C73_PAUSE BIT(10) |
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#define DW_C73_ASYM_PAUSE BIT(11) |
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#define DW_C73_AN_ADV_SF 0x1 |
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/* AN_LP_ABL2 */ |
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#define DW_C73_1000KX BIT(5) |
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#define DW_C73_10000KX4 BIT(6) |
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#define DW_C73_10000KR BIT(7) |
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/* AN_LP_ABL3 */ |
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#define DW_C73_2500KX BIT(0) |
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#define DW_C73_5000KR BIT(1) |
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static const int xpcs_usxgmii_features[] = { |
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ETHTOOL_LINK_MODE_Pause_BIT, |
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ETHTOOL_LINK_MODE_Asym_Pause_BIT, |
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ETHTOOL_LINK_MODE_Autoneg_BIT, |
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ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, |
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ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, |
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ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, |
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ETHTOOL_LINK_MODE_2500baseX_Full_BIT, |
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__ETHTOOL_LINK_MODE_MASK_NBITS, |
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}; |
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static const int xpcs_10gkr_features[] = { |
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ETHTOOL_LINK_MODE_Pause_BIT, |
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ETHTOOL_LINK_MODE_Asym_Pause_BIT, |
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ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, |
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__ETHTOOL_LINK_MODE_MASK_NBITS, |
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}; |
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static const int xpcs_xlgmii_features[] = { |
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ETHTOOL_LINK_MODE_Pause_BIT, |
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ETHTOOL_LINK_MODE_Asym_Pause_BIT, |
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ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, |
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ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, |
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ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, |
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ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, |
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ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, |
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ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, |
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ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseDR_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT, |
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__ETHTOOL_LINK_MODE_MASK_NBITS, |
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}; |
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static const phy_interface_t xpcs_usxgmii_interfaces[] = { |
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PHY_INTERFACE_MODE_USXGMII, |
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PHY_INTERFACE_MODE_MAX, |
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}; |
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static const phy_interface_t xpcs_10gkr_interfaces[] = { |
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PHY_INTERFACE_MODE_10GKR, |
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PHY_INTERFACE_MODE_MAX, |
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}; |
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static const phy_interface_t xpcs_xlgmii_interfaces[] = { |
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PHY_INTERFACE_MODE_XLGMII, |
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PHY_INTERFACE_MODE_MAX, |
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}; |
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static struct xpcs_id { |
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u32 id; |
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u32 mask; |
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const int *supported; |
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const phy_interface_t *interface; |
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} xpcs_id_list[] = { |
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{ |
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.id = SYNOPSYS_XPCS_USXGMII_ID, |
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.mask = SYNOPSYS_XPCS_MASK, |
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.supported = xpcs_usxgmii_features, |
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.interface = xpcs_usxgmii_interfaces, |
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}, { |
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.id = SYNOPSYS_XPCS_10GKR_ID, |
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.mask = SYNOPSYS_XPCS_MASK, |
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.supported = xpcs_10gkr_features, |
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.interface = xpcs_10gkr_interfaces, |
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}, { |
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.id = SYNOPSYS_XPCS_XLGMII_ID, |
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.mask = SYNOPSYS_XPCS_MASK, |
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.supported = xpcs_xlgmii_features, |
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.interface = xpcs_xlgmii_interfaces, |
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}, |
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}; |
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static int xpcs_read(struct mdio_xpcs_args *xpcs, int dev, u32 reg) |
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{ |
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u32 reg_addr = MII_ADDR_C45 | dev << 16 | reg; |
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return mdiobus_read(xpcs->bus, xpcs->addr, reg_addr); |
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} |
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static int xpcs_write(struct mdio_xpcs_args *xpcs, int dev, u32 reg, u16 val) |
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{ |
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u32 reg_addr = MII_ADDR_C45 | dev << 16 | reg; |
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return mdiobus_write(xpcs->bus, xpcs->addr, reg_addr, val); |
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} |
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static int xpcs_read_vendor(struct mdio_xpcs_args *xpcs, int dev, u32 reg) |
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{ |
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return xpcs_read(xpcs, dev, DW_VENDOR | reg); |
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} |
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static int xpcs_write_vendor(struct mdio_xpcs_args *xpcs, int dev, int reg, |
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u16 val) |
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{ |
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return xpcs_write(xpcs, dev, DW_VENDOR | reg, val); |
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} |
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static int xpcs_read_vpcs(struct mdio_xpcs_args *xpcs, int reg) |
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{ |
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return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg); |
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} |
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static int xpcs_write_vpcs(struct mdio_xpcs_args *xpcs, int reg, u16 val) |
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{ |
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return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val); |
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} |
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static int xpcs_poll_reset(struct mdio_xpcs_args *xpcs, int dev) |
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{ |
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/* Poll until the reset bit clears (50ms per retry == 0.6 sec) */ |
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unsigned int retries = 12; |
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int ret; |
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do { |
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msleep(50); |
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ret = xpcs_read(xpcs, dev, MDIO_CTRL1); |
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if (ret < 0) |
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return ret; |
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} while (ret & MDIO_CTRL1_RESET && --retries); |
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return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0; |
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} |
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static int xpcs_soft_reset(struct mdio_xpcs_args *xpcs, int dev) |
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{ |
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int ret; |
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ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET); |
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if (ret < 0) |
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return ret; |
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return xpcs_poll_reset(xpcs, dev); |
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} |
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#define xpcs_warn(__xpcs, __state, __args...) \ |
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({ \ |
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if ((__state)->link) \ |
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dev_warn(&(__xpcs)->bus->dev, ##__args); \ |
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}) |
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static int xpcs_read_fault(struct mdio_xpcs_args *xpcs, |
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struct phylink_link_state *state) |
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{ |
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int ret; |
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ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); |
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if (ret < 0) |
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return ret; |
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if (ret & MDIO_STAT1_FAULT) { |
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xpcs_warn(xpcs, state, "Link fault condition detected!\n"); |
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return -EFAULT; |
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} |
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ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2); |
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if (ret < 0) |
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return ret; |
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if (ret & MDIO_STAT2_RXFAULT) |
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xpcs_warn(xpcs, state, "Receiver fault detected!\n"); |
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if (ret & MDIO_STAT2_TXFAULT) |
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xpcs_warn(xpcs, state, "Transmitter fault detected!\n"); |
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ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS); |
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if (ret < 0) |
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return ret; |
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if (ret & DW_RXFIFO_ERR) { |
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xpcs_warn(xpcs, state, "FIFO fault condition detected!\n"); |
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return -EFAULT; |
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} |
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ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); |
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if (ret < 0) |
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return ret; |
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if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK)) |
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xpcs_warn(xpcs, state, "Link is not locked!\n"); |
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ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2); |
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if (ret < 0) |
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return ret; |
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if (ret & MDIO_PCS_10GBRT_STAT2_ERR) { |
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xpcs_warn(xpcs, state, "Link has errors!\n"); |
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return -EFAULT; |
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} |
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return 0; |
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} |
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static int xpcs_read_link(struct mdio_xpcs_args *xpcs, bool an) |
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{ |
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bool link = true; |
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int ret; |
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ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); |
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if (ret < 0) |
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return ret; |
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if (!(ret & MDIO_STAT1_LSTATUS)) |
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link = false; |
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if (an) { |
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ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); |
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if (ret < 0) |
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return ret; |
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if (!(ret & MDIO_STAT1_LSTATUS)) |
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link = false; |
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} |
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return link; |
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} |
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static int xpcs_get_max_usxgmii_speed(const unsigned long *supported) |
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{ |
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int max = SPEED_UNKNOWN; |
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if (phylink_test(supported, 1000baseKX_Full)) |
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max = SPEED_1000; |
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if (phylink_test(supported, 2500baseX_Full)) |
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max = SPEED_2500; |
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if (phylink_test(supported, 10000baseKX4_Full)) |
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max = SPEED_10000; |
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if (phylink_test(supported, 10000baseKR_Full)) |
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max = SPEED_10000; |
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return max; |
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} |
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static int xpcs_config_usxgmii(struct mdio_xpcs_args *xpcs, int speed) |
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{ |
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int ret, speed_sel; |
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switch (speed) { |
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case SPEED_10: |
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speed_sel = DW_USXGMII_10; |
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break; |
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case SPEED_100: |
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speed_sel = DW_USXGMII_100; |
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break; |
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case SPEED_1000: |
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speed_sel = DW_USXGMII_1000; |
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break; |
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case SPEED_2500: |
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speed_sel = DW_USXGMII_2500; |
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break; |
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case SPEED_5000: |
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speed_sel = DW_USXGMII_5000; |
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break; |
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case SPEED_10000: |
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speed_sel = DW_USXGMII_10000; |
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break; |
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default: |
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/* Nothing to do here */ |
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return -EINVAL; |
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} |
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ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1); |
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if (ret < 0) |
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return ret; |
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ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN); |
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if (ret < 0) |
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return ret; |
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ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); |
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if (ret < 0) |
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return ret; |
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ret &= ~DW_USXGMII_SS_MASK; |
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ret |= speed_sel | DW_USXGMII_FULL; |
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ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); |
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if (ret < 0) |
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return ret; |
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ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1); |
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if (ret < 0) |
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return ret; |
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return xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST); |
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} |
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static int xpcs_config_aneg_c73(struct mdio_xpcs_args *xpcs) |
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{ |
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int ret, adv; |
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/* By default, in USXGMII mode XPCS operates at 10G baud and |
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* replicates data to achieve lower speeds. Hereby, in this |
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* default configuration we need to advertise all supported |
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* modes and not only the ones we want to use. |
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*/ |
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/* SR_AN_ADV3 */ |
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adv = 0; |
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if (phylink_test(xpcs->supported, 2500baseX_Full)) |
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adv |= DW_C73_2500KX; |
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/* TODO: 5000baseKR */ |
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ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv); |
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if (ret < 0) |
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return ret; |
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/* SR_AN_ADV2 */ |
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adv = 0; |
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if (phylink_test(xpcs->supported, 1000baseKX_Full)) |
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adv |= DW_C73_1000KX; |
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if (phylink_test(xpcs->supported, 10000baseKX4_Full)) |
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adv |= DW_C73_10000KX4; |
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if (phylink_test(xpcs->supported, 10000baseKR_Full)) |
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adv |= DW_C73_10000KR; |
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ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv); |
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if (ret < 0) |
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return ret; |
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/* SR_AN_ADV1 */ |
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adv = DW_C73_AN_ADV_SF; |
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if (phylink_test(xpcs->supported, Pause)) |
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adv |= DW_C73_PAUSE; |
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if (phylink_test(xpcs->supported, Asym_Pause)) |
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adv |= DW_C73_ASYM_PAUSE; |
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return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv); |
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} |
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static int xpcs_config_aneg(struct mdio_xpcs_args *xpcs) |
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{ |
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int ret; |
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ret = xpcs_config_aneg_c73(xpcs); |
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if (ret < 0) |
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return ret; |
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ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1); |
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if (ret < 0) |
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return ret; |
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ret |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART; |
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return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret); |
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} |
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static int xpcs_aneg_done(struct mdio_xpcs_args *xpcs, |
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struct phylink_link_state *state) |
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{ |
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int ret; |
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ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); |
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if (ret < 0) |
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return ret; |
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if (ret & MDIO_AN_STAT1_COMPLETE) { |
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ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1); |
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if (ret < 0) |
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return ret; |
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/* Check if Aneg outcome is valid */ |
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if (!(ret & DW_C73_AN_ADV_SF)) { |
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xpcs_config_aneg(xpcs); |
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return 0; |
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} |
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return 1; |
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} |
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return 0; |
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} |
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static int xpcs_read_lpa(struct mdio_xpcs_args *xpcs, |
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struct phylink_link_state *state) |
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{ |
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int ret; |
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ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); |
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if (ret < 0) |
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return ret; |
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if (!(ret & MDIO_AN_STAT1_LPABLE)) { |
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phylink_clear(state->lp_advertising, Autoneg); |
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return 0; |
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} |
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phylink_set(state->lp_advertising, Autoneg); |
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/* Clause 73 outcome */ |
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ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL3); |
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if (ret < 0) |
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return ret; |
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if (ret & DW_C73_2500KX) |
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phylink_set(state->lp_advertising, 2500baseX_Full); |
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ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL2); |
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if (ret < 0) |
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return ret; |
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if (ret & DW_C73_1000KX) |
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phylink_set(state->lp_advertising, 1000baseKX_Full); |
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if (ret & DW_C73_10000KX4) |
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phylink_set(state->lp_advertising, 10000baseKX4_Full); |
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if (ret & DW_C73_10000KR) |
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phylink_set(state->lp_advertising, 10000baseKR_Full); |
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ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1); |
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if (ret < 0) |
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return ret; |
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if (ret & DW_C73_PAUSE) |
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phylink_set(state->lp_advertising, Pause); |
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if (ret & DW_C73_ASYM_PAUSE) |
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phylink_set(state->lp_advertising, Asym_Pause); |
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linkmode_and(state->lp_advertising, state->lp_advertising, |
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state->advertising); |
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return 0; |
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} |
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static void xpcs_resolve_lpa(struct mdio_xpcs_args *xpcs, |
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struct phylink_link_state *state) |
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{ |
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int max_speed = xpcs_get_max_usxgmii_speed(state->lp_advertising); |
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state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX; |
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state->speed = max_speed; |
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state->duplex = DUPLEX_FULL; |
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} |
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static int xpcs_get_max_xlgmii_speed(struct mdio_xpcs_args *xpcs, |
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struct phylink_link_state *state) |
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{ |
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unsigned long *adv = state->advertising; |
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int speed = SPEED_UNKNOWN; |
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int bit; |
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for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) { |
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int new_speed = SPEED_UNKNOWN; |
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|
|
switch (bit) { |
|
case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: |
|
case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: |
|
case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: |
|
new_speed = SPEED_25000; |
|
break; |
|
case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: |
|
case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: |
|
case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: |
|
case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: |
|
new_speed = SPEED_40000; |
|
break; |
|
case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT: |
|
case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT: |
|
case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT: |
|
case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: |
|
case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: |
|
case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: |
|
case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: |
|
case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT: |
|
new_speed = SPEED_50000; |
|
break; |
|
case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT: |
|
new_speed = SPEED_100000; |
|
break; |
|
default: |
|
continue; |
|
} |
|
|
|
if (new_speed > speed) |
|
speed = new_speed; |
|
} |
|
|
|
return speed; |
|
} |
|
|
|
static void xpcs_resolve_pma(struct mdio_xpcs_args *xpcs, |
|
struct phylink_link_state *state) |
|
{ |
|
state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX; |
|
state->duplex = DUPLEX_FULL; |
|
|
|
switch (state->interface) { |
|
case PHY_INTERFACE_MODE_10GKR: |
|
state->speed = SPEED_10000; |
|
break; |
|
case PHY_INTERFACE_MODE_XLGMII: |
|
state->speed = xpcs_get_max_xlgmii_speed(xpcs, state); |
|
break; |
|
default: |
|
state->speed = SPEED_UNKNOWN; |
|
break; |
|
} |
|
} |
|
|
|
static int xpcs_validate(struct mdio_xpcs_args *xpcs, |
|
unsigned long *supported, |
|
struct phylink_link_state *state) |
|
{ |
|
linkmode_and(supported, supported, xpcs->supported); |
|
linkmode_and(state->advertising, state->advertising, xpcs->supported); |
|
return 0; |
|
} |
|
|
|
static int xpcs_config(struct mdio_xpcs_args *xpcs, |
|
const struct phylink_link_state *state) |
|
{ |
|
int ret; |
|
|
|
if (state->an_enabled) { |
|
ret = xpcs_config_aneg(xpcs); |
|
if (ret) |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int xpcs_get_state(struct mdio_xpcs_args *xpcs, |
|
struct phylink_link_state *state) |
|
{ |
|
int ret; |
|
|
|
/* Link needs to be read first ... */ |
|
state->link = xpcs_read_link(xpcs, state->an_enabled) > 0 ? 1 : 0; |
|
|
|
/* ... and then we check the faults. */ |
|
ret = xpcs_read_fault(xpcs, state); |
|
if (ret) { |
|
ret = xpcs_soft_reset(xpcs, MDIO_MMD_PCS); |
|
if (ret) |
|
return ret; |
|
|
|
state->link = 0; |
|
|
|
return xpcs_config(xpcs, state); |
|
} |
|
|
|
if (state->an_enabled && xpcs_aneg_done(xpcs, state)) { |
|
state->an_complete = true; |
|
xpcs_read_lpa(xpcs, state); |
|
xpcs_resolve_lpa(xpcs, state); |
|
} else if (state->an_enabled) { |
|
state->link = 0; |
|
} else if (state->link) { |
|
xpcs_resolve_pma(xpcs, state); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int xpcs_link_up(struct mdio_xpcs_args *xpcs, int speed, |
|
phy_interface_t interface) |
|
{ |
|
if (interface == PHY_INTERFACE_MODE_USXGMII) |
|
return xpcs_config_usxgmii(xpcs, speed); |
|
|
|
return 0; |
|
} |
|
|
|
static u32 xpcs_get_id(struct mdio_xpcs_args *xpcs) |
|
{ |
|
int ret; |
|
u32 id; |
|
|
|
ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1); |
|
if (ret < 0) |
|
return 0xffffffff; |
|
|
|
id = ret << 16; |
|
|
|
ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2); |
|
if (ret < 0) |
|
return 0xffffffff; |
|
|
|
return id | ret; |
|
} |
|
|
|
static bool xpcs_check_features(struct mdio_xpcs_args *xpcs, |
|
struct xpcs_id *match, |
|
phy_interface_t interface) |
|
{ |
|
int i; |
|
|
|
for (i = 0; match->interface[i] != PHY_INTERFACE_MODE_MAX; i++) { |
|
if (match->interface[i] == interface) |
|
break; |
|
} |
|
|
|
if (match->interface[i] == PHY_INTERFACE_MODE_MAX) |
|
return false; |
|
|
|
for (i = 0; match->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) |
|
set_bit(match->supported[i], xpcs->supported); |
|
|
|
return true; |
|
} |
|
|
|
static int xpcs_probe(struct mdio_xpcs_args *xpcs, phy_interface_t interface) |
|
{ |
|
u32 xpcs_id = xpcs_get_id(xpcs); |
|
struct xpcs_id *match = NULL; |
|
int i; |
|
|
|
for (i = 0; i < ARRAY_SIZE(xpcs_id_list); i++) { |
|
struct xpcs_id *entry = &xpcs_id_list[i]; |
|
|
|
if ((xpcs_id & entry->mask) == entry->id) { |
|
match = entry; |
|
|
|
if (xpcs_check_features(xpcs, match, interface)) |
|
return xpcs_soft_reset(xpcs, MDIO_MMD_PCS); |
|
} |
|
} |
|
|
|
return -ENODEV; |
|
} |
|
|
|
static struct mdio_xpcs_ops xpcs_ops = { |
|
.validate = xpcs_validate, |
|
.config = xpcs_config, |
|
.get_state = xpcs_get_state, |
|
.link_up = xpcs_link_up, |
|
.probe = xpcs_probe, |
|
}; |
|
|
|
struct mdio_xpcs_ops *mdio_xpcs_get_ops(void) |
|
{ |
|
return &xpcs_ops; |
|
} |
|
EXPORT_SYMBOL_GPL(mdio_xpcs_get_ops); |
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|