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533 lines
13 KiB
533 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2003-2020, Intel Corporation. All rights reserved. |
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* Intel Management Engine Interface (Intel MEI) Linux driver |
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*/ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/device.h> |
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#include <linux/errno.h> |
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#include <linux/types.h> |
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#include <linux/pci.h> |
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#include <linux/sched.h> |
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#include <linux/interrupt.h> |
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#include <linux/pm_domain.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/mei.h> |
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#include "mei_dev.h" |
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#include "client.h" |
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#include "hw-me-regs.h" |
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#include "hw-me.h" |
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/* mei_pci_tbl - PCI Device ID Table */ |
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static const struct pci_device_id mei_me_pci_tbl[] = { |
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{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)}, |
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{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)}, |
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/* required last entry */ |
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{0, } |
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}; |
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MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); |
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#ifdef CONFIG_PM |
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static inline void mei_me_set_pm_domain(struct mei_device *dev); |
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static inline void mei_me_unset_pm_domain(struct mei_device *dev); |
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#else |
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static inline void mei_me_set_pm_domain(struct mei_device *dev) {} |
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static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} |
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#endif /* CONFIG_PM */ |
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static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val) |
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{ |
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struct pci_dev *pdev = to_pci_dev(dev->dev); |
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return pci_read_config_dword(pdev, where, val); |
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} |
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/** |
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* mei_me_quirk_probe - probe for devices that doesn't valid ME interface |
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* |
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* @pdev: PCI device structure |
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* @cfg: per generation config |
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* |
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* Return: true if ME Interface is valid, false otherwise |
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*/ |
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static bool mei_me_quirk_probe(struct pci_dev *pdev, |
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const struct mei_cfg *cfg) |
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{ |
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if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { |
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dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); |
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return false; |
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} |
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return true; |
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} |
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/** |
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* mei_me_probe - Device Initialization Routine |
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* |
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* @pdev: PCI device structure |
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* @ent: entry in kcs_pci_tbl |
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* |
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* Return: 0 on success, <0 on failure. |
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*/ |
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static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
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{ |
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const struct mei_cfg *cfg; |
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struct mei_device *dev; |
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struct mei_me_hw *hw; |
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unsigned int irqflags; |
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int err; |
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cfg = mei_me_get_cfg(ent->driver_data); |
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if (!cfg) |
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return -ENODEV; |
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if (!mei_me_quirk_probe(pdev, cfg)) |
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return -ENODEV; |
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/* enable pci dev */ |
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err = pcim_enable_device(pdev); |
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if (err) { |
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dev_err(&pdev->dev, "failed to enable pci device.\n"); |
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goto end; |
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} |
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/* set PCI host mastering */ |
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pci_set_master(pdev); |
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/* pci request regions and mapping IO device memory for mei driver */ |
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err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); |
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if (err) { |
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dev_err(&pdev->dev, "failed to get pci regions.\n"); |
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goto end; |
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} |
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if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) || |
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dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { |
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err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
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if (err) |
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err = dma_set_coherent_mask(&pdev->dev, |
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DMA_BIT_MASK(32)); |
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} |
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if (err) { |
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dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); |
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goto end; |
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} |
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/* allocates and initializes the mei dev structure */ |
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dev = mei_me_dev_init(&pdev->dev, cfg); |
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if (!dev) { |
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err = -ENOMEM; |
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goto end; |
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} |
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hw = to_me_hw(dev); |
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hw->mem_addr = pcim_iomap_table(pdev)[0]; |
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hw->read_fws = mei_me_read_fws; |
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pci_enable_msi(pdev); |
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hw->irq = pdev->irq; |
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/* request and enable interrupt */ |
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irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; |
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err = request_threaded_irq(pdev->irq, |
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mei_me_irq_quick_handler, |
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mei_me_irq_thread_handler, |
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irqflags, KBUILD_MODNAME, dev); |
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if (err) { |
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dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", |
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pdev->irq); |
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goto end; |
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} |
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if (mei_start(dev)) { |
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dev_err(&pdev->dev, "init hw failure.\n"); |
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err = -ENODEV; |
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goto release_irq; |
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} |
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pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); |
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pm_runtime_use_autosuspend(&pdev->dev); |
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err = mei_register(dev, &pdev->dev); |
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if (err) |
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goto stop; |
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pci_set_drvdata(pdev, dev); |
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/* |
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* MEI requires to resume from runtime suspend mode |
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* in order to perform link reset flow upon system suspend. |
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*/ |
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dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); |
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/* |
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* ME maps runtime suspend/resume to D0i states, |
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* hence we need to go around native PCI runtime service which |
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* eventually brings the device into D3cold/hot state, |
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* but the mei device cannot wake up from D3 unlike from D0i3. |
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* To get around the PCI device native runtime pm, |
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* ME uses runtime pm domain handlers which take precedence |
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* over the driver's pm handlers. |
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*/ |
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mei_me_set_pm_domain(dev); |
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if (mei_pg_is_enabled(dev)) { |
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pm_runtime_put_noidle(&pdev->dev); |
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if (hw->d0i3_supported) |
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pm_runtime_allow(&pdev->dev); |
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} |
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dev_dbg(&pdev->dev, "initialization successful.\n"); |
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return 0; |
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stop: |
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mei_stop(dev); |
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release_irq: |
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mei_cancel_work(dev); |
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mei_disable_interrupts(dev); |
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free_irq(pdev->irq, dev); |
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end: |
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dev_err(&pdev->dev, "initialization failed.\n"); |
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return err; |
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} |
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/** |
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* mei_me_shutdown - Device Removal Routine |
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* |
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* @pdev: PCI device structure |
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* |
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* mei_me_shutdown is called from the reboot notifier |
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* it's a simplified version of remove so we go down |
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* faster. |
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*/ |
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static void mei_me_shutdown(struct pci_dev *pdev) |
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{ |
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struct mei_device *dev; |
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dev = pci_get_drvdata(pdev); |
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if (!dev) |
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return; |
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dev_dbg(&pdev->dev, "shutdown\n"); |
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mei_stop(dev); |
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mei_me_unset_pm_domain(dev); |
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mei_disable_interrupts(dev); |
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free_irq(pdev->irq, dev); |
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} |
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/** |
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* mei_me_remove - Device Removal Routine |
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* |
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* @pdev: PCI device structure |
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* |
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* mei_me_remove is called by the PCI subsystem to alert the driver |
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* that it should release a PCI device. |
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*/ |
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static void mei_me_remove(struct pci_dev *pdev) |
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{ |
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struct mei_device *dev; |
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dev = pci_get_drvdata(pdev); |
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if (!dev) |
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return; |
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if (mei_pg_is_enabled(dev)) |
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pm_runtime_get_noresume(&pdev->dev); |
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dev_dbg(&pdev->dev, "stop\n"); |
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mei_stop(dev); |
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mei_me_unset_pm_domain(dev); |
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mei_disable_interrupts(dev); |
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free_irq(pdev->irq, dev); |
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mei_deregister(dev); |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int mei_me_pci_suspend(struct device *device) |
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{ |
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struct pci_dev *pdev = to_pci_dev(device); |
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struct mei_device *dev = pci_get_drvdata(pdev); |
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if (!dev) |
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return -ENODEV; |
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dev_dbg(&pdev->dev, "suspend\n"); |
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mei_stop(dev); |
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mei_disable_interrupts(dev); |
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free_irq(pdev->irq, dev); |
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pci_disable_msi(pdev); |
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return 0; |
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} |
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static int mei_me_pci_resume(struct device *device) |
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{ |
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struct pci_dev *pdev = to_pci_dev(device); |
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struct mei_device *dev; |
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unsigned int irqflags; |
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int err; |
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dev = pci_get_drvdata(pdev); |
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if (!dev) |
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return -ENODEV; |
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pci_enable_msi(pdev); |
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irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; |
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/* request and enable interrupt */ |
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err = request_threaded_irq(pdev->irq, |
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mei_me_irq_quick_handler, |
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mei_me_irq_thread_handler, |
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irqflags, KBUILD_MODNAME, dev); |
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if (err) { |
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dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", |
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pdev->irq); |
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return err; |
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} |
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err = mei_restart(dev); |
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if (err) |
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return err; |
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/* Start timer if stopped in suspend */ |
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schedule_delayed_work(&dev->timer_work, HZ); |
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return 0; |
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} |
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#endif /* CONFIG_PM_SLEEP */ |
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#ifdef CONFIG_PM |
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static int mei_me_pm_runtime_idle(struct device *device) |
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{ |
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struct mei_device *dev; |
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dev_dbg(device, "rpm: me: runtime_idle\n"); |
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dev = dev_get_drvdata(device); |
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if (!dev) |
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return -ENODEV; |
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if (mei_write_is_idle(dev)) |
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pm_runtime_autosuspend(device); |
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return -EBUSY; |
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} |
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static int mei_me_pm_runtime_suspend(struct device *device) |
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{ |
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struct mei_device *dev; |
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int ret; |
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dev_dbg(device, "rpm: me: runtime suspend\n"); |
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dev = dev_get_drvdata(device); |
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if (!dev) |
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return -ENODEV; |
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mutex_lock(&dev->device_lock); |
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if (mei_write_is_idle(dev)) |
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ret = mei_me_pg_enter_sync(dev); |
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else |
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ret = -EAGAIN; |
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mutex_unlock(&dev->device_lock); |
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dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret); |
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if (ret && ret != -EAGAIN) |
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schedule_work(&dev->reset_work); |
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return ret; |
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} |
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static int mei_me_pm_runtime_resume(struct device *device) |
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{ |
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struct mei_device *dev; |
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int ret; |
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dev_dbg(device, "rpm: me: runtime resume\n"); |
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dev = dev_get_drvdata(device); |
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if (!dev) |
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return -ENODEV; |
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mutex_lock(&dev->device_lock); |
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ret = mei_me_pg_exit_sync(dev); |
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mutex_unlock(&dev->device_lock); |
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dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret); |
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if (ret) |
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schedule_work(&dev->reset_work); |
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return ret; |
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} |
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/** |
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* mei_me_set_pm_domain - fill and set pm domain structure for device |
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* |
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* @dev: mei_device |
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*/ |
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static inline void mei_me_set_pm_domain(struct mei_device *dev) |
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{ |
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struct pci_dev *pdev = to_pci_dev(dev->dev); |
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if (pdev->dev.bus && pdev->dev.bus->pm) { |
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dev->pg_domain.ops = *pdev->dev.bus->pm; |
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dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; |
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dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; |
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dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; |
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dev_pm_domain_set(&pdev->dev, &dev->pg_domain); |
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} |
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} |
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/** |
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* mei_me_unset_pm_domain - clean pm domain structure for device |
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* |
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* @dev: mei_device |
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*/ |
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static inline void mei_me_unset_pm_domain(struct mei_device *dev) |
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{ |
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/* stop using pm callbacks if any */ |
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dev_pm_domain_set(dev->dev, NULL); |
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} |
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|
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static const struct dev_pm_ops mei_me_pm_ops = { |
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SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, |
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mei_me_pci_resume) |
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SET_RUNTIME_PM_OPS( |
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mei_me_pm_runtime_suspend, |
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mei_me_pm_runtime_resume, |
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mei_me_pm_runtime_idle) |
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}; |
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|
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#define MEI_ME_PM_OPS (&mei_me_pm_ops) |
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#else |
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#define MEI_ME_PM_OPS NULL |
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#endif /* CONFIG_PM */ |
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/* |
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* PCI driver structure |
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*/ |
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static struct pci_driver mei_me_driver = { |
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.name = KBUILD_MODNAME, |
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.id_table = mei_me_pci_tbl, |
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.probe = mei_me_probe, |
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.remove = mei_me_remove, |
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.shutdown = mei_me_shutdown, |
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.driver.pm = MEI_ME_PM_OPS, |
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.driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, |
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}; |
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|
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module_pci_driver(mei_me_driver); |
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|
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MODULE_AUTHOR("Intel Corporation"); |
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MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); |
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MODULE_LICENSE("GPL v2");
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