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855 lines
21 KiB
855 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Toshiba TC6393XB SoC support |
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* |
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* Copyright(c) 2005-2006 Chris Humbert |
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* Copyright(c) 2005 Dirk Opfer |
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* Copyright(c) 2005 Ian Molton <[email protected]> |
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* Copyright(c) 2007 Dmitry Baryshkov |
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* |
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* Based on code written by Sharp/Lineo for 2.4 kernels |
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* Based on locomo.c |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/platform_device.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/mfd/core.h> |
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#include <linux/mfd/tmio.h> |
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#include <linux/mfd/tc6393xb.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/slab.h> |
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#define SCR_REVID 0x08 /* b Revision ID */ |
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#define SCR_ISR 0x50 /* b Interrupt Status */ |
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#define SCR_IMR 0x52 /* b Interrupt Mask */ |
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#define SCR_IRR 0x54 /* b Interrupt Routing */ |
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#define SCR_GPER 0x60 /* w GP Enable */ |
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#define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */ |
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#define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */ |
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#define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */ |
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#define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */ |
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#define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */ |
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#define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */ |
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#define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */ |
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#define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */ |
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#define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */ |
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#define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */ |
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#define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */ |
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#define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */ |
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#define SCR_CCR 0x98 /* w Clock Control */ |
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#define SCR_PLL2CR 0x9a /* w PLL2 Control */ |
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#define SCR_PLL1CR 0x9c /* l PLL1 Control */ |
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#define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */ |
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#define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */ |
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#define SCR_FER 0xe0 /* b Function Enable */ |
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#define SCR_MCR 0xe4 /* w Mode Control */ |
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#define SCR_CONFIG 0xfc /* b Configuration Control */ |
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#define SCR_DEBUG 0xff /* b Debug */ |
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#define SCR_CCR_CK32K BIT(0) |
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#define SCR_CCR_USBCK BIT(1) |
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#define SCR_CCR_UNK1 BIT(4) |
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#define SCR_CCR_MCLK_MASK (7 << 8) |
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#define SCR_CCR_MCLK_OFF (0 << 8) |
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#define SCR_CCR_MCLK_12 (1 << 8) |
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#define SCR_CCR_MCLK_24 (2 << 8) |
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#define SCR_CCR_MCLK_48 (3 << 8) |
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#define SCR_CCR_HCLK_MASK (3 << 12) |
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#define SCR_CCR_HCLK_24 (0 << 12) |
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#define SCR_CCR_HCLK_48 (1 << 12) |
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#define SCR_FER_USBEN BIT(0) /* USB host enable */ |
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#define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */ |
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#define SCR_FER_SLCDEN BIT(2) /* SLCD enable */ |
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#define SCR_MCR_RDY_MASK (3 << 0) |
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#define SCR_MCR_RDY_OPENDRAIN (0 << 0) |
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#define SCR_MCR_RDY_TRISTATE (1 << 0) |
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#define SCR_MCR_RDY_PUSHPULL (2 << 0) |
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#define SCR_MCR_RDY_UNK BIT(2) |
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#define SCR_MCR_RDY_EN BIT(3) |
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#define SCR_MCR_INT_MASK (3 << 4) |
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#define SCR_MCR_INT_OPENDRAIN (0 << 4) |
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#define SCR_MCR_INT_TRISTATE (1 << 4) |
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#define SCR_MCR_INT_PUSHPULL (2 << 4) |
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#define SCR_MCR_INT_UNK BIT(6) |
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#define SCR_MCR_INT_EN BIT(7) |
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/* bits 8 - 16 are unknown */ |
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#define TC_GPIO_BIT(i) (1 << (i & 0x7)) |
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/*--------------------------------------------------------------------------*/ |
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struct tc6393xb { |
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void __iomem *scr; |
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struct gpio_chip gpio; |
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struct clk *clk; /* 3,6 Mhz */ |
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raw_spinlock_t lock; /* protects RMW cycles */ |
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struct { |
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u8 fer; |
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u16 ccr; |
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u8 gpi_bcr[3]; |
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u8 gpo_dsr[3]; |
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u8 gpo_doecr[3]; |
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} suspend_state; |
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struct resource rscr; |
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struct resource *iomem; |
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int irq; |
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int irq_base; |
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}; |
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enum { |
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TC6393XB_CELL_NAND, |
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TC6393XB_CELL_MMC, |
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TC6393XB_CELL_OHCI, |
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TC6393XB_CELL_FB, |
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}; |
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/*--------------------------------------------------------------------------*/ |
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static int tc6393xb_nand_enable(struct platform_device *nand) |
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{ |
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struct tc6393xb *tc6393xb = dev_get_drvdata(nand->dev.parent); |
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unsigned long flags; |
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raw_spin_lock_irqsave(&tc6393xb->lock, flags); |
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/* SMD buffer on */ |
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dev_dbg(nand->dev.parent, "SMD buffer on\n"); |
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tmio_iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1)); |
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raw_spin_unlock_irqrestore(&tc6393xb->lock, flags); |
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return 0; |
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} |
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static const struct resource tc6393xb_nand_resources[] = { |
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{ |
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.start = 0x1000, |
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.end = 0x1007, |
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.flags = IORESOURCE_MEM, |
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}, |
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{ |
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.start = 0x0100, |
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.end = 0x01ff, |
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.flags = IORESOURCE_MEM, |
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}, |
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{ |
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.start = IRQ_TC6393_NAND, |
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.end = IRQ_TC6393_NAND, |
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.flags = IORESOURCE_IRQ, |
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}, |
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}; |
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static const struct resource tc6393xb_mmc_resources[] = { |
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{ |
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.start = 0x800, |
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.end = 0x9ff, |
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.flags = IORESOURCE_MEM, |
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}, |
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{ |
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.start = IRQ_TC6393_MMC, |
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.end = IRQ_TC6393_MMC, |
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.flags = IORESOURCE_IRQ, |
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}, |
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}; |
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static const struct resource tc6393xb_ohci_resources[] = { |
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{ |
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.start = 0x3000, |
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.end = 0x31ff, |
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.flags = IORESOURCE_MEM, |
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}, |
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{ |
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.start = 0x0300, |
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.end = 0x03ff, |
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.flags = IORESOURCE_MEM, |
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}, |
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{ |
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.start = 0x010000, |
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.end = 0x017fff, |
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.flags = IORESOURCE_MEM, |
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}, |
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{ |
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.start = 0x018000, |
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.end = 0x01ffff, |
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.flags = IORESOURCE_MEM, |
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}, |
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{ |
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.start = IRQ_TC6393_OHCI, |
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.end = IRQ_TC6393_OHCI, |
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.flags = IORESOURCE_IRQ, |
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}, |
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}; |
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static const struct resource tc6393xb_fb_resources[] = { |
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{ |
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.start = 0x5000, |
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.end = 0x51ff, |
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.flags = IORESOURCE_MEM, |
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}, |
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{ |
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.start = 0x0500, |
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.end = 0x05ff, |
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.flags = IORESOURCE_MEM, |
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}, |
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{ |
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.start = 0x100000, |
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.end = 0x1fffff, |
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.flags = IORESOURCE_MEM, |
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}, |
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{ |
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.start = IRQ_TC6393_FB, |
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.end = IRQ_TC6393_FB, |
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.flags = IORESOURCE_IRQ, |
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}, |
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}; |
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static int tc6393xb_ohci_enable(struct platform_device *dev) |
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{ |
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struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent); |
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unsigned long flags; |
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u16 ccr; |
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u8 fer; |
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raw_spin_lock_irqsave(&tc6393xb->lock, flags); |
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ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR); |
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ccr |= SCR_CCR_USBCK; |
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tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR); |
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fer = tmio_ioread8(tc6393xb->scr + SCR_FER); |
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fer |= SCR_FER_USBEN; |
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tmio_iowrite8(fer, tc6393xb->scr + SCR_FER); |
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raw_spin_unlock_irqrestore(&tc6393xb->lock, flags); |
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return 0; |
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} |
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static int tc6393xb_ohci_disable(struct platform_device *dev) |
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{ |
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struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent); |
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unsigned long flags; |
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u16 ccr; |
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u8 fer; |
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raw_spin_lock_irqsave(&tc6393xb->lock, flags); |
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fer = tmio_ioread8(tc6393xb->scr + SCR_FER); |
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fer &= ~SCR_FER_USBEN; |
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tmio_iowrite8(fer, tc6393xb->scr + SCR_FER); |
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ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR); |
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ccr &= ~SCR_CCR_USBCK; |
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tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR); |
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raw_spin_unlock_irqrestore(&tc6393xb->lock, flags); |
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return 0; |
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} |
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static int tc6393xb_ohci_suspend(struct platform_device *dev) |
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{ |
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struct tc6393xb_platform_data *tcpd = dev_get_platdata(dev->dev.parent); |
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/* We can't properly store/restore OHCI state, so fail here */ |
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if (tcpd->resume_restore) |
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return -EBUSY; |
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return tc6393xb_ohci_disable(dev); |
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} |
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static int tc6393xb_fb_enable(struct platform_device *dev) |
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{ |
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struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent); |
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unsigned long flags; |
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u16 ccr; |
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raw_spin_lock_irqsave(&tc6393xb->lock, flags); |
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ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR); |
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ccr &= ~SCR_CCR_MCLK_MASK; |
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ccr |= SCR_CCR_MCLK_48; |
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tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR); |
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raw_spin_unlock_irqrestore(&tc6393xb->lock, flags); |
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return 0; |
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} |
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static int tc6393xb_fb_disable(struct platform_device *dev) |
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{ |
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struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent); |
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unsigned long flags; |
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u16 ccr; |
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raw_spin_lock_irqsave(&tc6393xb->lock, flags); |
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ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR); |
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ccr &= ~SCR_CCR_MCLK_MASK; |
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ccr |= SCR_CCR_MCLK_OFF; |
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tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR); |
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raw_spin_unlock_irqrestore(&tc6393xb->lock, flags); |
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return 0; |
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} |
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int tc6393xb_lcd_set_power(struct platform_device *fb, bool on) |
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{ |
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struct tc6393xb *tc6393xb = dev_get_drvdata(fb->dev.parent); |
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u8 fer; |
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unsigned long flags; |
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raw_spin_lock_irqsave(&tc6393xb->lock, flags); |
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fer = ioread8(tc6393xb->scr + SCR_FER); |
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if (on) |
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fer |= SCR_FER_SLCDEN; |
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else |
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fer &= ~SCR_FER_SLCDEN; |
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iowrite8(fer, tc6393xb->scr + SCR_FER); |
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raw_spin_unlock_irqrestore(&tc6393xb->lock, flags); |
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return 0; |
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} |
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EXPORT_SYMBOL(tc6393xb_lcd_set_power); |
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int tc6393xb_lcd_mode(struct platform_device *fb, |
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const struct fb_videomode *mode) { |
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struct tc6393xb *tc6393xb = dev_get_drvdata(fb->dev.parent); |
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unsigned long flags; |
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raw_spin_lock_irqsave(&tc6393xb->lock, flags); |
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iowrite16(mode->pixclock, tc6393xb->scr + SCR_PLL1CR + 0); |
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iowrite16(mode->pixclock >> 16, tc6393xb->scr + SCR_PLL1CR + 2); |
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raw_spin_unlock_irqrestore(&tc6393xb->lock, flags); |
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return 0; |
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} |
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EXPORT_SYMBOL(tc6393xb_lcd_mode); |
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static int tc6393xb_mmc_enable(struct platform_device *mmc) |
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{ |
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struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent); |
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tmio_core_mmc_enable(tc6393xb->scr + 0x200, 0, |
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tc6393xb_mmc_resources[0].start & 0xfffe); |
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return 0; |
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} |
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static int tc6393xb_mmc_resume(struct platform_device *mmc) |
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{ |
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struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent); |
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tmio_core_mmc_resume(tc6393xb->scr + 0x200, 0, |
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tc6393xb_mmc_resources[0].start & 0xfffe); |
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return 0; |
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} |
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static void tc6393xb_mmc_pwr(struct platform_device *mmc, int state) |
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{ |
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struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent); |
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tmio_core_mmc_pwr(tc6393xb->scr + 0x200, 0, state); |
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} |
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static void tc6393xb_mmc_clk_div(struct platform_device *mmc, int state) |
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{ |
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struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent); |
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tmio_core_mmc_clk_div(tc6393xb->scr + 0x200, 0, state); |
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} |
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static struct tmio_mmc_data tc6393xb_mmc_data = { |
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.hclk = 24000000, |
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.set_pwr = tc6393xb_mmc_pwr, |
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.set_clk_div = tc6393xb_mmc_clk_div, |
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}; |
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static struct mfd_cell tc6393xb_cells[] = { |
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[TC6393XB_CELL_NAND] = { |
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.name = "tmio-nand", |
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.enable = tc6393xb_nand_enable, |
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.num_resources = ARRAY_SIZE(tc6393xb_nand_resources), |
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.resources = tc6393xb_nand_resources, |
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}, |
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[TC6393XB_CELL_MMC] = { |
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.name = "tmio-mmc", |
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.enable = tc6393xb_mmc_enable, |
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.resume = tc6393xb_mmc_resume, |
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.platform_data = &tc6393xb_mmc_data, |
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.pdata_size = sizeof(tc6393xb_mmc_data), |
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.num_resources = ARRAY_SIZE(tc6393xb_mmc_resources), |
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.resources = tc6393xb_mmc_resources, |
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}, |
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[TC6393XB_CELL_OHCI] = { |
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.name = "tmio-ohci", |
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.num_resources = ARRAY_SIZE(tc6393xb_ohci_resources), |
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.resources = tc6393xb_ohci_resources, |
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.enable = tc6393xb_ohci_enable, |
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.suspend = tc6393xb_ohci_suspend, |
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.resume = tc6393xb_ohci_enable, |
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.disable = tc6393xb_ohci_disable, |
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}, |
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[TC6393XB_CELL_FB] = { |
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.name = "tmio-fb", |
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.num_resources = ARRAY_SIZE(tc6393xb_fb_resources), |
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.resources = tc6393xb_fb_resources, |
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.enable = tc6393xb_fb_enable, |
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.suspend = tc6393xb_fb_disable, |
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.resume = tc6393xb_fb_enable, |
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.disable = tc6393xb_fb_disable, |
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}, |
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}; |
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/*--------------------------------------------------------------------------*/ |
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static int tc6393xb_gpio_get(struct gpio_chip *chip, |
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unsigned offset) |
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{ |
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struct tc6393xb *tc6393xb = gpiochip_get_data(chip); |
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/* XXX: does dsr also represent inputs? */ |
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return !!(tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8)) |
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& TC_GPIO_BIT(offset)); |
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} |
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static void __tc6393xb_gpio_set(struct gpio_chip *chip, |
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unsigned offset, int value) |
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{ |
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struct tc6393xb *tc6393xb = gpiochip_get_data(chip); |
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u8 dsr; |
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dsr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8)); |
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if (value) |
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dsr |= TC_GPIO_BIT(offset); |
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else |
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dsr &= ~TC_GPIO_BIT(offset); |
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tmio_iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8)); |
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} |
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static void tc6393xb_gpio_set(struct gpio_chip *chip, |
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unsigned offset, int value) |
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{ |
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struct tc6393xb *tc6393xb = gpiochip_get_data(chip); |
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unsigned long flags; |
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raw_spin_lock_irqsave(&tc6393xb->lock, flags); |
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__tc6393xb_gpio_set(chip, offset, value); |
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raw_spin_unlock_irqrestore(&tc6393xb->lock, flags); |
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} |
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static int tc6393xb_gpio_direction_input(struct gpio_chip *chip, |
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unsigned offset) |
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{ |
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struct tc6393xb *tc6393xb = gpiochip_get_data(chip); |
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unsigned long flags; |
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u8 doecr; |
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raw_spin_lock_irqsave(&tc6393xb->lock, flags); |
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doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); |
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doecr &= ~TC_GPIO_BIT(offset); |
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tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); |
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raw_spin_unlock_irqrestore(&tc6393xb->lock, flags); |
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return 0; |
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} |
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static int tc6393xb_gpio_direction_output(struct gpio_chip *chip, |
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unsigned offset, int value) |
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{ |
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struct tc6393xb *tc6393xb = gpiochip_get_data(chip); |
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unsigned long flags; |
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u8 doecr; |
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raw_spin_lock_irqsave(&tc6393xb->lock, flags); |
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__tc6393xb_gpio_set(chip, offset, value); |
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doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); |
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doecr |= TC_GPIO_BIT(offset); |
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tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); |
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raw_spin_unlock_irqrestore(&tc6393xb->lock, flags); |
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return 0; |
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} |
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static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base) |
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{ |
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tc6393xb->gpio.label = "tc6393xb"; |
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tc6393xb->gpio.base = gpio_base; |
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tc6393xb->gpio.ngpio = 16; |
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tc6393xb->gpio.set = tc6393xb_gpio_set; |
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tc6393xb->gpio.get = tc6393xb_gpio_get; |
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tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input; |
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tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output; |
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return gpiochip_add_data(&tc6393xb->gpio, tc6393xb); |
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} |
|
|
|
/*--------------------------------------------------------------------------*/ |
|
|
|
static void tc6393xb_irq(struct irq_desc *desc) |
|
{ |
|
struct tc6393xb *tc6393xb = irq_desc_get_handler_data(desc); |
|
unsigned int isr; |
|
unsigned int i, irq_base; |
|
|
|
irq_base = tc6393xb->irq_base; |
|
|
|
while ((isr = tmio_ioread8(tc6393xb->scr + SCR_ISR) & |
|
~tmio_ioread8(tc6393xb->scr + SCR_IMR))) |
|
for (i = 0; i < TC6393XB_NR_IRQS; i++) { |
|
if (isr & (1 << i)) |
|
generic_handle_irq(irq_base + i); |
|
} |
|
} |
|
|
|
static void tc6393xb_irq_ack(struct irq_data *data) |
|
{ |
|
} |
|
|
|
static void tc6393xb_irq_mask(struct irq_data *data) |
|
{ |
|
struct tc6393xb *tc6393xb = irq_data_get_irq_chip_data(data); |
|
unsigned long flags; |
|
u8 imr; |
|
|
|
raw_spin_lock_irqsave(&tc6393xb->lock, flags); |
|
imr = tmio_ioread8(tc6393xb->scr + SCR_IMR); |
|
imr |= 1 << (data->irq - tc6393xb->irq_base); |
|
tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR); |
|
raw_spin_unlock_irqrestore(&tc6393xb->lock, flags); |
|
} |
|
|
|
static void tc6393xb_irq_unmask(struct irq_data *data) |
|
{ |
|
struct tc6393xb *tc6393xb = irq_data_get_irq_chip_data(data); |
|
unsigned long flags; |
|
u8 imr; |
|
|
|
raw_spin_lock_irqsave(&tc6393xb->lock, flags); |
|
imr = tmio_ioread8(tc6393xb->scr + SCR_IMR); |
|
imr &= ~(1 << (data->irq - tc6393xb->irq_base)); |
|
tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR); |
|
raw_spin_unlock_irqrestore(&tc6393xb->lock, flags); |
|
} |
|
|
|
static struct irq_chip tc6393xb_chip = { |
|
.name = "tc6393xb", |
|
.irq_ack = tc6393xb_irq_ack, |
|
.irq_mask = tc6393xb_irq_mask, |
|
.irq_unmask = tc6393xb_irq_unmask, |
|
}; |
|
|
|
static void tc6393xb_attach_irq(struct platform_device *dev) |
|
{ |
|
struct tc6393xb *tc6393xb = platform_get_drvdata(dev); |
|
unsigned int irq, irq_base; |
|
|
|
irq_base = tc6393xb->irq_base; |
|
|
|
for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) { |
|
irq_set_chip_and_handler(irq, &tc6393xb_chip, handle_edge_irq); |
|
irq_set_chip_data(irq, tc6393xb); |
|
irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); |
|
} |
|
|
|
irq_set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING); |
|
irq_set_chained_handler_and_data(tc6393xb->irq, tc6393xb_irq, |
|
tc6393xb); |
|
} |
|
|
|
static void tc6393xb_detach_irq(struct platform_device *dev) |
|
{ |
|
struct tc6393xb *tc6393xb = platform_get_drvdata(dev); |
|
unsigned int irq, irq_base; |
|
|
|
irq_set_chained_handler_and_data(tc6393xb->irq, NULL, NULL); |
|
|
|
irq_base = tc6393xb->irq_base; |
|
|
|
for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) { |
|
irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); |
|
irq_set_chip(irq, NULL); |
|
irq_set_chip_data(irq, NULL); |
|
} |
|
} |
|
|
|
/*--------------------------------------------------------------------------*/ |
|
|
|
static int tc6393xb_probe(struct platform_device *dev) |
|
{ |
|
struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev); |
|
struct tc6393xb *tc6393xb; |
|
struct resource *iomem, *rscr; |
|
int ret; |
|
|
|
iomem = platform_get_resource(dev, IORESOURCE_MEM, 0); |
|
if (!iomem) |
|
return -EINVAL; |
|
|
|
tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL); |
|
if (!tc6393xb) { |
|
ret = -ENOMEM; |
|
goto err_kzalloc; |
|
} |
|
|
|
raw_spin_lock_init(&tc6393xb->lock); |
|
|
|
platform_set_drvdata(dev, tc6393xb); |
|
|
|
ret = platform_get_irq(dev, 0); |
|
if (ret >= 0) |
|
tc6393xb->irq = ret; |
|
else |
|
goto err_noirq; |
|
|
|
tc6393xb->iomem = iomem; |
|
tc6393xb->irq_base = tcpd->irq_base; |
|
|
|
tc6393xb->clk = clk_get(&dev->dev, "CLK_CK3P6MI"); |
|
if (IS_ERR(tc6393xb->clk)) { |
|
ret = PTR_ERR(tc6393xb->clk); |
|
goto err_clk_get; |
|
} |
|
|
|
rscr = &tc6393xb->rscr; |
|
rscr->name = "tc6393xb-core"; |
|
rscr->start = iomem->start; |
|
rscr->end = iomem->start + 0xff; |
|
rscr->flags = IORESOURCE_MEM; |
|
|
|
ret = request_resource(iomem, rscr); |
|
if (ret) |
|
goto err_request_scr; |
|
|
|
tc6393xb->scr = ioremap(rscr->start, resource_size(rscr)); |
|
if (!tc6393xb->scr) { |
|
ret = -ENOMEM; |
|
goto err_ioremap; |
|
} |
|
|
|
ret = clk_prepare_enable(tc6393xb->clk); |
|
if (ret) |
|
goto err_clk_enable; |
|
|
|
ret = tcpd->enable(dev); |
|
if (ret) |
|
goto err_enable; |
|
|
|
iowrite8(0, tc6393xb->scr + SCR_FER); |
|
iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR); |
|
iowrite16(SCR_CCR_UNK1 | SCR_CCR_HCLK_48, |
|
tc6393xb->scr + SCR_CCR); |
|
iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN | |
|
SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN | |
|
BIT(15), tc6393xb->scr + SCR_MCR); |
|
iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER); |
|
iowrite8(0, tc6393xb->scr + SCR_IRR); |
|
iowrite8(0xbf, tc6393xb->scr + SCR_IMR); |
|
|
|
printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n", |
|
tmio_ioread8(tc6393xb->scr + SCR_REVID), |
|
(unsigned long) iomem->start, tc6393xb->irq); |
|
|
|
tc6393xb->gpio.base = -1; |
|
|
|
if (tcpd->gpio_base >= 0) { |
|
ret = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base); |
|
if (ret) |
|
goto err_gpio_add; |
|
} |
|
|
|
tc6393xb_attach_irq(dev); |
|
|
|
if (tcpd->setup) { |
|
ret = tcpd->setup(dev); |
|
if (ret) |
|
goto err_setup; |
|
} |
|
|
|
tc6393xb_cells[TC6393XB_CELL_NAND].platform_data = tcpd->nand_data; |
|
tc6393xb_cells[TC6393XB_CELL_NAND].pdata_size = |
|
sizeof(*tcpd->nand_data); |
|
tc6393xb_cells[TC6393XB_CELL_FB].platform_data = tcpd->fb_data; |
|
tc6393xb_cells[TC6393XB_CELL_FB].pdata_size = sizeof(*tcpd->fb_data); |
|
|
|
ret = mfd_add_devices(&dev->dev, dev->id, |
|
tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells), |
|
iomem, tcpd->irq_base, NULL); |
|
|
|
if (!ret) |
|
return 0; |
|
|
|
if (tcpd->teardown) |
|
tcpd->teardown(dev); |
|
|
|
err_setup: |
|
tc6393xb_detach_irq(dev); |
|
|
|
err_gpio_add: |
|
if (tc6393xb->gpio.base != -1) |
|
gpiochip_remove(&tc6393xb->gpio); |
|
tcpd->disable(dev); |
|
err_enable: |
|
clk_disable_unprepare(tc6393xb->clk); |
|
err_clk_enable: |
|
iounmap(tc6393xb->scr); |
|
err_ioremap: |
|
release_resource(&tc6393xb->rscr); |
|
err_request_scr: |
|
clk_put(tc6393xb->clk); |
|
err_noirq: |
|
err_clk_get: |
|
kfree(tc6393xb); |
|
err_kzalloc: |
|
return ret; |
|
} |
|
|
|
static int tc6393xb_remove(struct platform_device *dev) |
|
{ |
|
struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev); |
|
struct tc6393xb *tc6393xb = platform_get_drvdata(dev); |
|
int ret; |
|
|
|
mfd_remove_devices(&dev->dev); |
|
|
|
if (tcpd->teardown) |
|
tcpd->teardown(dev); |
|
|
|
tc6393xb_detach_irq(dev); |
|
|
|
if (tc6393xb->gpio.base != -1) |
|
gpiochip_remove(&tc6393xb->gpio); |
|
|
|
ret = tcpd->disable(dev); |
|
clk_disable_unprepare(tc6393xb->clk); |
|
iounmap(tc6393xb->scr); |
|
release_resource(&tc6393xb->rscr); |
|
clk_put(tc6393xb->clk); |
|
kfree(tc6393xb); |
|
|
|
return ret; |
|
} |
|
|
|
#ifdef CONFIG_PM |
|
static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state) |
|
{ |
|
struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev); |
|
struct tc6393xb *tc6393xb = platform_get_drvdata(dev); |
|
int i, ret; |
|
|
|
tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR); |
|
tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER); |
|
|
|
for (i = 0; i < 3; i++) { |
|
tc6393xb->suspend_state.gpo_dsr[i] = |
|
ioread8(tc6393xb->scr + SCR_GPO_DSR(i)); |
|
tc6393xb->suspend_state.gpo_doecr[i] = |
|
ioread8(tc6393xb->scr + SCR_GPO_DOECR(i)); |
|
tc6393xb->suspend_state.gpi_bcr[i] = |
|
ioread8(tc6393xb->scr + SCR_GPI_BCR(i)); |
|
} |
|
ret = tcpd->suspend(dev); |
|
clk_disable_unprepare(tc6393xb->clk); |
|
|
|
return ret; |
|
} |
|
|
|
static int tc6393xb_resume(struct platform_device *dev) |
|
{ |
|
struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev); |
|
struct tc6393xb *tc6393xb = platform_get_drvdata(dev); |
|
int ret; |
|
int i; |
|
|
|
ret = clk_prepare_enable(tc6393xb->clk); |
|
if (ret) |
|
return ret; |
|
|
|
ret = tcpd->resume(dev); |
|
if (ret) |
|
return ret; |
|
|
|
if (!tcpd->resume_restore) |
|
return 0; |
|
|
|
iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER); |
|
iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR); |
|
iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR); |
|
iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN | |
|
SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN | |
|
BIT(15), tc6393xb->scr + SCR_MCR); |
|
iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER); |
|
iowrite8(0, tc6393xb->scr + SCR_IRR); |
|
iowrite8(0xbf, tc6393xb->scr + SCR_IMR); |
|
|
|
for (i = 0; i < 3; i++) { |
|
iowrite8(tc6393xb->suspend_state.gpo_dsr[i], |
|
tc6393xb->scr + SCR_GPO_DSR(i)); |
|
iowrite8(tc6393xb->suspend_state.gpo_doecr[i], |
|
tc6393xb->scr + SCR_GPO_DOECR(i)); |
|
iowrite8(tc6393xb->suspend_state.gpi_bcr[i], |
|
tc6393xb->scr + SCR_GPI_BCR(i)); |
|
} |
|
|
|
return 0; |
|
} |
|
#else |
|
#define tc6393xb_suspend NULL |
|
#define tc6393xb_resume NULL |
|
#endif |
|
|
|
static struct platform_driver tc6393xb_driver = { |
|
.probe = tc6393xb_probe, |
|
.remove = tc6393xb_remove, |
|
.suspend = tc6393xb_suspend, |
|
.resume = tc6393xb_resume, |
|
|
|
.driver = { |
|
.name = "tc6393xb", |
|
}, |
|
}; |
|
|
|
static int __init tc6393xb_init(void) |
|
{ |
|
return platform_driver_register(&tc6393xb_driver); |
|
} |
|
|
|
static void __exit tc6393xb_exit(void) |
|
{ |
|
platform_driver_unregister(&tc6393xb_driver); |
|
} |
|
|
|
subsys_initcall(tc6393xb_init); |
|
module_exit(tc6393xb_exit); |
|
|
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer"); |
|
MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller"); |
|
MODULE_ALIAS("platform:tc6393xb"); |
|
|
|
|