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468 lines
12 KiB
468 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Driver for the Intel Broxton PMC |
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* |
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* (C) Copyright 2014 - 2020 Intel Corporation |
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* |
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* This driver is based on Intel SCU IPC driver (intel_scu_ipc.c) by |
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* Sreedhara DS <[email protected]> |
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* |
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* The PMC (Power Management Controller) running on the ARC processor |
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* communicates with another entity running in the IA (Intel Architecture) |
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* core through an IPC (Intel Processor Communications) mechanism which in |
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* turn sends messages between the IA and the PMC. |
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*/ |
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#include <linux/acpi.h> |
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#include <linux/delay.h> |
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#include <linux/errno.h> |
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#include <linux/interrupt.h> |
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#include <linux/io-64-nonatomic-lo-hi.h> |
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#include <linux/mfd/core.h> |
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#include <linux/mfd/intel_pmc_bxt.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/platform_data/itco_wdt.h> |
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#include <asm/intel_scu_ipc.h> |
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/* Residency with clock rate at 19.2MHz to usecs */ |
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#define S0IX_RESIDENCY_IN_USECS(d, s) \ |
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({ \ |
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u64 result = 10ull * ((d) + (s)); \ |
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do_div(result, 192); \ |
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result; \ |
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}) |
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/* Resources exported from IFWI */ |
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#define PLAT_RESOURCE_IPC_INDEX 0 |
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#define PLAT_RESOURCE_IPC_SIZE 0x1000 |
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#define PLAT_RESOURCE_GCR_OFFSET 0x1000 |
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#define PLAT_RESOURCE_GCR_SIZE 0x1000 |
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#define PLAT_RESOURCE_BIOS_DATA_INDEX 1 |
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#define PLAT_RESOURCE_BIOS_IFACE_INDEX 2 |
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#define PLAT_RESOURCE_TELEM_SSRAM_INDEX 3 |
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#define PLAT_RESOURCE_ISP_DATA_INDEX 4 |
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#define PLAT_RESOURCE_ISP_IFACE_INDEX 5 |
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#define PLAT_RESOURCE_GTD_DATA_INDEX 6 |
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#define PLAT_RESOURCE_GTD_IFACE_INDEX 7 |
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#define PLAT_RESOURCE_ACPI_IO_INDEX 0 |
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/* |
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* BIOS does not create an ACPI device for each PMC function, but |
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* exports multiple resources from one ACPI device (IPC) for multiple |
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* functions. This driver is responsible for creating a child device and |
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* to export resources for those functions. |
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*/ |
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#define SMI_EN_OFFSET 0x0040 |
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#define SMI_EN_SIZE 4 |
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#define TCO_BASE_OFFSET 0x0060 |
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#define TCO_REGS_SIZE 16 |
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#define TELEM_SSRAM_SIZE 240 |
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#define TELEM_PMC_SSRAM_OFFSET 0x1b00 |
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#define TELEM_PUNIT_SSRAM_OFFSET 0x1a00 |
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/* Commands */ |
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#define PMC_NORTHPEAK_CTRL 0xed |
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static inline bool is_gcr_valid(u32 offset) |
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{ |
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return offset < PLAT_RESOURCE_GCR_SIZE - 8; |
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} |
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/** |
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* intel_pmc_gcr_read64() - Read a 64-bit PMC GCR register |
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* @pmc: PMC device pointer |
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* @offset: offset of GCR register from GCR address base |
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* @data: data pointer for storing the register output |
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* |
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* Reads the 64-bit PMC GCR register at given offset. |
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* |
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* Return: Negative value on error or 0 on success. |
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*/ |
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int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset, u64 *data) |
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{ |
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if (!is_gcr_valid(offset)) |
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return -EINVAL; |
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spin_lock(&pmc->gcr_lock); |
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*data = readq(pmc->gcr_mem_base + offset); |
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spin_unlock(&pmc->gcr_lock); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(intel_pmc_gcr_read64); |
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/** |
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* intel_pmc_gcr_update() - Update PMC GCR register bits |
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* @pmc: PMC device pointer |
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* @offset: offset of GCR register from GCR address base |
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* @mask: bit mask for update operation |
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* @val: update value |
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* |
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* Updates the bits of given GCR register as specified by |
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* @mask and @val. |
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* |
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* Return: Negative value on error or 0 on success. |
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*/ |
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int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset, u32 mask, u32 val) |
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{ |
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u32 new_val; |
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if (!is_gcr_valid(offset)) |
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return -EINVAL; |
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spin_lock(&pmc->gcr_lock); |
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new_val = readl(pmc->gcr_mem_base + offset); |
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new_val = (new_val & ~mask) | (val & mask); |
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writel(new_val, pmc->gcr_mem_base + offset); |
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new_val = readl(pmc->gcr_mem_base + offset); |
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spin_unlock(&pmc->gcr_lock); |
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/* Check whether the bit update is successful */ |
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return (new_val & mask) != (val & mask) ? -EIO : 0; |
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} |
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EXPORT_SYMBOL_GPL(intel_pmc_gcr_update); |
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/** |
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* intel_pmc_s0ix_counter_read() - Read S0ix residency |
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* @pmc: PMC device pointer |
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* @data: Out param that contains current S0ix residency count. |
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* |
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* Writes to @data how many usecs the system has been in low-power S0ix |
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* state. |
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* |
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* Return: An error code or 0 on success. |
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*/ |
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int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data) |
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{ |
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u64 deep, shlw; |
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spin_lock(&pmc->gcr_lock); |
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deep = readq(pmc->gcr_mem_base + PMC_GCR_TELEM_DEEP_S0IX_REG); |
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shlw = readq(pmc->gcr_mem_base + PMC_GCR_TELEM_SHLW_S0IX_REG); |
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spin_unlock(&pmc->gcr_lock); |
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*data = S0IX_RESIDENCY_IN_USECS(deep, shlw); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(intel_pmc_s0ix_counter_read); |
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/** |
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* simplecmd_store() - Send a simple IPC command |
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* @dev: Device under the attribute is |
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* @attr: Attribute in question |
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* @buf: Buffer holding data to be stored to the attribute |
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* @count: Number of bytes in @buf |
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* |
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* Expects a string with two integers separated with space. These two |
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* values hold command and subcommand that is send to PMC. |
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* |
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* Return: Number number of bytes written (@count) or negative errno in |
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* case of error. |
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*/ |
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static ssize_t simplecmd_store(struct device *dev, struct device_attribute *attr, |
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const char *buf, size_t count) |
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{ |
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struct intel_pmc_dev *pmc = dev_get_drvdata(dev); |
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struct intel_scu_ipc_dev *scu = pmc->scu; |
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int subcmd; |
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int cmd; |
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int ret; |
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ret = sscanf(buf, "%d %d", &cmd, &subcmd); |
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if (ret != 2) { |
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dev_err(dev, "Invalid values, expected: cmd subcmd\n"); |
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return -EINVAL; |
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} |
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ret = intel_scu_ipc_dev_simple_command(scu, cmd, subcmd); |
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if (ret) |
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return ret; |
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return count; |
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} |
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static DEVICE_ATTR_WO(simplecmd); |
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/** |
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* northpeak_store() - Enable or disable Northpeak |
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* @dev: Device under the attribute is |
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* @attr: Attribute in question |
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* @buf: Buffer holding data to be stored to the attribute |
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* @count: Number of bytes in @buf |
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* |
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* Expects an unsigned integer. Non-zero enables Northpeak and zero |
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* disables it. |
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* |
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* Return: Number number of bytes written (@count) or negative errno in |
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* case of error. |
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*/ |
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static ssize_t northpeak_store(struct device *dev, struct device_attribute *attr, |
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const char *buf, size_t count) |
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{ |
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struct intel_pmc_dev *pmc = dev_get_drvdata(dev); |
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struct intel_scu_ipc_dev *scu = pmc->scu; |
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unsigned long val; |
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int subcmd; |
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int ret; |
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ret = kstrtoul(buf, 0, &val); |
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if (ret) |
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return ret; |
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/* Northpeak is enabled if subcmd == 1 and disabled if it is 0 */ |
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if (val) |
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subcmd = 1; |
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else |
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subcmd = 0; |
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ret = intel_scu_ipc_dev_simple_command(scu, PMC_NORTHPEAK_CTRL, subcmd); |
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if (ret) |
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return ret; |
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return count; |
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} |
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static DEVICE_ATTR_WO(northpeak); |
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static struct attribute *intel_pmc_attrs[] = { |
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&dev_attr_northpeak.attr, |
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&dev_attr_simplecmd.attr, |
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NULL |
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}; |
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static const struct attribute_group intel_pmc_group = { |
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.attrs = intel_pmc_attrs, |
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}; |
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static const struct attribute_group *intel_pmc_groups[] = { |
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&intel_pmc_group, |
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NULL |
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}; |
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static struct resource punit_res[6]; |
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static struct mfd_cell punit = { |
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.name = "intel_punit_ipc", |
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.resources = punit_res, |
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}; |
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static struct itco_wdt_platform_data tco_pdata = { |
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.name = "Apollo Lake SoC", |
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.version = 5, |
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.no_reboot_use_pmc = true, |
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}; |
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static struct resource tco_res[2]; |
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static const struct mfd_cell tco = { |
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.name = "iTCO_wdt", |
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.ignore_resource_conflicts = true, |
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.resources = tco_res, |
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.num_resources = ARRAY_SIZE(tco_res), |
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.platform_data = &tco_pdata, |
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.pdata_size = sizeof(tco_pdata), |
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}; |
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static const struct resource telem_res[] = { |
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DEFINE_RES_MEM(TELEM_PUNIT_SSRAM_OFFSET, TELEM_SSRAM_SIZE), |
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DEFINE_RES_MEM(TELEM_PMC_SSRAM_OFFSET, TELEM_SSRAM_SIZE), |
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}; |
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static const struct mfd_cell telem = { |
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.name = "intel_telemetry", |
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.resources = telem_res, |
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.num_resources = ARRAY_SIZE(telem_res), |
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}; |
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static int intel_pmc_get_tco_resources(struct platform_device *pdev) |
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{ |
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struct resource *res; |
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if (acpi_has_watchdog()) |
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return 0; |
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res = platform_get_resource(pdev, IORESOURCE_IO, |
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PLAT_RESOURCE_ACPI_IO_INDEX); |
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if (!res) { |
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dev_err(&pdev->dev, "Failed to get IO resource\n"); |
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return -EINVAL; |
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} |
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tco_res[0].flags = IORESOURCE_IO; |
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tco_res[0].start = res->start + TCO_BASE_OFFSET; |
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tco_res[0].end = tco_res[0].start + TCO_REGS_SIZE - 1; |
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tco_res[1].flags = IORESOURCE_IO; |
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tco_res[1].start = res->start + SMI_EN_OFFSET; |
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tco_res[1].end = tco_res[1].start + SMI_EN_SIZE - 1; |
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return 0; |
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} |
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static int intel_pmc_get_resources(struct platform_device *pdev, |
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struct intel_pmc_dev *pmc, |
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struct intel_scu_ipc_data *scu_data) |
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{ |
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struct resource gcr_res; |
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size_t npunit_res = 0; |
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struct resource *res; |
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int ret; |
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scu_data->irq = platform_get_irq_optional(pdev, 0); |
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res = platform_get_resource(pdev, IORESOURCE_MEM, |
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PLAT_RESOURCE_IPC_INDEX); |
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if (!res) { |
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dev_err(&pdev->dev, "Failed to get IPC resource\n"); |
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return -EINVAL; |
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} |
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/* IPC registers */ |
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scu_data->mem.flags = res->flags; |
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scu_data->mem.start = res->start; |
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scu_data->mem.end = res->start + PLAT_RESOURCE_IPC_SIZE - 1; |
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/* GCR registers */ |
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gcr_res.flags = res->flags; |
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gcr_res.start = res->start + PLAT_RESOURCE_GCR_OFFSET; |
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gcr_res.end = gcr_res.start + PLAT_RESOURCE_GCR_SIZE - 1; |
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pmc->gcr_mem_base = devm_ioremap_resource(&pdev->dev, &gcr_res); |
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if (IS_ERR(pmc->gcr_mem_base)) |
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return PTR_ERR(pmc->gcr_mem_base); |
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/* Only register iTCO watchdog if there is no WDAT ACPI table */ |
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ret = intel_pmc_get_tco_resources(pdev); |
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if (ret) |
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return ret; |
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/* BIOS data register */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, |
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PLAT_RESOURCE_BIOS_DATA_INDEX); |
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if (!res) { |
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dev_err(&pdev->dev, "Failed to get resource of P-unit BIOS data\n"); |
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return -EINVAL; |
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} |
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punit_res[npunit_res++] = *res; |
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/* BIOS interface register */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, |
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PLAT_RESOURCE_BIOS_IFACE_INDEX); |
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if (!res) { |
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dev_err(&pdev->dev, "Failed to get resource of P-unit BIOS interface\n"); |
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return -EINVAL; |
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} |
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punit_res[npunit_res++] = *res; |
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/* ISP data register, optional */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, |
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PLAT_RESOURCE_ISP_DATA_INDEX); |
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if (res) |
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punit_res[npunit_res++] = *res; |
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/* ISP interface register, optional */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, |
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PLAT_RESOURCE_ISP_IFACE_INDEX); |
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if (res) |
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punit_res[npunit_res++] = *res; |
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/* GTD data register, optional */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, |
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PLAT_RESOURCE_GTD_DATA_INDEX); |
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if (res) |
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punit_res[npunit_res++] = *res; |
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/* GTD interface register, optional */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, |
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PLAT_RESOURCE_GTD_IFACE_INDEX); |
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if (res) |
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punit_res[npunit_res++] = *res; |
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punit.num_resources = npunit_res; |
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/* Telemetry SSRAM is optional */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, |
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PLAT_RESOURCE_TELEM_SSRAM_INDEX); |
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if (res) |
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pmc->telem_base = res; |
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return 0; |
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} |
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static int intel_pmc_create_devices(struct intel_pmc_dev *pmc) |
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{ |
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int ret; |
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if (!acpi_has_watchdog()) { |
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ret = devm_mfd_add_devices(pmc->dev, PLATFORM_DEVID_AUTO, &tco, |
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1, NULL, 0, NULL); |
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if (ret) |
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return ret; |
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} |
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ret = devm_mfd_add_devices(pmc->dev, PLATFORM_DEVID_AUTO, &punit, 1, |
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NULL, 0, NULL); |
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if (ret) |
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return ret; |
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if (pmc->telem_base) { |
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ret = devm_mfd_add_devices(pmc->dev, PLATFORM_DEVID_AUTO, |
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&telem, 1, pmc->telem_base, 0, NULL); |
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} |
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return ret; |
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} |
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static const struct acpi_device_id intel_pmc_acpi_ids[] = { |
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{ "INT34D2" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(acpi, intel_pmc_acpi_ids); |
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static int intel_pmc_probe(struct platform_device *pdev) |
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{ |
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struct intel_scu_ipc_data scu_data = {}; |
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struct intel_pmc_dev *pmc; |
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int ret; |
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pmc = devm_kzalloc(&pdev->dev, sizeof(*pmc), GFP_KERNEL); |
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if (!pmc) |
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return -ENOMEM; |
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pmc->dev = &pdev->dev; |
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spin_lock_init(&pmc->gcr_lock); |
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ret = intel_pmc_get_resources(pdev, pmc, &scu_data); |
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if (ret) { |
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dev_err(&pdev->dev, "Failed to request resources\n"); |
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return ret; |
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} |
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pmc->scu = devm_intel_scu_ipc_register(&pdev->dev, &scu_data); |
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if (IS_ERR(pmc->scu)) |
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return PTR_ERR(pmc->scu); |
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platform_set_drvdata(pdev, pmc); |
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ret = intel_pmc_create_devices(pmc); |
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if (ret) |
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dev_err(&pdev->dev, "Failed to create PMC devices\n"); |
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return ret; |
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} |
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static struct platform_driver intel_pmc_driver = { |
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.probe = intel_pmc_probe, |
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.driver = { |
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.name = "intel_pmc_bxt", |
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.acpi_match_table = intel_pmc_acpi_ids, |
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.dev_groups = intel_pmc_groups, |
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}, |
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}; |
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module_platform_driver(intel_pmc_driver); |
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MODULE_AUTHOR("Mika Westerberg <[email protected]>"); |
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MODULE_AUTHOR("Zha Qipeng <[email protected]>"); |
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MODULE_DESCRIPTION("Intel Broxton PMC driver"); |
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MODULE_LICENSE("GPL v2");
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