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1147 lines
33 KiB
1147 lines
33 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* ImgTec IR Hardware Decoder found in PowerDown Controller. |
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* |
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* Copyright 2010-2014 Imagination Technologies Ltd. |
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* |
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* This ties into the input subsystem using the RC-core. Protocol support is |
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* provided in separate modules which provide the parameters and scancode |
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* translation functions to set up the hardware decoder and interpret the |
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* resulting input. |
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*/ |
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|
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/interrupt.h> |
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#include <linux/spinlock.h> |
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#include <linux/timer.h> |
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#include <media/rc-core.h> |
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#include "img-ir.h" |
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|
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/* Decoders lock (only modified to preprocess them) */ |
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static DEFINE_SPINLOCK(img_ir_decoders_lock); |
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|
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static bool img_ir_decoders_preprocessed; |
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static struct img_ir_decoder *img_ir_decoders[] = { |
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#ifdef CONFIG_IR_IMG_NEC |
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&img_ir_nec, |
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#endif |
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#ifdef CONFIG_IR_IMG_JVC |
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&img_ir_jvc, |
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#endif |
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#ifdef CONFIG_IR_IMG_SONY |
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&img_ir_sony, |
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#endif |
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#ifdef CONFIG_IR_IMG_SHARP |
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&img_ir_sharp, |
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#endif |
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#ifdef CONFIG_IR_IMG_SANYO |
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&img_ir_sanyo, |
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#endif |
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#ifdef CONFIG_IR_IMG_RC5 |
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&img_ir_rc5, |
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#endif |
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#ifdef CONFIG_IR_IMG_RC6 |
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&img_ir_rc6, |
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#endif |
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NULL |
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}; |
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|
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#define IMG_IR_F_FILTER BIT(RC_FILTER_NORMAL) /* enable filtering */ |
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#define IMG_IR_F_WAKE BIT(RC_FILTER_WAKEUP) /* enable waking */ |
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|
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/* code type quirks */ |
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|
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#define IMG_IR_QUIRK_CODE_BROKEN 0x1 /* Decode is broken */ |
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#define IMG_IR_QUIRK_CODE_LEN_INCR 0x2 /* Bit length needs increment */ |
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/* |
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* The decoder generates rapid interrupts without actually having |
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* received any new data after an incomplete IR code is decoded. |
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*/ |
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#define IMG_IR_QUIRK_CODE_IRQ 0x4 |
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|
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/* functions for preprocessing timings, ensuring max is set */ |
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|
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static void img_ir_timing_preprocess(struct img_ir_timing_range *range, |
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unsigned int unit) |
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{ |
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if (range->max < range->min) |
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range->max = range->min; |
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if (unit) { |
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/* multiply by unit and convert to microseconds */ |
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range->min = (range->min*unit)/1000; |
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range->max = (range->max*unit + 999)/1000; /* round up */ |
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} |
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} |
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|
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static void img_ir_symbol_timing_preprocess(struct img_ir_symbol_timing *timing, |
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unsigned int unit) |
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{ |
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img_ir_timing_preprocess(&timing->pulse, unit); |
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img_ir_timing_preprocess(&timing->space, unit); |
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} |
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|
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static void img_ir_timings_preprocess(struct img_ir_timings *timings, |
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unsigned int unit) |
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{ |
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img_ir_symbol_timing_preprocess(&timings->ldr, unit); |
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img_ir_symbol_timing_preprocess(&timings->s00, unit); |
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img_ir_symbol_timing_preprocess(&timings->s01, unit); |
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img_ir_symbol_timing_preprocess(&timings->s10, unit); |
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img_ir_symbol_timing_preprocess(&timings->s11, unit); |
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/* default s10 and s11 to s00 and s01 if no leader */ |
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if (unit) |
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/* multiply by unit and convert to microseconds (round up) */ |
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timings->ft.ft_min = (timings->ft.ft_min*unit + 999)/1000; |
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} |
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|
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/* functions for filling empty fields with defaults */ |
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|
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static void img_ir_timing_defaults(struct img_ir_timing_range *range, |
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struct img_ir_timing_range *defaults) |
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{ |
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if (!range->min) |
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range->min = defaults->min; |
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if (!range->max) |
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range->max = defaults->max; |
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} |
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|
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static void img_ir_symbol_timing_defaults(struct img_ir_symbol_timing *timing, |
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struct img_ir_symbol_timing *defaults) |
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{ |
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img_ir_timing_defaults(&timing->pulse, &defaults->pulse); |
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img_ir_timing_defaults(&timing->space, &defaults->space); |
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} |
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|
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static void img_ir_timings_defaults(struct img_ir_timings *timings, |
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struct img_ir_timings *defaults) |
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{ |
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img_ir_symbol_timing_defaults(&timings->ldr, &defaults->ldr); |
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img_ir_symbol_timing_defaults(&timings->s00, &defaults->s00); |
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img_ir_symbol_timing_defaults(&timings->s01, &defaults->s01); |
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img_ir_symbol_timing_defaults(&timings->s10, &defaults->s10); |
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img_ir_symbol_timing_defaults(&timings->s11, &defaults->s11); |
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if (!timings->ft.ft_min) |
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timings->ft.ft_min = defaults->ft.ft_min; |
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} |
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|
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/* functions for converting timings to register values */ |
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|
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/** |
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* img_ir_control() - Convert control struct to control register value. |
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* @control: Control data |
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* |
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* Returns: The control register value equivalent of @control. |
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*/ |
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static u32 img_ir_control(const struct img_ir_control *control) |
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{ |
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u32 ctrl = control->code_type << IMG_IR_CODETYPE_SHIFT; |
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if (control->decoden) |
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ctrl |= IMG_IR_DECODEN; |
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if (control->hdrtog) |
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ctrl |= IMG_IR_HDRTOG; |
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if (control->ldrdec) |
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ctrl |= IMG_IR_LDRDEC; |
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if (control->decodinpol) |
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ctrl |= IMG_IR_DECODINPOL; |
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if (control->bitorien) |
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ctrl |= IMG_IR_BITORIEN; |
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if (control->d1validsel) |
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ctrl |= IMG_IR_D1VALIDSEL; |
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if (control->bitinv) |
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ctrl |= IMG_IR_BITINV; |
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if (control->decodend2) |
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ctrl |= IMG_IR_DECODEND2; |
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if (control->bitoriend2) |
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ctrl |= IMG_IR_BITORIEND2; |
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if (control->bitinvd2) |
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ctrl |= IMG_IR_BITINVD2; |
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return ctrl; |
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} |
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|
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/** |
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* img_ir_timing_range_convert() - Convert microsecond range. |
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* @out: Output timing range in clock cycles with a shift. |
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* @in: Input timing range in microseconds. |
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* @tolerance: Tolerance as a fraction of 128 (roughly percent). |
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* @clock_hz: IR clock rate in Hz. |
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* @shift: Shift of output units. |
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* |
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* Converts min and max from microseconds to IR clock cycles, applies a |
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* tolerance, and shifts for the register, rounding in the right direction. |
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* Note that in and out can safely be the same object. |
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*/ |
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static void img_ir_timing_range_convert(struct img_ir_timing_range *out, |
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const struct img_ir_timing_range *in, |
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unsigned int tolerance, |
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unsigned long clock_hz, |
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unsigned int shift) |
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{ |
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unsigned int min = in->min; |
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unsigned int max = in->max; |
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/* add a tolerance */ |
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min = min - (min*tolerance >> 7); |
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max = max + (max*tolerance >> 7); |
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/* convert from microseconds into clock cycles */ |
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min = min*clock_hz / 1000000; |
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max = (max*clock_hz + 999999) / 1000000; /* round up */ |
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/* apply shift and copy to output */ |
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out->min = min >> shift; |
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out->max = (max + ((1 << shift) - 1)) >> shift; /* round up */ |
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} |
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|
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/** |
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* img_ir_symbol_timing() - Convert symbol timing struct to register value. |
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* @timing: Symbol timing data |
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* @tolerance: Timing tolerance where 0-128 represents 0-100% |
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* @clock_hz: Frequency of source clock in Hz |
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* @pd_shift: Shift to apply to symbol period |
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* @w_shift: Shift to apply to symbol width |
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* |
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* Returns: Symbol timing register value based on arguments. |
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*/ |
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static u32 img_ir_symbol_timing(const struct img_ir_symbol_timing *timing, |
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unsigned int tolerance, |
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unsigned long clock_hz, |
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unsigned int pd_shift, |
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unsigned int w_shift) |
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{ |
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struct img_ir_timing_range hw_pulse, hw_period; |
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/* we calculate period in hw_period, then convert in place */ |
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hw_period.min = timing->pulse.min + timing->space.min; |
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hw_period.max = timing->pulse.max + timing->space.max; |
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img_ir_timing_range_convert(&hw_period, &hw_period, |
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tolerance, clock_hz, pd_shift); |
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img_ir_timing_range_convert(&hw_pulse, &timing->pulse, |
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tolerance, clock_hz, w_shift); |
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/* construct register value */ |
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return (hw_period.max << IMG_IR_PD_MAX_SHIFT) | |
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(hw_period.min << IMG_IR_PD_MIN_SHIFT) | |
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(hw_pulse.max << IMG_IR_W_MAX_SHIFT) | |
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(hw_pulse.min << IMG_IR_W_MIN_SHIFT); |
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} |
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|
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/** |
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* img_ir_free_timing() - Convert free time timing struct to register value. |
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* @timing: Free symbol timing data |
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* @clock_hz: Source clock frequency in Hz |
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* |
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* Returns: Free symbol timing register value. |
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*/ |
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static u32 img_ir_free_timing(const struct img_ir_free_timing *timing, |
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unsigned long clock_hz) |
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{ |
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unsigned int minlen, maxlen, ft_min; |
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/* minlen is only 5 bits, and round minlen to multiple of 2 */ |
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if (timing->minlen < 30) |
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minlen = timing->minlen & -2; |
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else |
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minlen = 30; |
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/* maxlen has maximum value of 48, and round maxlen to multiple of 2 */ |
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if (timing->maxlen < 48) |
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maxlen = (timing->maxlen + 1) & -2; |
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else |
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maxlen = 48; |
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/* convert and shift ft_min, rounding upwards */ |
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ft_min = (timing->ft_min*clock_hz + 999999) / 1000000; |
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ft_min = (ft_min + 7) >> 3; |
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/* construct register value */ |
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return (maxlen << IMG_IR_MAXLEN_SHIFT) | |
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(minlen << IMG_IR_MINLEN_SHIFT) | |
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(ft_min << IMG_IR_FT_MIN_SHIFT); |
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} |
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|
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/** |
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* img_ir_free_timing_dynamic() - Update free time register value. |
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* @st_ft: Static free time register value from img_ir_free_timing. |
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* @filter: Current filter which may additionally restrict min/max len. |
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* |
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* Returns: Updated free time register value based on the current filter. |
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*/ |
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static u32 img_ir_free_timing_dynamic(u32 st_ft, struct img_ir_filter *filter) |
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{ |
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unsigned int minlen, maxlen, newminlen, newmaxlen; |
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|
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/* round minlen, maxlen to multiple of 2 */ |
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newminlen = filter->minlen & -2; |
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newmaxlen = (filter->maxlen + 1) & -2; |
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/* extract min/max len from register */ |
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minlen = (st_ft & IMG_IR_MINLEN) >> IMG_IR_MINLEN_SHIFT; |
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maxlen = (st_ft & IMG_IR_MAXLEN) >> IMG_IR_MAXLEN_SHIFT; |
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/* if the new values are more restrictive, update the register value */ |
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if (newminlen > minlen) { |
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st_ft &= ~IMG_IR_MINLEN; |
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st_ft |= newminlen << IMG_IR_MINLEN_SHIFT; |
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} |
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if (newmaxlen < maxlen) { |
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st_ft &= ~IMG_IR_MAXLEN; |
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st_ft |= newmaxlen << IMG_IR_MAXLEN_SHIFT; |
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} |
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return st_ft; |
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} |
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|
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/** |
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* img_ir_timings_convert() - Convert timings to register values |
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* @regs: Output timing register values |
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* @timings: Input timing data |
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* @tolerance: Timing tolerance where 0-128 represents 0-100% |
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* @clock_hz: Source clock frequency in Hz |
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*/ |
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static void img_ir_timings_convert(struct img_ir_timing_regvals *regs, |
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const struct img_ir_timings *timings, |
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unsigned int tolerance, |
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unsigned int clock_hz) |
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{ |
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/* leader symbol timings are divided by 16 */ |
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regs->ldr = img_ir_symbol_timing(&timings->ldr, tolerance, clock_hz, |
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4, 4); |
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/* other symbol timings, pd fields only are divided by 2 */ |
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regs->s00 = img_ir_symbol_timing(&timings->s00, tolerance, clock_hz, |
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1, 0); |
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regs->s01 = img_ir_symbol_timing(&timings->s01, tolerance, clock_hz, |
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1, 0); |
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regs->s10 = img_ir_symbol_timing(&timings->s10, tolerance, clock_hz, |
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1, 0); |
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regs->s11 = img_ir_symbol_timing(&timings->s11, tolerance, clock_hz, |
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1, 0); |
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regs->ft = img_ir_free_timing(&timings->ft, clock_hz); |
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} |
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|
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/** |
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* img_ir_decoder_preprocess() - Preprocess timings in decoder. |
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* @decoder: Decoder to be preprocessed. |
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* |
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* Ensures that the symbol timing ranges are valid with respect to ordering, and |
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* does some fixed conversion on them. |
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*/ |
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static void img_ir_decoder_preprocess(struct img_ir_decoder *decoder) |
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{ |
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/* default tolerance */ |
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if (!decoder->tolerance) |
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decoder->tolerance = 10; /* percent */ |
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/* and convert tolerance to fraction out of 128 */ |
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decoder->tolerance = decoder->tolerance * 128 / 100; |
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|
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/* fill in implicit fields */ |
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img_ir_timings_preprocess(&decoder->timings, decoder->unit); |
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|
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/* do the same for repeat timings if applicable */ |
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if (decoder->repeat) { |
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img_ir_timings_preprocess(&decoder->rtimings, decoder->unit); |
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img_ir_timings_defaults(&decoder->rtimings, &decoder->timings); |
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} |
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} |
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|
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/** |
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* img_ir_decoder_convert() - Generate internal timings in decoder. |
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* @decoder: Decoder to be converted to internal timings. |
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* @reg_timings: Timing register values. |
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* @clock_hz: IR clock rate in Hz. |
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* |
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* Fills out the repeat timings and timing register values for a specific clock |
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* rate. |
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*/ |
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static void img_ir_decoder_convert(const struct img_ir_decoder *decoder, |
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struct img_ir_reg_timings *reg_timings, |
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unsigned int clock_hz) |
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{ |
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/* calculate control value */ |
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reg_timings->ctrl = img_ir_control(&decoder->control); |
|
|
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/* fill in implicit fields and calculate register values */ |
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img_ir_timings_convert(®_timings->timings, &decoder->timings, |
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decoder->tolerance, clock_hz); |
|
|
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/* do the same for repeat timings if applicable */ |
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if (decoder->repeat) |
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img_ir_timings_convert(®_timings->rtimings, |
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&decoder->rtimings, decoder->tolerance, |
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clock_hz); |
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} |
|
|
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/** |
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* img_ir_write_timings() - Write timings to the hardware now |
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* @priv: IR private data |
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* @regs: Timing register values to write |
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* @type: RC filter type (RC_FILTER_*) |
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* |
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* Write timing register values @regs to the hardware, taking into account the |
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* current filter which may impose restrictions on the length of the expected |
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* data. |
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*/ |
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static void img_ir_write_timings(struct img_ir_priv *priv, |
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struct img_ir_timing_regvals *regs, |
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enum rc_filter_type type) |
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{ |
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struct img_ir_priv_hw *hw = &priv->hw; |
|
|
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/* filter may be more restrictive to minlen, maxlen */ |
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u32 ft = regs->ft; |
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if (hw->flags & BIT(type)) |
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ft = img_ir_free_timing_dynamic(regs->ft, &hw->filters[type]); |
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/* write to registers */ |
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img_ir_write(priv, IMG_IR_LEAD_SYMB_TIMING, regs->ldr); |
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img_ir_write(priv, IMG_IR_S00_SYMB_TIMING, regs->s00); |
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img_ir_write(priv, IMG_IR_S01_SYMB_TIMING, regs->s01); |
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img_ir_write(priv, IMG_IR_S10_SYMB_TIMING, regs->s10); |
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img_ir_write(priv, IMG_IR_S11_SYMB_TIMING, regs->s11); |
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img_ir_write(priv, IMG_IR_FREE_SYMB_TIMING, ft); |
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dev_dbg(priv->dev, "timings: ldr=%#x, s=[%#x, %#x, %#x, %#x], ft=%#x\n", |
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regs->ldr, regs->s00, regs->s01, regs->s10, regs->s11, ft); |
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} |
|
|
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static void img_ir_write_filter(struct img_ir_priv *priv, |
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struct img_ir_filter *filter) |
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{ |
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if (filter) { |
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dev_dbg(priv->dev, "IR filter=%016llx & %016llx\n", |
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(unsigned long long)filter->data, |
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(unsigned long long)filter->mask); |
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img_ir_write(priv, IMG_IR_IRQ_MSG_DATA_LW, (u32)filter->data); |
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img_ir_write(priv, IMG_IR_IRQ_MSG_DATA_UP, (u32)(filter->data |
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>> 32)); |
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img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_LW, (u32)filter->mask); |
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img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_UP, (u32)(filter->mask |
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>> 32)); |
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} else { |
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dev_dbg(priv->dev, "IR clearing filter\n"); |
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img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_LW, 0); |
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img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_UP, 0); |
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} |
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} |
|
|
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/* caller must have lock */ |
|
static void _img_ir_set_filter(struct img_ir_priv *priv, |
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struct img_ir_filter *filter) |
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{ |
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struct img_ir_priv_hw *hw = &priv->hw; |
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u32 irq_en, irq_on; |
|
|
|
irq_en = img_ir_read(priv, IMG_IR_IRQ_ENABLE); |
|
if (filter) { |
|
/* Only use the match interrupt */ |
|
hw->filters[RC_FILTER_NORMAL] = *filter; |
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hw->flags |= IMG_IR_F_FILTER; |
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irq_on = IMG_IR_IRQ_DATA_MATCH; |
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irq_en &= ~(IMG_IR_IRQ_DATA_VALID | IMG_IR_IRQ_DATA2_VALID); |
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} else { |
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/* Only use the valid interrupt */ |
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hw->flags &= ~IMG_IR_F_FILTER; |
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irq_en &= ~IMG_IR_IRQ_DATA_MATCH; |
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irq_on = IMG_IR_IRQ_DATA_VALID | IMG_IR_IRQ_DATA2_VALID; |
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} |
|
irq_en |= irq_on; |
|
|
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img_ir_write_filter(priv, filter); |
|
/* clear any interrupts we're enabling so we don't handle old ones */ |
|
img_ir_write(priv, IMG_IR_IRQ_CLEAR, irq_on); |
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img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en); |
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} |
|
|
|
/* caller must have lock */ |
|
static void _img_ir_set_wake_filter(struct img_ir_priv *priv, |
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struct img_ir_filter *filter) |
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{ |
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struct img_ir_priv_hw *hw = &priv->hw; |
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if (filter) { |
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/* Enable wake, and copy filter for later */ |
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hw->filters[RC_FILTER_WAKEUP] = *filter; |
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hw->flags |= IMG_IR_F_WAKE; |
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} else { |
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/* Disable wake */ |
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hw->flags &= ~IMG_IR_F_WAKE; |
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} |
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} |
|
|
|
/* Callback for setting scancode filter */ |
|
static int img_ir_set_filter(struct rc_dev *dev, enum rc_filter_type type, |
|
struct rc_scancode_filter *sc_filter) |
|
{ |
|
struct img_ir_priv *priv = dev->priv; |
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struct img_ir_priv_hw *hw = &priv->hw; |
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struct img_ir_filter filter, *filter_ptr = &filter; |
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int ret = 0; |
|
|
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dev_dbg(priv->dev, "IR scancode %sfilter=%08x & %08x\n", |
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type == RC_FILTER_WAKEUP ? "wake " : "", |
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sc_filter->data, |
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sc_filter->mask); |
|
|
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spin_lock_irq(&priv->lock); |
|
|
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/* filtering can always be disabled */ |
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if (!sc_filter->mask) { |
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filter_ptr = NULL; |
|
goto set_unlock; |
|
} |
|
|
|
/* current decoder must support scancode filtering */ |
|
if (!hw->decoder || !hw->decoder->filter) { |
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ret = -EINVAL; |
|
goto unlock; |
|
} |
|
|
|
/* convert scancode filter to raw filter */ |
|
filter.minlen = 0; |
|
filter.maxlen = ~0; |
|
if (type == RC_FILTER_NORMAL) { |
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/* guess scancode from protocol */ |
|
ret = hw->decoder->filter(sc_filter, &filter, |
|
dev->enabled_protocols); |
|
} else { |
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/* for wakeup user provided exact protocol variant */ |
|
ret = hw->decoder->filter(sc_filter, &filter, |
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1ULL << dev->wakeup_protocol); |
|
} |
|
if (ret) |
|
goto unlock; |
|
dev_dbg(priv->dev, "IR raw %sfilter=%016llx & %016llx\n", |
|
type == RC_FILTER_WAKEUP ? "wake " : "", |
|
(unsigned long long)filter.data, |
|
(unsigned long long)filter.mask); |
|
|
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set_unlock: |
|
/* apply raw filters */ |
|
switch (type) { |
|
case RC_FILTER_NORMAL: |
|
_img_ir_set_filter(priv, filter_ptr); |
|
break; |
|
case RC_FILTER_WAKEUP: |
|
_img_ir_set_wake_filter(priv, filter_ptr); |
|
break; |
|
default: |
|
ret = -EINVAL; |
|
} |
|
|
|
unlock: |
|
spin_unlock_irq(&priv->lock); |
|
return ret; |
|
} |
|
|
|
static int img_ir_set_normal_filter(struct rc_dev *dev, |
|
struct rc_scancode_filter *sc_filter) |
|
{ |
|
return img_ir_set_filter(dev, RC_FILTER_NORMAL, sc_filter); |
|
} |
|
|
|
static int img_ir_set_wakeup_filter(struct rc_dev *dev, |
|
struct rc_scancode_filter *sc_filter) |
|
{ |
|
return img_ir_set_filter(dev, RC_FILTER_WAKEUP, sc_filter); |
|
} |
|
|
|
/** |
|
* img_ir_set_decoder() - Set the current decoder. |
|
* @priv: IR private data. |
|
* @decoder: Decoder to use with immediate effect. |
|
* @proto: Protocol bitmap (or 0 to use decoder->type). |
|
*/ |
|
static void img_ir_set_decoder(struct img_ir_priv *priv, |
|
const struct img_ir_decoder *decoder, |
|
u64 proto) |
|
{ |
|
struct img_ir_priv_hw *hw = &priv->hw; |
|
struct rc_dev *rdev = hw->rdev; |
|
u32 ir_status, irq_en; |
|
spin_lock_irq(&priv->lock); |
|
|
|
/* |
|
* First record that the protocol is being stopped so that the end timer |
|
* isn't restarted while we're trying to stop it. |
|
*/ |
|
hw->stopping = true; |
|
|
|
/* |
|
* Release the lock to stop the end timer, since the end timer handler |
|
* acquires the lock and we don't want to deadlock waiting for it. |
|
*/ |
|
spin_unlock_irq(&priv->lock); |
|
del_timer_sync(&hw->end_timer); |
|
del_timer_sync(&hw->suspend_timer); |
|
spin_lock_irq(&priv->lock); |
|
|
|
hw->stopping = false; |
|
|
|
/* switch off and disable interrupts */ |
|
img_ir_write(priv, IMG_IR_CONTROL, 0); |
|
irq_en = img_ir_read(priv, IMG_IR_IRQ_ENABLE); |
|
img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en & IMG_IR_IRQ_EDGE); |
|
img_ir_write(priv, IMG_IR_IRQ_CLEAR, IMG_IR_IRQ_ALL & ~IMG_IR_IRQ_EDGE); |
|
|
|
/* ack any data already detected */ |
|
ir_status = img_ir_read(priv, IMG_IR_STATUS); |
|
if (ir_status & (IMG_IR_RXDVAL | IMG_IR_RXDVALD2)) { |
|
ir_status &= ~(IMG_IR_RXDVAL | IMG_IR_RXDVALD2); |
|
img_ir_write(priv, IMG_IR_STATUS, ir_status); |
|
} |
|
|
|
/* always read data to clear buffer if IR wakes the device */ |
|
img_ir_read(priv, IMG_IR_DATA_LW); |
|
img_ir_read(priv, IMG_IR_DATA_UP); |
|
|
|
/* switch back to normal mode */ |
|
hw->mode = IMG_IR_M_NORMAL; |
|
|
|
/* clear the wakeup scancode filter */ |
|
rdev->scancode_wakeup_filter.data = 0; |
|
rdev->scancode_wakeup_filter.mask = 0; |
|
rdev->wakeup_protocol = RC_PROTO_UNKNOWN; |
|
|
|
/* clear raw filters */ |
|
_img_ir_set_filter(priv, NULL); |
|
_img_ir_set_wake_filter(priv, NULL); |
|
|
|
/* clear the enabled protocols */ |
|
hw->enabled_protocols = 0; |
|
|
|
/* switch decoder */ |
|
hw->decoder = decoder; |
|
if (!decoder) |
|
goto unlock; |
|
|
|
/* set the enabled protocols */ |
|
if (!proto) |
|
proto = decoder->type; |
|
hw->enabled_protocols = proto; |
|
|
|
/* write the new timings */ |
|
img_ir_decoder_convert(decoder, &hw->reg_timings, hw->clk_hz); |
|
img_ir_write_timings(priv, &hw->reg_timings.timings, RC_FILTER_NORMAL); |
|
|
|
/* set up and enable */ |
|
img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl); |
|
|
|
|
|
unlock: |
|
spin_unlock_irq(&priv->lock); |
|
} |
|
|
|
/** |
|
* img_ir_decoder_compatable() - Find whether a decoder will work with a device. |
|
* @priv: IR private data. |
|
* @dec: Decoder to check. |
|
* |
|
* Returns: true if @dec is compatible with the device @priv refers to. |
|
*/ |
|
static bool img_ir_decoder_compatible(struct img_ir_priv *priv, |
|
const struct img_ir_decoder *dec) |
|
{ |
|
unsigned int ct; |
|
|
|
/* don't accept decoders using code types which aren't supported */ |
|
ct = dec->control.code_type; |
|
if (priv->hw.ct_quirks[ct] & IMG_IR_QUIRK_CODE_BROKEN) |
|
return false; |
|
|
|
return true; |
|
} |
|
|
|
/** |
|
* img_ir_allowed_protos() - Get allowed protocols from global decoder list. |
|
* @priv: IR private data. |
|
* |
|
* Returns: Mask of protocols supported by the device @priv refers to. |
|
*/ |
|
static u64 img_ir_allowed_protos(struct img_ir_priv *priv) |
|
{ |
|
u64 protos = 0; |
|
struct img_ir_decoder **decp; |
|
|
|
for (decp = img_ir_decoders; *decp; ++decp) { |
|
const struct img_ir_decoder *dec = *decp; |
|
if (img_ir_decoder_compatible(priv, dec)) |
|
protos |= dec->type; |
|
} |
|
return protos; |
|
} |
|
|
|
/* Callback for changing protocol using sysfs */ |
|
static int img_ir_change_protocol(struct rc_dev *dev, u64 *ir_type) |
|
{ |
|
struct img_ir_priv *priv = dev->priv; |
|
struct img_ir_priv_hw *hw = &priv->hw; |
|
struct rc_dev *rdev = hw->rdev; |
|
struct img_ir_decoder **decp; |
|
u64 wakeup_protocols; |
|
|
|
if (!*ir_type) { |
|
/* disable all protocols */ |
|
img_ir_set_decoder(priv, NULL, 0); |
|
goto success; |
|
} |
|
for (decp = img_ir_decoders; *decp; ++decp) { |
|
const struct img_ir_decoder *dec = *decp; |
|
if (!img_ir_decoder_compatible(priv, dec)) |
|
continue; |
|
if (*ir_type & dec->type) { |
|
*ir_type &= dec->type; |
|
img_ir_set_decoder(priv, dec, *ir_type); |
|
goto success; |
|
} |
|
} |
|
return -EINVAL; |
|
|
|
success: |
|
/* |
|
* Only allow matching wakeup protocols for now, and only if filtering |
|
* is supported. |
|
*/ |
|
wakeup_protocols = *ir_type; |
|
if (!hw->decoder || !hw->decoder->filter) |
|
wakeup_protocols = 0; |
|
rdev->allowed_wakeup_protocols = wakeup_protocols; |
|
return 0; |
|
} |
|
|
|
/* Changes ir-core protocol device attribute */ |
|
static void img_ir_set_protocol(struct img_ir_priv *priv, u64 proto) |
|
{ |
|
struct rc_dev *rdev = priv->hw.rdev; |
|
|
|
mutex_lock(&rdev->lock); |
|
rdev->enabled_protocols = proto; |
|
rdev->allowed_wakeup_protocols = proto; |
|
mutex_unlock(&rdev->lock); |
|
} |
|
|
|
/* Set up IR decoders */ |
|
static void img_ir_init_decoders(void) |
|
{ |
|
struct img_ir_decoder **decp; |
|
|
|
spin_lock(&img_ir_decoders_lock); |
|
if (!img_ir_decoders_preprocessed) { |
|
for (decp = img_ir_decoders; *decp; ++decp) |
|
img_ir_decoder_preprocess(*decp); |
|
img_ir_decoders_preprocessed = true; |
|
} |
|
spin_unlock(&img_ir_decoders_lock); |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
/** |
|
* img_ir_enable_wake() - Switch to wake mode. |
|
* @priv: IR private data. |
|
* |
|
* Returns: non-zero if the IR can wake the system. |
|
*/ |
|
static int img_ir_enable_wake(struct img_ir_priv *priv) |
|
{ |
|
struct img_ir_priv_hw *hw = &priv->hw; |
|
int ret = 0; |
|
|
|
spin_lock_irq(&priv->lock); |
|
if (hw->flags & IMG_IR_F_WAKE) { |
|
/* interrupt only on a match */ |
|
hw->suspend_irqen = img_ir_read(priv, IMG_IR_IRQ_ENABLE); |
|
img_ir_write(priv, IMG_IR_IRQ_ENABLE, IMG_IR_IRQ_DATA_MATCH); |
|
img_ir_write_filter(priv, &hw->filters[RC_FILTER_WAKEUP]); |
|
img_ir_write_timings(priv, &hw->reg_timings.timings, |
|
RC_FILTER_WAKEUP); |
|
hw->mode = IMG_IR_M_WAKE; |
|
ret = 1; |
|
} |
|
spin_unlock_irq(&priv->lock); |
|
return ret; |
|
} |
|
|
|
/** |
|
* img_ir_disable_wake() - Switch out of wake mode. |
|
* @priv: IR private data |
|
* |
|
* Returns: 1 if the hardware should be allowed to wake from a sleep state. |
|
* 0 otherwise. |
|
*/ |
|
static int img_ir_disable_wake(struct img_ir_priv *priv) |
|
{ |
|
struct img_ir_priv_hw *hw = &priv->hw; |
|
int ret = 0; |
|
|
|
spin_lock_irq(&priv->lock); |
|
if (hw->flags & IMG_IR_F_WAKE) { |
|
/* restore normal filtering */ |
|
if (hw->flags & IMG_IR_F_FILTER) { |
|
img_ir_write(priv, IMG_IR_IRQ_ENABLE, |
|
(hw->suspend_irqen & IMG_IR_IRQ_EDGE) | |
|
IMG_IR_IRQ_DATA_MATCH); |
|
img_ir_write_filter(priv, |
|
&hw->filters[RC_FILTER_NORMAL]); |
|
} else { |
|
img_ir_write(priv, IMG_IR_IRQ_ENABLE, |
|
(hw->suspend_irqen & IMG_IR_IRQ_EDGE) | |
|
IMG_IR_IRQ_DATA_VALID | |
|
IMG_IR_IRQ_DATA2_VALID); |
|
img_ir_write_filter(priv, NULL); |
|
} |
|
img_ir_write_timings(priv, &hw->reg_timings.timings, |
|
RC_FILTER_NORMAL); |
|
hw->mode = IMG_IR_M_NORMAL; |
|
ret = 1; |
|
} |
|
spin_unlock_irq(&priv->lock); |
|
return ret; |
|
} |
|
#endif /* CONFIG_PM_SLEEP */ |
|
|
|
/* lock must be held */ |
|
static void img_ir_begin_repeat(struct img_ir_priv *priv) |
|
{ |
|
struct img_ir_priv_hw *hw = &priv->hw; |
|
if (hw->mode == IMG_IR_M_NORMAL) { |
|
/* switch to repeat timings */ |
|
img_ir_write(priv, IMG_IR_CONTROL, 0); |
|
hw->mode = IMG_IR_M_REPEATING; |
|
img_ir_write_timings(priv, &hw->reg_timings.rtimings, |
|
RC_FILTER_NORMAL); |
|
img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl); |
|
} |
|
} |
|
|
|
/* lock must be held */ |
|
static void img_ir_end_repeat(struct img_ir_priv *priv) |
|
{ |
|
struct img_ir_priv_hw *hw = &priv->hw; |
|
if (hw->mode == IMG_IR_M_REPEATING) { |
|
/* switch to normal timings */ |
|
img_ir_write(priv, IMG_IR_CONTROL, 0); |
|
hw->mode = IMG_IR_M_NORMAL; |
|
img_ir_write_timings(priv, &hw->reg_timings.timings, |
|
RC_FILTER_NORMAL); |
|
img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl); |
|
} |
|
} |
|
|
|
/* lock must be held */ |
|
static void img_ir_handle_data(struct img_ir_priv *priv, u32 len, u64 raw) |
|
{ |
|
struct img_ir_priv_hw *hw = &priv->hw; |
|
const struct img_ir_decoder *dec = hw->decoder; |
|
int ret = IMG_IR_SCANCODE; |
|
struct img_ir_scancode_req request; |
|
|
|
request.protocol = RC_PROTO_UNKNOWN; |
|
request.toggle = 0; |
|
|
|
if (dec->scancode) |
|
ret = dec->scancode(len, raw, hw->enabled_protocols, &request); |
|
else if (len >= 32) |
|
request.scancode = (u32)raw; |
|
else if (len < 32) |
|
request.scancode = (u32)raw & ((1 << len)-1); |
|
dev_dbg(priv->dev, "data (%u bits) = %#llx\n", |
|
len, (unsigned long long)raw); |
|
if (ret == IMG_IR_SCANCODE) { |
|
dev_dbg(priv->dev, "decoded scan code %#x, toggle %u\n", |
|
request.scancode, request.toggle); |
|
rc_keydown(hw->rdev, request.protocol, request.scancode, |
|
request.toggle); |
|
img_ir_end_repeat(priv); |
|
} else if (ret == IMG_IR_REPEATCODE) { |
|
if (hw->mode == IMG_IR_M_REPEATING) { |
|
dev_dbg(priv->dev, "decoded repeat code\n"); |
|
rc_repeat(hw->rdev); |
|
} else { |
|
dev_dbg(priv->dev, "decoded unexpected repeat code, ignoring\n"); |
|
} |
|
} else { |
|
dev_dbg(priv->dev, "decode failed (%d)\n", ret); |
|
return; |
|
} |
|
|
|
|
|
/* we mustn't update the end timer while trying to stop it */ |
|
if (dec->repeat && !hw->stopping) { |
|
unsigned long interval; |
|
|
|
img_ir_begin_repeat(priv); |
|
|
|
/* update timer, but allowing for 1/8th tolerance */ |
|
interval = dec->repeat + (dec->repeat >> 3); |
|
mod_timer(&hw->end_timer, |
|
jiffies + msecs_to_jiffies(interval)); |
|
} |
|
} |
|
|
|
/* timer function to end waiting for repeat. */ |
|
static void img_ir_end_timer(struct timer_list *t) |
|
{ |
|
struct img_ir_priv *priv = from_timer(priv, t, hw.end_timer); |
|
|
|
spin_lock_irq(&priv->lock); |
|
img_ir_end_repeat(priv); |
|
spin_unlock_irq(&priv->lock); |
|
} |
|
|
|
/* |
|
* Timer function to re-enable the current protocol after it had been |
|
* cleared when invalid interrupts were generated due to a quirk in the |
|
* img-ir decoder. |
|
*/ |
|
static void img_ir_suspend_timer(struct timer_list *t) |
|
{ |
|
struct img_ir_priv *priv = from_timer(priv, t, hw.suspend_timer); |
|
|
|
spin_lock_irq(&priv->lock); |
|
/* |
|
* Don't overwrite enabled valid/match IRQs if they have already been |
|
* changed by e.g. a filter change. |
|
*/ |
|
if ((priv->hw.quirk_suspend_irq & IMG_IR_IRQ_EDGE) == |
|
img_ir_read(priv, IMG_IR_IRQ_ENABLE)) |
|
img_ir_write(priv, IMG_IR_IRQ_ENABLE, |
|
priv->hw.quirk_suspend_irq); |
|
/* enable */ |
|
img_ir_write(priv, IMG_IR_CONTROL, priv->hw.reg_timings.ctrl); |
|
spin_unlock_irq(&priv->lock); |
|
} |
|
|
|
#ifdef CONFIG_COMMON_CLK |
|
static void img_ir_change_frequency(struct img_ir_priv *priv, |
|
struct clk_notifier_data *change) |
|
{ |
|
struct img_ir_priv_hw *hw = &priv->hw; |
|
|
|
dev_dbg(priv->dev, "clk changed %lu HZ -> %lu HZ\n", |
|
change->old_rate, change->new_rate); |
|
|
|
spin_lock_irq(&priv->lock); |
|
if (hw->clk_hz == change->new_rate) |
|
goto unlock; |
|
hw->clk_hz = change->new_rate; |
|
/* refresh current timings */ |
|
if (hw->decoder) { |
|
img_ir_decoder_convert(hw->decoder, &hw->reg_timings, |
|
hw->clk_hz); |
|
switch (hw->mode) { |
|
case IMG_IR_M_NORMAL: |
|
img_ir_write_timings(priv, &hw->reg_timings.timings, |
|
RC_FILTER_NORMAL); |
|
break; |
|
case IMG_IR_M_REPEATING: |
|
img_ir_write_timings(priv, &hw->reg_timings.rtimings, |
|
RC_FILTER_NORMAL); |
|
break; |
|
#ifdef CONFIG_PM_SLEEP |
|
case IMG_IR_M_WAKE: |
|
img_ir_write_timings(priv, &hw->reg_timings.timings, |
|
RC_FILTER_WAKEUP); |
|
break; |
|
#endif |
|
} |
|
} |
|
unlock: |
|
spin_unlock_irq(&priv->lock); |
|
} |
|
|
|
static int img_ir_clk_notify(struct notifier_block *self, unsigned long action, |
|
void *data) |
|
{ |
|
struct img_ir_priv *priv = container_of(self, struct img_ir_priv, |
|
hw.clk_nb); |
|
switch (action) { |
|
case POST_RATE_CHANGE: |
|
img_ir_change_frequency(priv, data); |
|
break; |
|
default: |
|
break; |
|
} |
|
return NOTIFY_OK; |
|
} |
|
#endif /* CONFIG_COMMON_CLK */ |
|
|
|
/* called with priv->lock held */ |
|
void img_ir_isr_hw(struct img_ir_priv *priv, u32 irq_status) |
|
{ |
|
struct img_ir_priv_hw *hw = &priv->hw; |
|
u32 ir_status, len, lw, up; |
|
unsigned int ct; |
|
|
|
/* use the current decoder */ |
|
if (!hw->decoder) |
|
return; |
|
|
|
ct = hw->decoder->control.code_type; |
|
|
|
ir_status = img_ir_read(priv, IMG_IR_STATUS); |
|
if (!(ir_status & (IMG_IR_RXDVAL | IMG_IR_RXDVALD2))) { |
|
if (!(priv->hw.ct_quirks[ct] & IMG_IR_QUIRK_CODE_IRQ) || |
|
hw->stopping) |
|
return; |
|
/* |
|
* The below functionality is added as a work around to stop |
|
* multiple Interrupts generated when an incomplete IR code is |
|
* received by the decoder. |
|
* The decoder generates rapid interrupts without actually |
|
* having received any new data. After a single interrupt it's |
|
* expected to clear up, but instead multiple interrupts are |
|
* rapidly generated. only way to get out of this loop is to |
|
* reset the control register after a short delay. |
|
*/ |
|
img_ir_write(priv, IMG_IR_CONTROL, 0); |
|
hw->quirk_suspend_irq = img_ir_read(priv, IMG_IR_IRQ_ENABLE); |
|
img_ir_write(priv, IMG_IR_IRQ_ENABLE, |
|
hw->quirk_suspend_irq & IMG_IR_IRQ_EDGE); |
|
|
|
/* Timer activated to re-enable the protocol. */ |
|
mod_timer(&hw->suspend_timer, |
|
jiffies + msecs_to_jiffies(5)); |
|
return; |
|
} |
|
ir_status &= ~(IMG_IR_RXDVAL | IMG_IR_RXDVALD2); |
|
img_ir_write(priv, IMG_IR_STATUS, ir_status); |
|
|
|
len = (ir_status & IMG_IR_RXDLEN) >> IMG_IR_RXDLEN_SHIFT; |
|
/* some versions report wrong length for certain code types */ |
|
if (hw->ct_quirks[ct] & IMG_IR_QUIRK_CODE_LEN_INCR) |
|
++len; |
|
|
|
lw = img_ir_read(priv, IMG_IR_DATA_LW); |
|
up = img_ir_read(priv, IMG_IR_DATA_UP); |
|
img_ir_handle_data(priv, len, (u64)up << 32 | lw); |
|
} |
|
|
|
void img_ir_setup_hw(struct img_ir_priv *priv) |
|
{ |
|
struct img_ir_decoder **decp; |
|
|
|
if (!priv->hw.rdev) |
|
return; |
|
|
|
/* Use the first available decoder (or disable stuff if NULL) */ |
|
for (decp = img_ir_decoders; *decp; ++decp) { |
|
const struct img_ir_decoder *dec = *decp; |
|
if (img_ir_decoder_compatible(priv, dec)) { |
|
img_ir_set_protocol(priv, dec->type); |
|
img_ir_set_decoder(priv, dec, 0); |
|
return; |
|
} |
|
} |
|
img_ir_set_decoder(priv, NULL, 0); |
|
} |
|
|
|
/** |
|
* img_ir_probe_hw_caps() - Probe capabilities of the hardware. |
|
* @priv: IR private data. |
|
*/ |
|
static void img_ir_probe_hw_caps(struct img_ir_priv *priv) |
|
{ |
|
struct img_ir_priv_hw *hw = &priv->hw; |
|
/* |
|
* When a version of the block becomes available without these quirks, |
|
* they'll have to depend on the core revision. |
|
*/ |
|
hw->ct_quirks[IMG_IR_CODETYPE_PULSELEN] |
|
|= IMG_IR_QUIRK_CODE_LEN_INCR; |
|
hw->ct_quirks[IMG_IR_CODETYPE_BIPHASE] |
|
|= IMG_IR_QUIRK_CODE_IRQ; |
|
hw->ct_quirks[IMG_IR_CODETYPE_2BITPULSEPOS] |
|
|= IMG_IR_QUIRK_CODE_BROKEN; |
|
} |
|
|
|
int img_ir_probe_hw(struct img_ir_priv *priv) |
|
{ |
|
struct img_ir_priv_hw *hw = &priv->hw; |
|
struct rc_dev *rdev; |
|
int error; |
|
|
|
/* Ensure hardware decoders have been preprocessed */ |
|
img_ir_init_decoders(); |
|
|
|
/* Probe hardware capabilities */ |
|
img_ir_probe_hw_caps(priv); |
|
|
|
/* Set up the end timer */ |
|
timer_setup(&hw->end_timer, img_ir_end_timer, 0); |
|
timer_setup(&hw->suspend_timer, img_ir_suspend_timer, 0); |
|
|
|
/* Register a clock notifier */ |
|
if (!IS_ERR(priv->clk)) { |
|
hw->clk_hz = clk_get_rate(priv->clk); |
|
#ifdef CONFIG_COMMON_CLK |
|
hw->clk_nb.notifier_call = img_ir_clk_notify; |
|
error = clk_notifier_register(priv->clk, &hw->clk_nb); |
|
if (error) |
|
dev_warn(priv->dev, |
|
"failed to register clock notifier\n"); |
|
#endif |
|
} else { |
|
hw->clk_hz = 32768; |
|
} |
|
|
|
/* Allocate hardware decoder */ |
|
hw->rdev = rdev = rc_allocate_device(RC_DRIVER_SCANCODE); |
|
if (!rdev) { |
|
dev_err(priv->dev, "cannot allocate input device\n"); |
|
error = -ENOMEM; |
|
goto err_alloc_rc; |
|
} |
|
rdev->priv = priv; |
|
rdev->map_name = RC_MAP_EMPTY; |
|
rdev->allowed_protocols = img_ir_allowed_protos(priv); |
|
rdev->device_name = "IMG Infrared Decoder"; |
|
rdev->s_filter = img_ir_set_normal_filter; |
|
rdev->s_wakeup_filter = img_ir_set_wakeup_filter; |
|
|
|
/* Register hardware decoder */ |
|
error = rc_register_device(rdev); |
|
if (error) { |
|
dev_err(priv->dev, "failed to register IR input device\n"); |
|
goto err_register_rc; |
|
} |
|
|
|
/* |
|
* Set this after rc_register_device as no protocols have been |
|
* registered yet. |
|
*/ |
|
rdev->change_protocol = img_ir_change_protocol; |
|
|
|
device_init_wakeup(priv->dev, 1); |
|
|
|
return 0; |
|
|
|
err_register_rc: |
|
img_ir_set_decoder(priv, NULL, 0); |
|
hw->rdev = NULL; |
|
rc_free_device(rdev); |
|
err_alloc_rc: |
|
#ifdef CONFIG_COMMON_CLK |
|
if (!IS_ERR(priv->clk)) |
|
clk_notifier_unregister(priv->clk, &hw->clk_nb); |
|
#endif |
|
return error; |
|
} |
|
|
|
void img_ir_remove_hw(struct img_ir_priv *priv) |
|
{ |
|
struct img_ir_priv_hw *hw = &priv->hw; |
|
struct rc_dev *rdev = hw->rdev; |
|
if (!rdev) |
|
return; |
|
img_ir_set_decoder(priv, NULL, 0); |
|
hw->rdev = NULL; |
|
rc_unregister_device(rdev); |
|
#ifdef CONFIG_COMMON_CLK |
|
if (!IS_ERR(priv->clk)) |
|
clk_notifier_unregister(priv->clk, &hw->clk_nb); |
|
#endif |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
int img_ir_suspend(struct device *dev) |
|
{ |
|
struct img_ir_priv *priv = dev_get_drvdata(dev); |
|
|
|
if (device_may_wakeup(dev) && img_ir_enable_wake(priv)) |
|
enable_irq_wake(priv->irq); |
|
return 0; |
|
} |
|
|
|
int img_ir_resume(struct device *dev) |
|
{ |
|
struct img_ir_priv *priv = dev_get_drvdata(dev); |
|
|
|
if (device_may_wakeup(dev) && img_ir_disable_wake(priv)) |
|
disable_irq_wake(priv->irq); |
|
return 0; |
|
} |
|
#endif /* CONFIG_PM_SLEEP */
|
|
|