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670 lines
16 KiB
670 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2018 Pengutronix, Oleksij Rempel <[email protected]> |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/firmware/imx/ipc.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/kernel.h> |
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#include <linux/mailbox_controller.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/slab.h> |
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#define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x))) |
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#define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x))) |
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#define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x))) |
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#define IMX_MU_xSR_BRDIP BIT(9) |
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/* General Purpose Interrupt Enable */ |
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#define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x))) |
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/* Receive Interrupt Enable */ |
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#define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x))) |
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/* Transmit Interrupt Enable */ |
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#define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x))) |
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/* General Purpose Interrupt Request */ |
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#define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x))) |
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#define IMX_MU_CHANS 16 |
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/* TX0/RX0/RXDB[0-3] */ |
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#define IMX_MU_SCU_CHANS 6 |
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#define IMX_MU_CHAN_NAME_SIZE 20 |
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enum imx_mu_chan_type { |
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IMX_MU_TYPE_TX, /* Tx */ |
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IMX_MU_TYPE_RX, /* Rx */ |
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IMX_MU_TYPE_TXDB, /* Tx doorbell */ |
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IMX_MU_TYPE_RXDB, /* Rx doorbell */ |
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}; |
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struct imx_sc_rpc_msg_max { |
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struct imx_sc_rpc_msg hdr; |
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u32 data[7]; |
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}; |
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struct imx_mu_con_priv { |
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unsigned int idx; |
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char irq_desc[IMX_MU_CHAN_NAME_SIZE]; |
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enum imx_mu_chan_type type; |
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struct mbox_chan *chan; |
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struct tasklet_struct txdb_tasklet; |
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}; |
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struct imx_mu_priv { |
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struct device *dev; |
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void __iomem *base; |
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spinlock_t xcr_lock; /* control register lock */ |
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struct mbox_controller mbox; |
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struct mbox_chan mbox_chans[IMX_MU_CHANS]; |
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struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; |
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const struct imx_mu_dcfg *dcfg; |
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struct clk *clk; |
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int irq; |
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u32 xcr; |
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bool side_b; |
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}; |
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struct imx_mu_dcfg { |
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int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data); |
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int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); |
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void (*init)(struct imx_mu_priv *priv); |
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u32 xTR[4]; /* Transmit Registers */ |
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u32 xRR[4]; /* Receive Registers */ |
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u32 xSR; /* Status Register */ |
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u32 xCR; /* Control Register */ |
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}; |
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static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) |
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{ |
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return container_of(mbox, struct imx_mu_priv, mbox); |
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} |
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static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs) |
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{ |
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iowrite32(val, priv->base + offs); |
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} |
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static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs) |
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{ |
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return ioread32(priv->base + offs); |
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} |
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static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr) |
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{ |
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unsigned long flags; |
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u32 val; |
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spin_lock_irqsave(&priv->xcr_lock, flags); |
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val = imx_mu_read(priv, priv->dcfg->xCR); |
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val &= ~clr; |
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val |= set; |
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imx_mu_write(priv, val, priv->dcfg->xCR); |
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spin_unlock_irqrestore(&priv->xcr_lock, flags); |
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return val; |
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} |
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static int imx_mu_generic_tx(struct imx_mu_priv *priv, |
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struct imx_mu_con_priv *cp, |
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void *data) |
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{ |
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u32 *arg = data; |
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switch (cp->type) { |
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case IMX_MU_TYPE_TX: |
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imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]); |
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); |
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break; |
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case IMX_MU_TYPE_TXDB: |
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0); |
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tasklet_schedule(&cp->txdb_tasklet); |
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break; |
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default: |
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dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int imx_mu_generic_rx(struct imx_mu_priv *priv, |
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struct imx_mu_con_priv *cp) |
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{ |
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u32 dat; |
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dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]); |
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mbox_chan_received_data(cp->chan, (void *)&dat); |
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return 0; |
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} |
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static int imx_mu_scu_tx(struct imx_mu_priv *priv, |
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struct imx_mu_con_priv *cp, |
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void *data) |
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{ |
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struct imx_sc_rpc_msg_max *msg = data; |
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u32 *arg = data; |
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int i, ret; |
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u32 xsr; |
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switch (cp->type) { |
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case IMX_MU_TYPE_TX: |
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/* |
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* msg->hdr.size specifies the number of u32 words while |
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* sizeof yields bytes. |
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*/ |
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if (msg->hdr.size > sizeof(*msg) / 4) { |
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/* |
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* The real message size can be different to |
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* struct imx_sc_rpc_msg_max size |
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*/ |
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dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg), msg->hdr.size << 2); |
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return -EINVAL; |
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} |
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for (i = 0; i < 4 && i < msg->hdr.size; i++) |
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imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]); |
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for (; i < msg->hdr.size; i++) { |
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ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, |
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xsr, |
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xsr & IMX_MU_xSR_TEn(i % 4), |
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0, 100); |
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if (ret) { |
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dev_err(priv->dev, "Send data index: %d timeout\n", i); |
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return ret; |
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} |
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imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]); |
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} |
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); |
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break; |
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default: |
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dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int imx_mu_scu_rx(struct imx_mu_priv *priv, |
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struct imx_mu_con_priv *cp) |
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{ |
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struct imx_sc_rpc_msg_max msg; |
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u32 *data = (u32 *)&msg; |
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int i, ret; |
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u32 xsr; |
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imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0)); |
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*data++ = imx_mu_read(priv, priv->dcfg->xRR[0]); |
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if (msg.hdr.size > sizeof(msg) / 4) { |
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dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2); |
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return -EINVAL; |
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} |
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for (i = 1; i < msg.hdr.size; i++) { |
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ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr, |
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xsr & IMX_MU_xSR_RFn(i % 4), 0, 100); |
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if (ret) { |
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dev_err(priv->dev, "timeout read idx %d\n", i); |
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return ret; |
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} |
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*data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]); |
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} |
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0); |
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mbox_chan_received_data(cp->chan, (void *)&msg); |
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return 0; |
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} |
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static void imx_mu_txdb_tasklet(unsigned long data) |
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{ |
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struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data; |
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mbox_chan_txdone(cp->chan, 0); |
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} |
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static irqreturn_t imx_mu_isr(int irq, void *p) |
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{ |
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struct mbox_chan *chan = p; |
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struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); |
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struct imx_mu_con_priv *cp = chan->con_priv; |
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u32 val, ctrl; |
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ctrl = imx_mu_read(priv, priv->dcfg->xCR); |
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val = imx_mu_read(priv, priv->dcfg->xSR); |
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switch (cp->type) { |
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case IMX_MU_TYPE_TX: |
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val &= IMX_MU_xSR_TEn(cp->idx) & |
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(ctrl & IMX_MU_xCR_TIEn(cp->idx)); |
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break; |
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case IMX_MU_TYPE_RX: |
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val &= IMX_MU_xSR_RFn(cp->idx) & |
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(ctrl & IMX_MU_xCR_RIEn(cp->idx)); |
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break; |
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case IMX_MU_TYPE_RXDB: |
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val &= IMX_MU_xSR_GIPn(cp->idx) & |
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(ctrl & IMX_MU_xCR_GIEn(cp->idx)); |
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break; |
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default: |
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break; |
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} |
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if (!val) |
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return IRQ_NONE; |
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if (val == IMX_MU_xSR_TEn(cp->idx)) { |
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imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); |
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mbox_chan_txdone(chan, 0); |
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} else if (val == IMX_MU_xSR_RFn(cp->idx)) { |
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priv->dcfg->rx(priv, cp); |
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} else if (val == IMX_MU_xSR_GIPn(cp->idx)) { |
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imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR); |
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mbox_chan_received_data(chan, NULL); |
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} else { |
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dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); |
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return IRQ_NONE; |
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} |
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return IRQ_HANDLED; |
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} |
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static int imx_mu_send_data(struct mbox_chan *chan, void *data) |
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{ |
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struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); |
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struct imx_mu_con_priv *cp = chan->con_priv; |
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return priv->dcfg->tx(priv, cp, data); |
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} |
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static int imx_mu_startup(struct mbox_chan *chan) |
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{ |
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struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); |
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struct imx_mu_con_priv *cp = chan->con_priv; |
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unsigned long irq_flag = IRQF_SHARED; |
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int ret; |
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pm_runtime_get_sync(priv->dev); |
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if (cp->type == IMX_MU_TYPE_TXDB) { |
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/* Tx doorbell don't have ACK support */ |
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tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet, |
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(unsigned long)cp); |
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return 0; |
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} |
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/* IPC MU should be with IRQF_NO_SUSPEND set */ |
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if (!priv->dev->pm_domain) |
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irq_flag |= IRQF_NO_SUSPEND; |
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ret = request_irq(priv->irq, imx_mu_isr, irq_flag, |
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cp->irq_desc, chan); |
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if (ret) { |
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dev_err(priv->dev, |
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"Unable to acquire IRQ %d\n", priv->irq); |
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return ret; |
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} |
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switch (cp->type) { |
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case IMX_MU_TYPE_RX: |
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0); |
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break; |
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case IMX_MU_TYPE_RXDB: |
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0); |
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break; |
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default: |
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break; |
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} |
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return 0; |
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} |
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static void imx_mu_shutdown(struct mbox_chan *chan) |
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{ |
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struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); |
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struct imx_mu_con_priv *cp = chan->con_priv; |
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if (cp->type == IMX_MU_TYPE_TXDB) { |
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tasklet_kill(&cp->txdb_tasklet); |
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pm_runtime_put_sync(priv->dev); |
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return; |
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} |
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switch (cp->type) { |
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case IMX_MU_TYPE_TX: |
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imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); |
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break; |
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case IMX_MU_TYPE_RX: |
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imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx)); |
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break; |
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case IMX_MU_TYPE_RXDB: |
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imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx)); |
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break; |
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default: |
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break; |
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} |
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free_irq(priv->irq, chan); |
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pm_runtime_put_sync(priv->dev); |
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} |
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static const struct mbox_chan_ops imx_mu_ops = { |
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.send_data = imx_mu_send_data, |
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.startup = imx_mu_startup, |
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.shutdown = imx_mu_shutdown, |
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}; |
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static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox, |
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const struct of_phandle_args *sp) |
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{ |
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u32 type, idx, chan; |
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if (sp->args_count != 2) { |
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dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); |
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return ERR_PTR(-EINVAL); |
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} |
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type = sp->args[0]; /* channel type */ |
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idx = sp->args[1]; /* index */ |
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switch (type) { |
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case IMX_MU_TYPE_TX: |
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case IMX_MU_TYPE_RX: |
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if (idx != 0) |
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dev_err(mbox->dev, "Invalid chan idx: %d\n", idx); |
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chan = type; |
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break; |
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case IMX_MU_TYPE_RXDB: |
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chan = 2 + idx; |
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break; |
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default: |
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dev_err(mbox->dev, "Invalid chan type: %d\n", type); |
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return ERR_PTR(-EINVAL); |
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} |
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if (chan >= mbox->num_chans) { |
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dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); |
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return ERR_PTR(-EINVAL); |
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} |
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return &mbox->chans[chan]; |
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} |
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static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox, |
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const struct of_phandle_args *sp) |
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{ |
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u32 type, idx, chan; |
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if (sp->args_count != 2) { |
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dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); |
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return ERR_PTR(-EINVAL); |
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} |
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type = sp->args[0]; /* channel type */ |
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idx = sp->args[1]; /* index */ |
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chan = type * 4 + idx; |
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if (chan >= mbox->num_chans) { |
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dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); |
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return ERR_PTR(-EINVAL); |
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} |
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return &mbox->chans[chan]; |
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} |
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static void imx_mu_init_generic(struct imx_mu_priv *priv) |
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{ |
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unsigned int i; |
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for (i = 0; i < IMX_MU_CHANS; i++) { |
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struct imx_mu_con_priv *cp = &priv->con_priv[i]; |
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cp->idx = i % 4; |
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cp->type = i >> 2; |
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cp->chan = &priv->mbox_chans[i]; |
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priv->mbox_chans[i].con_priv = cp; |
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snprintf(cp->irq_desc, sizeof(cp->irq_desc), |
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"imx_mu_chan[%i-%i]", cp->type, cp->idx); |
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} |
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priv->mbox.num_chans = IMX_MU_CHANS; |
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priv->mbox.of_xlate = imx_mu_xlate; |
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if (priv->side_b) |
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return; |
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/* Set default MU configuration */ |
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imx_mu_write(priv, 0, priv->dcfg->xCR); |
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} |
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static void imx_mu_init_scu(struct imx_mu_priv *priv) |
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{ |
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unsigned int i; |
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for (i = 0; i < IMX_MU_SCU_CHANS; i++) { |
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struct imx_mu_con_priv *cp = &priv->con_priv[i]; |
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cp->idx = i < 2 ? 0 : i - 2; |
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cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB; |
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cp->chan = &priv->mbox_chans[i]; |
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priv->mbox_chans[i].con_priv = cp; |
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snprintf(cp->irq_desc, sizeof(cp->irq_desc), |
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"imx_mu_chan[%i-%i]", cp->type, cp->idx); |
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} |
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priv->mbox.num_chans = IMX_MU_SCU_CHANS; |
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priv->mbox.of_xlate = imx_mu_scu_xlate; |
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/* Set default MU configuration */ |
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imx_mu_write(priv, 0, priv->dcfg->xCR); |
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} |
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static int imx_mu_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *np = dev->of_node; |
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struct imx_mu_priv *priv; |
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const struct imx_mu_dcfg *dcfg; |
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int ret; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->dev = dev; |
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priv->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(priv->base)) |
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return PTR_ERR(priv->base); |
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priv->irq = platform_get_irq(pdev, 0); |
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if (priv->irq < 0) |
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return priv->irq; |
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dcfg = of_device_get_match_data(dev); |
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if (!dcfg) |
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return -EINVAL; |
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priv->dcfg = dcfg; |
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priv->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(priv->clk)) { |
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if (PTR_ERR(priv->clk) != -ENOENT) |
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return PTR_ERR(priv->clk); |
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priv->clk = NULL; |
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} |
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ret = clk_prepare_enable(priv->clk); |
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if (ret) { |
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dev_err(dev, "Failed to enable clock\n"); |
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return ret; |
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} |
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priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); |
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priv->dcfg->init(priv); |
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spin_lock_init(&priv->xcr_lock); |
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priv->mbox.dev = dev; |
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priv->mbox.ops = &imx_mu_ops; |
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priv->mbox.chans = priv->mbox_chans; |
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priv->mbox.txdone_irq = true; |
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platform_set_drvdata(pdev, priv); |
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ret = devm_mbox_controller_register(dev, &priv->mbox); |
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if (ret) { |
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clk_disable_unprepare(priv->clk); |
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return ret; |
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} |
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pm_runtime_enable(dev); |
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ret = pm_runtime_get_sync(dev); |
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if (ret < 0) { |
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pm_runtime_put_noidle(dev); |
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goto disable_runtime_pm; |
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} |
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ret = pm_runtime_put_sync(dev); |
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if (ret < 0) |
|
goto disable_runtime_pm; |
|
|
|
clk_disable_unprepare(priv->clk); |
|
|
|
return 0; |
|
|
|
disable_runtime_pm: |
|
pm_runtime_disable(dev); |
|
clk_disable_unprepare(priv->clk); |
|
return ret; |
|
} |
|
|
|
static int imx_mu_remove(struct platform_device *pdev) |
|
{ |
|
struct imx_mu_priv *priv = platform_get_drvdata(pdev); |
|
|
|
pm_runtime_disable(priv->dev); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { |
|
.tx = imx_mu_generic_tx, |
|
.rx = imx_mu_generic_rx, |
|
.init = imx_mu_init_generic, |
|
.xTR = {0x0, 0x4, 0x8, 0xc}, |
|
.xRR = {0x10, 0x14, 0x18, 0x1c}, |
|
.xSR = 0x20, |
|
.xCR = 0x24, |
|
}; |
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { |
|
.tx = imx_mu_generic_tx, |
|
.rx = imx_mu_generic_rx, |
|
.init = imx_mu_init_generic, |
|
.xTR = {0x20, 0x24, 0x28, 0x2c}, |
|
.xRR = {0x40, 0x44, 0x48, 0x4c}, |
|
.xSR = 0x60, |
|
.xCR = 0x64, |
|
}; |
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = { |
|
.tx = imx_mu_scu_tx, |
|
.rx = imx_mu_scu_rx, |
|
.init = imx_mu_init_scu, |
|
.xTR = {0x0, 0x4, 0x8, 0xc}, |
|
.xRR = {0x10, 0x14, 0x18, 0x1c}, |
|
.xSR = 0x20, |
|
.xCR = 0x24, |
|
}; |
|
|
|
static const struct of_device_id imx_mu_dt_ids[] = { |
|
{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp }, |
|
{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx }, |
|
{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); |
|
|
|
static int __maybe_unused imx_mu_suspend_noirq(struct device *dev) |
|
{ |
|
struct imx_mu_priv *priv = dev_get_drvdata(dev); |
|
|
|
if (!priv->clk) |
|
priv->xcr = imx_mu_read(priv, priv->dcfg->xCR); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused imx_mu_resume_noirq(struct device *dev) |
|
{ |
|
struct imx_mu_priv *priv = dev_get_drvdata(dev); |
|
|
|
/* |
|
* ONLY restore MU when context lost, the TIE could |
|
* be set during noirq resume as there is MU data |
|
* communication going on, and restore the saved |
|
* value will overwrite the TIE and cause MU data |
|
* send failed, may lead to system freeze. This issue |
|
* is observed by testing freeze mode suspend. |
|
*/ |
|
if (!imx_mu_read(priv, priv->dcfg->xCR) && !priv->clk) |
|
imx_mu_write(priv, priv->xcr, priv->dcfg->xCR); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused imx_mu_runtime_suspend(struct device *dev) |
|
{ |
|
struct imx_mu_priv *priv = dev_get_drvdata(dev); |
|
|
|
clk_disable_unprepare(priv->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused imx_mu_runtime_resume(struct device *dev) |
|
{ |
|
struct imx_mu_priv *priv = dev_get_drvdata(dev); |
|
int ret; |
|
|
|
ret = clk_prepare_enable(priv->clk); |
|
if (ret) |
|
dev_err(dev, "failed to enable clock\n"); |
|
|
|
return ret; |
|
} |
|
|
|
static const struct dev_pm_ops imx_mu_pm_ops = { |
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq, |
|
imx_mu_resume_noirq) |
|
SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend, |
|
imx_mu_runtime_resume, NULL) |
|
}; |
|
|
|
static struct platform_driver imx_mu_driver = { |
|
.probe = imx_mu_probe, |
|
.remove = imx_mu_remove, |
|
.driver = { |
|
.name = "imx_mu", |
|
.of_match_table = imx_mu_dt_ids, |
|
.pm = &imx_mu_pm_ops, |
|
}, |
|
}; |
|
module_platform_driver(imx_mu_driver); |
|
|
|
MODULE_AUTHOR("Oleksij Rempel <[email protected]>"); |
|
MODULE_DESCRIPTION("Message Unit driver for i.MX"); |
|
MODULE_LICENSE("GPL v2");
|
|
|