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206 lines
5.1 KiB
206 lines
5.1 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* rWTM BIU Mailbox driver for Armada 37xx |
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* |
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* Author: Marek Behún <[email protected]> |
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*/ |
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#include <linux/device.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/mailbox_controller.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/armada-37xx-rwtm-mailbox.h> |
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#define DRIVER_NAME "armada-37xx-rwtm-mailbox" |
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/* relative to rWTM BIU Mailbox Registers */ |
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#define RWTM_MBOX_PARAM(i) (0x0 + ((i) << 2)) |
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#define RWTM_MBOX_COMMAND 0x40 |
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#define RWTM_MBOX_RETURN_STATUS 0x80 |
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#define RWTM_MBOX_STATUS(i) (0x84 + ((i) << 2)) |
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#define RWTM_MBOX_FIFO_STATUS 0xc4 |
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#define FIFO_STS_RDY 0x100 |
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#define FIFO_STS_CNTR_MASK 0x7 |
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#define FIFO_STS_CNTR_MAX 4 |
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#define RWTM_HOST_INT_RESET 0xc8 |
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#define RWTM_HOST_INT_MASK 0xcc |
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#define SP_CMD_COMPLETE BIT(0) |
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#define SP_CMD_QUEUE_FULL_ACCESS BIT(17) |
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#define SP_CMD_QUEUE_FULL BIT(18) |
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struct a37xx_mbox { |
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struct device *dev; |
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struct mbox_controller controller; |
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void __iomem *base; |
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int irq; |
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}; |
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static void a37xx_mbox_receive(struct mbox_chan *chan) |
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{ |
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struct a37xx_mbox *mbox = chan->con_priv; |
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struct armada_37xx_rwtm_rx_msg rx_msg; |
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int i; |
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rx_msg.retval = readl(mbox->base + RWTM_MBOX_RETURN_STATUS); |
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for (i = 0; i < 16; ++i) |
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rx_msg.status[i] = readl(mbox->base + RWTM_MBOX_STATUS(i)); |
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mbox_chan_received_data(chan, &rx_msg); |
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} |
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static irqreturn_t a37xx_mbox_irq_handler(int irq, void *data) |
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{ |
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struct mbox_chan *chan = data; |
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struct a37xx_mbox *mbox = chan->con_priv; |
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u32 reg; |
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reg = readl(mbox->base + RWTM_HOST_INT_RESET); |
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if (reg & SP_CMD_COMPLETE) |
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a37xx_mbox_receive(chan); |
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if (reg & (SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL)) |
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dev_err(mbox->dev, "Secure processor command queue full\n"); |
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writel(reg, mbox->base + RWTM_HOST_INT_RESET); |
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if (reg) |
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mbox_chan_txdone(chan, 0); |
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return reg ? IRQ_HANDLED : IRQ_NONE; |
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} |
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static int a37xx_mbox_send_data(struct mbox_chan *chan, void *data) |
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{ |
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struct a37xx_mbox *mbox = chan->con_priv; |
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struct armada_37xx_rwtm_tx_msg *msg = data; |
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int i; |
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u32 reg; |
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if (!data) |
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return -EINVAL; |
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reg = readl(mbox->base + RWTM_MBOX_FIFO_STATUS); |
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if (!(reg & FIFO_STS_RDY)) |
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dev_warn(mbox->dev, "Secure processor not ready\n"); |
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if ((reg & FIFO_STS_CNTR_MASK) >= FIFO_STS_CNTR_MAX) { |
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dev_err(mbox->dev, "Secure processor command queue full\n"); |
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return -EBUSY; |
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} |
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for (i = 0; i < 16; ++i) |
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writel(msg->args[i], mbox->base + RWTM_MBOX_PARAM(i)); |
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writel(msg->command, mbox->base + RWTM_MBOX_COMMAND); |
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return 0; |
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} |
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static int a37xx_mbox_startup(struct mbox_chan *chan) |
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{ |
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struct a37xx_mbox *mbox = chan->con_priv; |
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u32 reg; |
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int ret; |
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ret = devm_request_irq(mbox->dev, mbox->irq, a37xx_mbox_irq_handler, 0, |
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DRIVER_NAME, chan); |
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if (ret < 0) { |
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dev_err(mbox->dev, "Cannot request irq\n"); |
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return ret; |
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} |
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/* enable IRQ generation */ |
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reg = readl(mbox->base + RWTM_HOST_INT_MASK); |
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reg &= ~(SP_CMD_COMPLETE | SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL); |
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writel(reg, mbox->base + RWTM_HOST_INT_MASK); |
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return 0; |
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} |
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static void a37xx_mbox_shutdown(struct mbox_chan *chan) |
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{ |
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u32 reg; |
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struct a37xx_mbox *mbox = chan->con_priv; |
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/* disable interrupt generation */ |
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reg = readl(mbox->base + RWTM_HOST_INT_MASK); |
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reg |= SP_CMD_COMPLETE | SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL; |
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writel(reg, mbox->base + RWTM_HOST_INT_MASK); |
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devm_free_irq(mbox->dev, mbox->irq, chan); |
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} |
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static const struct mbox_chan_ops a37xx_mbox_ops = { |
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.send_data = a37xx_mbox_send_data, |
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.startup = a37xx_mbox_startup, |
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.shutdown = a37xx_mbox_shutdown, |
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}; |
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static int armada_37xx_mbox_probe(struct platform_device *pdev) |
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{ |
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struct a37xx_mbox *mbox; |
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struct mbox_chan *chans; |
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int ret; |
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mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL); |
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if (!mbox) |
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return -ENOMEM; |
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/* Allocated one channel */ |
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chans = devm_kzalloc(&pdev->dev, sizeof(*chans), GFP_KERNEL); |
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if (!chans) |
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return -ENOMEM; |
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mbox->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(mbox->base)) |
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return PTR_ERR(mbox->base); |
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mbox->irq = platform_get_irq(pdev, 0); |
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if (mbox->irq < 0) |
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return mbox->irq; |
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mbox->dev = &pdev->dev; |
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/* Hardware supports only one channel. */ |
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chans[0].con_priv = mbox; |
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mbox->controller.dev = mbox->dev; |
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mbox->controller.num_chans = 1; |
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mbox->controller.chans = chans; |
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mbox->controller.ops = &a37xx_mbox_ops; |
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mbox->controller.txdone_irq = true; |
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ret = devm_mbox_controller_register(mbox->dev, &mbox->controller); |
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if (ret) { |
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dev_err(&pdev->dev, "Could not register mailbox controller\n"); |
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return ret; |
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} |
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platform_set_drvdata(pdev, mbox); |
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return ret; |
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} |
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static const struct of_device_id armada_37xx_mbox_match[] = { |
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{ .compatible = "marvell,armada-3700-rwtm-mailbox" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, armada_37xx_mbox_match); |
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static struct platform_driver armada_37xx_mbox_driver = { |
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.probe = armada_37xx_mbox_probe, |
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.driver = { |
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.name = DRIVER_NAME, |
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.of_match_table = armada_37xx_mbox_match, |
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}, |
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}; |
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module_platform_driver(armada_37xx_mbox_driver); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_DESCRIPTION("rWTM BIU Mailbox driver for Armada 37xx"); |
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MODULE_AUTHOR("Marek Behun <[email protected]>");
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