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413 lines
11 KiB
413 lines
11 KiB
/* |
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* Copyright (C) 2017 Marvell |
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* |
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* Hanna Hawa <[email protected]> |
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* Thomas Petazzoni <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqdomain.h> |
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#include <linux/jump_label.h> |
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#include <linux/kernel.h> |
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#include <linux/msi.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <dt-bindings/interrupt-controller/mvebu-icu.h> |
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/* ICU registers */ |
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#define ICU_SETSPI_NSR_AL 0x10 |
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#define ICU_SETSPI_NSR_AH 0x14 |
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#define ICU_CLRSPI_NSR_AL 0x18 |
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#define ICU_CLRSPI_NSR_AH 0x1c |
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#define ICU_SET_SEI_AL 0x50 |
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#define ICU_SET_SEI_AH 0x54 |
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#define ICU_CLR_SEI_AL 0x58 |
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#define ICU_CLR_SEI_AH 0x5C |
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#define ICU_INT_CFG(x) (0x100 + 4 * (x)) |
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#define ICU_INT_ENABLE BIT(24) |
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#define ICU_IS_EDGE BIT(28) |
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#define ICU_GROUP_SHIFT 29 |
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/* ICU definitions */ |
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#define ICU_MAX_IRQS 207 |
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#define ICU_SATA0_ICU_ID 109 |
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#define ICU_SATA1_ICU_ID 107 |
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struct mvebu_icu_subset_data { |
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unsigned int icu_group; |
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unsigned int offset_set_ah; |
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unsigned int offset_set_al; |
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unsigned int offset_clr_ah; |
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unsigned int offset_clr_al; |
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}; |
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struct mvebu_icu { |
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void __iomem *base; |
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struct device *dev; |
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}; |
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struct mvebu_icu_msi_data { |
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struct mvebu_icu *icu; |
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atomic_t initialized; |
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const struct mvebu_icu_subset_data *subset_data; |
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}; |
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struct mvebu_icu_irq_data { |
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struct mvebu_icu *icu; |
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unsigned int icu_group; |
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unsigned int type; |
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}; |
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static DEFINE_STATIC_KEY_FALSE(legacy_bindings); |
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static void mvebu_icu_init(struct mvebu_icu *icu, |
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struct mvebu_icu_msi_data *msi_data, |
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struct msi_msg *msg) |
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{ |
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const struct mvebu_icu_subset_data *subset = msi_data->subset_data; |
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if (atomic_cmpxchg(&msi_data->initialized, false, true)) |
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return; |
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/* Set 'SET' ICU SPI message address in AP */ |
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writel_relaxed(msg[0].address_hi, icu->base + subset->offset_set_ah); |
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writel_relaxed(msg[0].address_lo, icu->base + subset->offset_set_al); |
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if (subset->icu_group != ICU_GRP_NSR) |
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return; |
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/* Set 'CLEAR' ICU SPI message address in AP (level-MSI only) */ |
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writel_relaxed(msg[1].address_hi, icu->base + subset->offset_clr_ah); |
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writel_relaxed(msg[1].address_lo, icu->base + subset->offset_clr_al); |
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} |
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static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg) |
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{ |
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struct irq_data *d = irq_get_irq_data(desc->irq); |
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struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d->domain); |
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struct mvebu_icu_irq_data *icu_irqd = d->chip_data; |
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struct mvebu_icu *icu = icu_irqd->icu; |
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unsigned int icu_int; |
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if (msg->address_lo || msg->address_hi) { |
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/* One off initialization per domain */ |
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mvebu_icu_init(icu, msi_data, msg); |
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/* Configure the ICU with irq number & type */ |
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icu_int = msg->data | ICU_INT_ENABLE; |
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if (icu_irqd->type & IRQ_TYPE_EDGE_RISING) |
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icu_int |= ICU_IS_EDGE; |
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icu_int |= icu_irqd->icu_group << ICU_GROUP_SHIFT; |
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} else { |
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/* De-configure the ICU */ |
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icu_int = 0; |
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} |
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writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq)); |
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/* |
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* The SATA unit has 2 ports, and a dedicated ICU entry per |
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* port. The ahci sata driver supports only one irq interrupt |
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* per SATA unit. To solve this conflict, we configure the 2 |
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* SATA wired interrupts in the south bridge into 1 GIC |
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* interrupt in the north bridge. Even if only a single port |
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* is enabled, if sata node is enabled, both interrupts are |
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* configured (regardless of which port is actually in use). |
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*/ |
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if (d->hwirq == ICU_SATA0_ICU_ID || d->hwirq == ICU_SATA1_ICU_ID) { |
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writel_relaxed(icu_int, |
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icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID)); |
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writel_relaxed(icu_int, |
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icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID)); |
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} |
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} |
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static struct irq_chip mvebu_icu_nsr_chip = { |
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.name = "ICU-NSR", |
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.irq_mask = irq_chip_mask_parent, |
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.irq_unmask = irq_chip_unmask_parent, |
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.irq_eoi = irq_chip_eoi_parent, |
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.irq_set_type = irq_chip_set_type_parent, |
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.irq_set_affinity = irq_chip_set_affinity_parent, |
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}; |
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static struct irq_chip mvebu_icu_sei_chip = { |
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.name = "ICU-SEI", |
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.irq_ack = irq_chip_ack_parent, |
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.irq_mask = irq_chip_mask_parent, |
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.irq_unmask = irq_chip_unmask_parent, |
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.irq_set_type = irq_chip_set_type_parent, |
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.irq_set_affinity = irq_chip_set_affinity_parent, |
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}; |
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static int |
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mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, |
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unsigned long *hwirq, unsigned int *type) |
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{ |
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struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d); |
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struct mvebu_icu *icu = platform_msi_get_host_data(d); |
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unsigned int param_count = static_branch_unlikely(&legacy_bindings) ? 3 : 2; |
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/* Check the count of the parameters in dt */ |
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if (WARN_ON(fwspec->param_count != param_count)) { |
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dev_err(icu->dev, "wrong ICU parameter count %d\n", |
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fwspec->param_count); |
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return -EINVAL; |
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} |
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if (static_branch_unlikely(&legacy_bindings)) { |
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*hwirq = fwspec->param[1]; |
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*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; |
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if (fwspec->param[0] != ICU_GRP_NSR) { |
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dev_err(icu->dev, "wrong ICU group type %x\n", |
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fwspec->param[0]); |
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return -EINVAL; |
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} |
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} else { |
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*hwirq = fwspec->param[0]; |
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*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; |
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/* |
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* The ICU receives level interrupts. While the NSR are also |
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* level interrupts, SEI are edge interrupts. Force the type |
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* here in this case. Please note that this makes the interrupt |
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* handling unreliable. |
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*/ |
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if (msi_data->subset_data->icu_group == ICU_GRP_SEI) |
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*type = IRQ_TYPE_EDGE_RISING; |
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} |
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if (*hwirq >= ICU_MAX_IRQS) { |
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dev_err(icu->dev, "invalid interrupt number %ld\n", *hwirq); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int |
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mvebu_icu_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
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unsigned int nr_irqs, void *args) |
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{ |
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int err; |
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unsigned long hwirq; |
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struct irq_fwspec *fwspec = args; |
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struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(domain); |
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struct mvebu_icu *icu = msi_data->icu; |
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struct mvebu_icu_irq_data *icu_irqd; |
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struct irq_chip *chip = &mvebu_icu_nsr_chip; |
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icu_irqd = kmalloc(sizeof(*icu_irqd), GFP_KERNEL); |
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if (!icu_irqd) |
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return -ENOMEM; |
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err = mvebu_icu_irq_domain_translate(domain, fwspec, &hwirq, |
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&icu_irqd->type); |
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if (err) { |
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dev_err(icu->dev, "failed to translate ICU parameters\n"); |
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goto free_irqd; |
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} |
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if (static_branch_unlikely(&legacy_bindings)) |
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icu_irqd->icu_group = fwspec->param[0]; |
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else |
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icu_irqd->icu_group = msi_data->subset_data->icu_group; |
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icu_irqd->icu = icu; |
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err = platform_msi_domain_alloc(domain, virq, nr_irqs); |
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if (err) { |
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dev_err(icu->dev, "failed to allocate ICU interrupt in parent domain\n"); |
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goto free_irqd; |
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} |
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/* Make sure there is no interrupt left pending by the firmware */ |
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err = irq_set_irqchip_state(virq, IRQCHIP_STATE_PENDING, false); |
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if (err) |
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goto free_msi; |
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if (icu_irqd->icu_group == ICU_GRP_SEI) |
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chip = &mvebu_icu_sei_chip; |
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err = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, |
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chip, icu_irqd); |
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if (err) { |
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dev_err(icu->dev, "failed to set the data to IRQ domain\n"); |
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goto free_msi; |
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} |
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return 0; |
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free_msi: |
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platform_msi_domain_free(domain, virq, nr_irqs); |
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free_irqd: |
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kfree(icu_irqd); |
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return err; |
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} |
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static void |
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mvebu_icu_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
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unsigned int nr_irqs) |
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{ |
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struct irq_data *d = irq_get_irq_data(virq); |
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struct mvebu_icu_irq_data *icu_irqd = d->chip_data; |
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kfree(icu_irqd); |
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platform_msi_domain_free(domain, virq, nr_irqs); |
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} |
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static const struct irq_domain_ops mvebu_icu_domain_ops = { |
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.translate = mvebu_icu_irq_domain_translate, |
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.alloc = mvebu_icu_irq_domain_alloc, |
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.free = mvebu_icu_irq_domain_free, |
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}; |
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static const struct mvebu_icu_subset_data mvebu_icu_nsr_subset_data = { |
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.icu_group = ICU_GRP_NSR, |
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.offset_set_ah = ICU_SETSPI_NSR_AH, |
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.offset_set_al = ICU_SETSPI_NSR_AL, |
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.offset_clr_ah = ICU_CLRSPI_NSR_AH, |
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.offset_clr_al = ICU_CLRSPI_NSR_AL, |
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}; |
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static const struct mvebu_icu_subset_data mvebu_icu_sei_subset_data = { |
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.icu_group = ICU_GRP_SEI, |
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.offset_set_ah = ICU_SET_SEI_AH, |
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.offset_set_al = ICU_SET_SEI_AL, |
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}; |
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static const struct of_device_id mvebu_icu_subset_of_match[] = { |
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{ |
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.compatible = "marvell,cp110-icu-nsr", |
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.data = &mvebu_icu_nsr_subset_data, |
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}, |
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{ |
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.compatible = "marvell,cp110-icu-sei", |
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.data = &mvebu_icu_sei_subset_data, |
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}, |
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{}, |
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}; |
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static int mvebu_icu_subset_probe(struct platform_device *pdev) |
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{ |
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struct mvebu_icu_msi_data *msi_data; |
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struct device_node *msi_parent_dn; |
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struct device *dev = &pdev->dev; |
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struct irq_domain *irq_domain; |
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msi_data = devm_kzalloc(dev, sizeof(*msi_data), GFP_KERNEL); |
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if (!msi_data) |
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return -ENOMEM; |
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if (static_branch_unlikely(&legacy_bindings)) { |
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msi_data->icu = dev_get_drvdata(dev); |
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msi_data->subset_data = &mvebu_icu_nsr_subset_data; |
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} else { |
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msi_data->icu = dev_get_drvdata(dev->parent); |
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msi_data->subset_data = of_device_get_match_data(dev); |
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} |
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dev->msi_domain = of_msi_get_domain(dev, dev->of_node, |
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DOMAIN_BUS_PLATFORM_MSI); |
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if (!dev->msi_domain) |
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return -EPROBE_DEFER; |
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msi_parent_dn = irq_domain_get_of_node(dev->msi_domain); |
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if (!msi_parent_dn) |
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return -ENODEV; |
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irq_domain = platform_msi_create_device_tree_domain(dev, ICU_MAX_IRQS, |
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mvebu_icu_write_msg, |
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&mvebu_icu_domain_ops, |
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msi_data); |
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if (!irq_domain) { |
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dev_err(dev, "Failed to create ICU MSI domain\n"); |
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return -ENOMEM; |
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} |
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return 0; |
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} |
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static struct platform_driver mvebu_icu_subset_driver = { |
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.probe = mvebu_icu_subset_probe, |
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.driver = { |
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.name = "mvebu-icu-subset", |
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.of_match_table = mvebu_icu_subset_of_match, |
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}, |
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}; |
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builtin_platform_driver(mvebu_icu_subset_driver); |
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static int mvebu_icu_probe(struct platform_device *pdev) |
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{ |
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struct mvebu_icu *icu; |
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struct resource *res; |
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int i; |
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icu = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_icu), |
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GFP_KERNEL); |
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if (!icu) |
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return -ENOMEM; |
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icu->dev = &pdev->dev; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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icu->base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(icu->base)) { |
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dev_err(&pdev->dev, "Failed to map icu base address.\n"); |
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return PTR_ERR(icu->base); |
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} |
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/* |
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* Legacy bindings: ICU is one node with one MSI parent: force manually |
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* the probe of the NSR interrupts side. |
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* New bindings: ICU node has children, one per interrupt controller |
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* having its own MSI parent: call platform_populate(). |
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* All ICU instances should use the same bindings. |
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*/ |
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if (!of_get_child_count(pdev->dev.of_node)) |
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static_branch_enable(&legacy_bindings); |
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/* |
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* Clean all ICU interrupts of type NSR and SEI, required to |
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* avoid unpredictable SPI assignments done by firmware. |
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*/ |
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for (i = 0 ; i < ICU_MAX_IRQS ; i++) { |
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u32 icu_int, icu_grp; |
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icu_int = readl_relaxed(icu->base + ICU_INT_CFG(i)); |
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icu_grp = icu_int >> ICU_GROUP_SHIFT; |
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if (icu_grp == ICU_GRP_NSR || |
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(icu_grp == ICU_GRP_SEI && |
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!static_branch_unlikely(&legacy_bindings))) |
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writel_relaxed(0x0, icu->base + ICU_INT_CFG(i)); |
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} |
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platform_set_drvdata(pdev, icu); |
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if (static_branch_unlikely(&legacy_bindings)) |
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return mvebu_icu_subset_probe(pdev); |
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else |
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return devm_of_platform_populate(&pdev->dev); |
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} |
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static const struct of_device_id mvebu_icu_of_match[] = { |
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{ .compatible = "marvell,cp110-icu", }, |
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{}, |
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}; |
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static struct platform_driver mvebu_icu_driver = { |
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.probe = mvebu_icu_probe, |
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.driver = { |
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.name = "mvebu-icu", |
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.of_match_table = mvebu_icu_of_match, |
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}, |
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}; |
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builtin_platform_driver(mvebu_icu_driver);
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