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353 lines
9.4 KiB
353 lines
9.4 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2010 Broadcom |
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* Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren |
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* |
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* Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits |
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* |
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* If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8 |
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* on bank 0 is set to signify that an interrupt in bank 1 has fired, and |
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* to look in the bank 1 status register for more information. |
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* |
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* If an interrupt fires on bank 1 that _is_ in the shortcuts list, its |
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* shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1 |
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* status register, but bank 0 bit 8 is _not_ set. |
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* |
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* Quirk 2: You can't mask the register 1/2 pending interrupts |
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* |
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* In a proper cascaded interrupt controller, the interrupt lines with |
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* cascaded interrupt controllers on them are just normal interrupt lines. |
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* You can mask the interrupts and get on with things. With this controller |
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* you can't do that. |
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* |
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* Quirk 3: The shortcut interrupts can't be (un)masked in bank 0 |
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* |
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* Those interrupts that have shortcuts can only be masked/unmasked in |
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* their respective banks' enable/disable registers. Doing so in the bank 0 |
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* enable/disable registers has no effect. |
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* |
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* The FIQ control register: |
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* Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0) |
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* Bit 7: Enable FIQ generation |
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* Bits 8+: Unused |
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* |
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* An interrupt must be disabled before configuring it for FIQ generation |
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* otherwise both handlers will fire at the same time! |
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*/ |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqdomain.h> |
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#include <asm/exception.h> |
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#ifndef CONFIG_ARM64 |
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#include <asm/mach/irq.h> |
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#endif |
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/* Put the bank and irq (32 bits) into the hwirq */ |
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#define MAKE_HWIRQ(b, n) (((b) << 5) | (n)) |
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#define HWIRQ_BANK(i) (i >> 5) |
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#define HWIRQ_BIT(i) BIT(i & 0x1f) |
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#define NR_IRQS_BANK0 8 |
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#define BANK0_HWIRQ_MASK 0xff |
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/* Shortcuts can't be disabled so any unknown new ones need to be masked */ |
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#define SHORTCUT1_MASK 0x00007c00 |
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#define SHORTCUT2_MASK 0x001f8000 |
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#define SHORTCUT_SHIFT 10 |
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#define BANK1_HWIRQ BIT(8) |
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#define BANK2_HWIRQ BIT(9) |
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#define BANK0_VALID_MASK (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \ |
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| SHORTCUT1_MASK | SHORTCUT2_MASK) |
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#undef ARM_LOCAL_GPU_INT_ROUTING |
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#define ARM_LOCAL_GPU_INT_ROUTING 0x0c |
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#define REG_FIQ_CONTROL 0x0c |
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#define FIQ_CONTROL_ENABLE BIT(7) |
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#define REG_FIQ_ENABLE FIQ_CONTROL_ENABLE |
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#define REG_FIQ_DISABLE 0 |
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#define NR_BANKS 3 |
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#define IRQS_PER_BANK 32 |
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#define NUMBER_IRQS MAKE_HWIRQ(NR_BANKS, 0) |
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static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 }; |
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static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 }; |
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static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 }; |
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static const int bank_irqs[] __initconst = { 8, 32, 32 }; |
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static const int shortcuts[] = { |
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7, 9, 10, 18, 19, /* Bank 1 */ |
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21, 22, 23, 24, 25, 30 /* Bank 2 */ |
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}; |
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struct armctrl_ic { |
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void __iomem *base; |
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void __iomem *pending[NR_BANKS]; |
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void __iomem *enable[NR_BANKS]; |
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void __iomem *disable[NR_BANKS]; |
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struct irq_domain *domain; |
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void __iomem *local_base; |
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}; |
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static struct armctrl_ic intc __read_mostly; |
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static void __exception_irq_entry bcm2835_handle_irq( |
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struct pt_regs *regs); |
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static void bcm2836_chained_handle_irq(struct irq_desc *desc); |
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static inline unsigned int hwirq_to_fiq(unsigned long hwirq) |
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{ |
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hwirq -= NUMBER_IRQS; |
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/* |
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* The hwirq numbering used in this driver is: |
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* BASE (0-7) GPU1 (32-63) GPU2 (64-95). |
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* This differ from the one used in the FIQ register: |
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* GPU1 (0-31) GPU2 (32-63) BASE (64-71) |
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*/ |
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if (hwirq >= 32) |
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return hwirq - 32; |
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return hwirq + 64; |
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} |
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static void armctrl_mask_irq(struct irq_data *d) |
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{ |
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if (d->hwirq >= NUMBER_IRQS) |
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writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL); |
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else |
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writel_relaxed(HWIRQ_BIT(d->hwirq), |
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intc.disable[HWIRQ_BANK(d->hwirq)]); |
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} |
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static void armctrl_unmask_irq(struct irq_data *d) |
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{ |
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if (d->hwirq >= NUMBER_IRQS) { |
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if (num_online_cpus() > 1) { |
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unsigned int data; |
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if (!intc.local_base) { |
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pr_err("FIQ is disabled due to missing arm_local_intc\n"); |
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return; |
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} |
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data = readl_relaxed(intc.local_base + |
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ARM_LOCAL_GPU_INT_ROUTING); |
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data &= ~0xc; |
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data |= (1 << 2); |
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writel_relaxed(data, |
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intc.local_base + |
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ARM_LOCAL_GPU_INT_ROUTING); |
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} |
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writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq), |
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intc.base + REG_FIQ_CONTROL); |
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} else { |
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writel_relaxed(HWIRQ_BIT(d->hwirq), |
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intc.enable[HWIRQ_BANK(d->hwirq)]); |
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} |
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} |
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#ifdef CONFIG_ARM64 |
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void bcm2836_arm_irqchip_spin_gpu_irq(void); |
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static void armctrl_ack_irq(struct irq_data *d) |
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{ |
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bcm2836_arm_irqchip_spin_gpu_irq(); |
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} |
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#endif |
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static struct irq_chip armctrl_chip = { |
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.name = "ARMCTRL-level", |
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.irq_mask = armctrl_mask_irq, |
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.irq_unmask = armctrl_unmask_irq, |
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#ifdef CONFIG_ARM64 |
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.irq_ack = armctrl_ack_irq |
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#endif |
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}; |
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static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr, |
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const u32 *intspec, unsigned int intsize, |
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unsigned long *out_hwirq, unsigned int *out_type) |
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{ |
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if (WARN_ON(intsize != 2)) |
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return -EINVAL; |
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if (WARN_ON(intspec[0] >= NR_BANKS)) |
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return -EINVAL; |
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if (WARN_ON(intspec[1] >= IRQS_PER_BANK)) |
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return -EINVAL; |
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if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0)) |
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return -EINVAL; |
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*out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]); |
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*out_type = IRQ_TYPE_NONE; |
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return 0; |
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} |
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static const struct irq_domain_ops armctrl_ops = { |
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.xlate = armctrl_xlate |
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}; |
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static int __init armctrl_of_init(struct device_node *node, |
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struct device_node *parent, |
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bool is_2836) |
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{ |
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void __iomem *base; |
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int irq = 0, last_irq, b, i; |
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u32 reg; |
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base = of_iomap(node, 0); |
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if (!base) |
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panic("%pOF: unable to map IC registers\n", node); |
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intc.base = base; |
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intc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2, |
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&armctrl_ops, NULL); |
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if (!intc.domain) |
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panic("%pOF: unable to create IRQ domain\n", node); |
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for (b = 0; b < NR_BANKS; b++) { |
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intc.pending[b] = base + reg_pending[b]; |
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intc.enable[b] = base + reg_enable[b]; |
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intc.disable[b] = base + reg_disable[b]; |
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for (i = 0; i < bank_irqs[b]; i++) { |
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irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i)); |
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BUG_ON(irq <= 0); |
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irq_set_chip_and_handler(irq, &armctrl_chip, |
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handle_level_irq); |
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irq_set_probe(irq); |
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} |
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reg = readl_relaxed(intc.enable[b]); |
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if (reg) { |
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writel_relaxed(reg, intc.disable[b]); |
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pr_err(FW_BUG "Bootloader left irq enabled: " |
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"bank %d irq %*pbl\n", b, IRQS_PER_BANK, ®); |
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} |
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} |
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reg = readl_relaxed(base + REG_FIQ_CONTROL); |
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if (reg & FIQ_CONTROL_ENABLE) { |
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writel_relaxed(0, base + REG_FIQ_CONTROL); |
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pr_err(FW_BUG "Bootloader left fiq enabled\n"); |
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} |
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last_irq = irq; |
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if (is_2836) { |
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int parent_irq = irq_of_parse_and_map(node, 0); |
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if (!parent_irq) { |
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panic("%pOF: unable to get parent interrupt.\n", |
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node); |
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} |
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irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq); |
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} else { |
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set_handle_irq(bcm2835_handle_irq); |
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} |
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if (is_2836) { |
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extern void __iomem * __attribute__((weak)) arm_local_intc; |
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intc.local_base = arm_local_intc; |
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if (!intc.local_base) |
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pr_err("Failed to get local intc base. FIQ is disabled for cpus > 1\n"); |
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} |
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/* Make a duplicate irq range which is used to enable FIQ */ |
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for (b = 0; b < NR_BANKS; b++) { |
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for (i = 0; i < bank_irqs[b]; i++) { |
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irq = irq_create_mapping(intc.domain, |
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MAKE_HWIRQ(b, i) + NUMBER_IRQS); |
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BUG_ON(irq <= 0); |
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irq_set_chip(irq, &armctrl_chip); |
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irq_set_probe(irq); |
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} |
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} |
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#ifndef CONFIG_ARM64 |
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init_FIQ(irq - last_irq); |
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#endif |
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return 0; |
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} |
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static int __init bcm2835_armctrl_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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return armctrl_of_init(node, parent, false); |
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} |
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static int __init bcm2836_armctrl_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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return armctrl_of_init(node, parent, true); |
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} |
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/* |
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* Handle each interrupt across the entire interrupt controller. This reads the |
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* status register before handling each interrupt, which is necessary given that |
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* handle_IRQ may briefly re-enable interrupts for soft IRQ handling. |
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*/ |
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static u32 armctrl_translate_bank(int bank) |
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{ |
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u32 stat = readl_relaxed(intc.pending[bank]); |
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return MAKE_HWIRQ(bank, ffs(stat) - 1); |
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} |
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static u32 armctrl_translate_shortcut(int bank, u32 stat) |
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{ |
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return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]); |
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} |
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static u32 get_next_armctrl_hwirq(void) |
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{ |
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u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK; |
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if (stat == 0) |
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return ~0; |
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else if (stat & BANK0_HWIRQ_MASK) |
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return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1); |
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else if (stat & SHORTCUT1_MASK) |
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return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK); |
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else if (stat & SHORTCUT2_MASK) |
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return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK); |
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else if (stat & BANK1_HWIRQ) |
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return armctrl_translate_bank(1); |
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else if (stat & BANK2_HWIRQ) |
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return armctrl_translate_bank(2); |
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else |
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BUG(); |
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} |
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static void __exception_irq_entry bcm2835_handle_irq( |
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struct pt_regs *regs) |
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{ |
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u32 hwirq; |
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while ((hwirq = get_next_armctrl_hwirq()) != ~0) |
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handle_domain_irq(intc.domain, hwirq, regs); |
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} |
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static void bcm2836_chained_handle_irq(struct irq_desc *desc) |
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{ |
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u32 hwirq; |
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while ((hwirq = get_next_armctrl_hwirq()) != ~0) |
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generic_handle_irq(irq_linear_revmap(intc.domain, hwirq)); |
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} |
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IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic", |
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bcm2835_armctrl_of_init); |
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IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic", |
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bcm2836_armctrl_of_init);
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