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850 lines
20 KiB
850 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
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* |
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* Author: Stepan Moskovchenko <[email protected]> |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/platform_device.h> |
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#include <linux/errno.h> |
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#include <linux/io.h> |
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#include <linux/io-pgtable.h> |
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#include <linux/interrupt.h> |
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#include <linux/list.h> |
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#include <linux/spinlock.h> |
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#include <linux/slab.h> |
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#include <linux/iommu.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/of_iommu.h> |
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#include <asm/cacheflush.h> |
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#include <linux/sizes.h> |
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#include "msm_iommu_hw-8xxx.h" |
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#include "msm_iommu.h" |
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#define MRC(reg, processor, op1, crn, crm, op2) \ |
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__asm__ __volatile__ ( \ |
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" mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \ |
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: "=r" (reg)) |
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/* bitmap of the page sizes currently supported */ |
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#define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) |
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static DEFINE_SPINLOCK(msm_iommu_lock); |
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static LIST_HEAD(qcom_iommu_devices); |
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static struct iommu_ops msm_iommu_ops; |
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struct msm_priv { |
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struct list_head list_attached; |
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struct iommu_domain domain; |
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struct io_pgtable_cfg cfg; |
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struct io_pgtable_ops *iop; |
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struct device *dev; |
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spinlock_t pgtlock; /* pagetable lock */ |
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}; |
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static struct msm_priv *to_msm_priv(struct iommu_domain *dom) |
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{ |
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return container_of(dom, struct msm_priv, domain); |
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} |
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static int __enable_clocks(struct msm_iommu_dev *iommu) |
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{ |
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int ret; |
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ret = clk_enable(iommu->pclk); |
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if (ret) |
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goto fail; |
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if (iommu->clk) { |
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ret = clk_enable(iommu->clk); |
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if (ret) |
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clk_disable(iommu->pclk); |
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} |
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fail: |
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return ret; |
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} |
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static void __disable_clocks(struct msm_iommu_dev *iommu) |
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{ |
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if (iommu->clk) |
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clk_disable(iommu->clk); |
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clk_disable(iommu->pclk); |
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} |
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static void msm_iommu_reset(void __iomem *base, int ncb) |
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{ |
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int ctx; |
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SET_RPUE(base, 0); |
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SET_RPUEIE(base, 0); |
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SET_ESRRESTORE(base, 0); |
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SET_TBE(base, 0); |
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SET_CR(base, 0); |
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SET_SPDMBE(base, 0); |
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SET_TESTBUSCR(base, 0); |
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SET_TLBRSW(base, 0); |
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SET_GLOBAL_TLBIALL(base, 0); |
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SET_RPU_ACR(base, 0); |
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SET_TLBLKCRWE(base, 1); |
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for (ctx = 0; ctx < ncb; ctx++) { |
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SET_BPRCOSH(base, ctx, 0); |
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SET_BPRCISH(base, ctx, 0); |
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SET_BPRCNSH(base, ctx, 0); |
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SET_BPSHCFG(base, ctx, 0); |
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SET_BPMTCFG(base, ctx, 0); |
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SET_ACTLR(base, ctx, 0); |
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SET_SCTLR(base, ctx, 0); |
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SET_FSRRESTORE(base, ctx, 0); |
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SET_TTBR0(base, ctx, 0); |
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SET_TTBR1(base, ctx, 0); |
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SET_TTBCR(base, ctx, 0); |
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SET_BFBCR(base, ctx, 0); |
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SET_PAR(base, ctx, 0); |
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SET_FAR(base, ctx, 0); |
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SET_CTX_TLBIALL(base, ctx, 0); |
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SET_TLBFLPTER(base, ctx, 0); |
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SET_TLBSLPTER(base, ctx, 0); |
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SET_TLBLKCR(base, ctx, 0); |
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SET_CONTEXTIDR(base, ctx, 0); |
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} |
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} |
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static void __flush_iotlb(void *cookie) |
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{ |
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struct msm_priv *priv = cookie; |
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struct msm_iommu_dev *iommu = NULL; |
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struct msm_iommu_ctx_dev *master; |
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int ret = 0; |
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list_for_each_entry(iommu, &priv->list_attached, dom_node) { |
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ret = __enable_clocks(iommu); |
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if (ret) |
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goto fail; |
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list_for_each_entry(master, &iommu->ctx_list, list) |
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SET_CTX_TLBIALL(iommu->base, master->num, 0); |
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__disable_clocks(iommu); |
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} |
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fail: |
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return; |
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} |
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static void __flush_iotlb_range(unsigned long iova, size_t size, |
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size_t granule, bool leaf, void *cookie) |
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{ |
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struct msm_priv *priv = cookie; |
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struct msm_iommu_dev *iommu = NULL; |
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struct msm_iommu_ctx_dev *master; |
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int ret = 0; |
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int temp_size; |
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list_for_each_entry(iommu, &priv->list_attached, dom_node) { |
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ret = __enable_clocks(iommu); |
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if (ret) |
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goto fail; |
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list_for_each_entry(master, &iommu->ctx_list, list) { |
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temp_size = size; |
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do { |
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iova &= TLBIVA_VA; |
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iova |= GET_CONTEXTIDR_ASID(iommu->base, |
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master->num); |
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SET_TLBIVA(iommu->base, master->num, iova); |
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iova += granule; |
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} while (temp_size -= granule); |
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} |
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__disable_clocks(iommu); |
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} |
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fail: |
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return; |
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} |
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static void __flush_iotlb_walk(unsigned long iova, size_t size, |
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size_t granule, void *cookie) |
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{ |
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__flush_iotlb_range(iova, size, granule, false, cookie); |
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} |
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static void __flush_iotlb_page(struct iommu_iotlb_gather *gather, |
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unsigned long iova, size_t granule, void *cookie) |
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{ |
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__flush_iotlb_range(iova, granule, granule, true, cookie); |
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} |
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static const struct iommu_flush_ops msm_iommu_flush_ops = { |
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.tlb_flush_all = __flush_iotlb, |
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.tlb_flush_walk = __flush_iotlb_walk, |
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.tlb_add_page = __flush_iotlb_page, |
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}; |
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static int msm_iommu_alloc_ctx(unsigned long *map, int start, int end) |
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{ |
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int idx; |
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do { |
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idx = find_next_zero_bit(map, end, start); |
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if (idx == end) |
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return -ENOSPC; |
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} while (test_and_set_bit(idx, map)); |
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return idx; |
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} |
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static void msm_iommu_free_ctx(unsigned long *map, int idx) |
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{ |
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clear_bit(idx, map); |
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} |
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static void config_mids(struct msm_iommu_dev *iommu, |
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struct msm_iommu_ctx_dev *master) |
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{ |
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int mid, ctx, i; |
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for (i = 0; i < master->num_mids; i++) { |
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mid = master->mids[i]; |
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ctx = master->num; |
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SET_M2VCBR_N(iommu->base, mid, 0); |
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SET_CBACR_N(iommu->base, ctx, 0); |
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/* Set VMID = 0 */ |
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SET_VMID(iommu->base, mid, 0); |
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/* Set the context number for that MID to this context */ |
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SET_CBNDX(iommu->base, mid, ctx); |
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/* Set MID associated with this context bank to 0*/ |
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SET_CBVMID(iommu->base, ctx, 0); |
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/* Set the ASID for TLB tagging for this context */ |
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SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx); |
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/* Set security bit override to be Non-secure */ |
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SET_NSCFG(iommu->base, mid, 3); |
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} |
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} |
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static void __reset_context(void __iomem *base, int ctx) |
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{ |
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SET_BPRCOSH(base, ctx, 0); |
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SET_BPRCISH(base, ctx, 0); |
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SET_BPRCNSH(base, ctx, 0); |
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SET_BPSHCFG(base, ctx, 0); |
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SET_BPMTCFG(base, ctx, 0); |
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SET_ACTLR(base, ctx, 0); |
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SET_SCTLR(base, ctx, 0); |
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SET_FSRRESTORE(base, ctx, 0); |
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SET_TTBR0(base, ctx, 0); |
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SET_TTBR1(base, ctx, 0); |
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SET_TTBCR(base, ctx, 0); |
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SET_BFBCR(base, ctx, 0); |
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SET_PAR(base, ctx, 0); |
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SET_FAR(base, ctx, 0); |
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SET_CTX_TLBIALL(base, ctx, 0); |
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SET_TLBFLPTER(base, ctx, 0); |
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SET_TLBSLPTER(base, ctx, 0); |
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SET_TLBLKCR(base, ctx, 0); |
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} |
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static void __program_context(void __iomem *base, int ctx, |
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struct msm_priv *priv) |
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{ |
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__reset_context(base, ctx); |
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/* Turn on TEX Remap */ |
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SET_TRE(base, ctx, 1); |
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SET_AFE(base, ctx, 1); |
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/* Set up HTW mode */ |
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/* TLB miss configuration: perform HTW on miss */ |
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SET_TLBMCFG(base, ctx, 0x3); |
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/* V2P configuration: HTW for access */ |
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SET_V2PCFG(base, ctx, 0x3); |
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SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr); |
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SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr); |
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SET_TTBR1(base, ctx, 0); |
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/* Set prrr and nmrr */ |
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SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr); |
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SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr); |
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/* Invalidate the TLB for this context */ |
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SET_CTX_TLBIALL(base, ctx, 0); |
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/* Set interrupt number to "secure" interrupt */ |
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SET_IRPTNDX(base, ctx, 0); |
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/* Enable context fault interrupt */ |
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SET_CFEIE(base, ctx, 1); |
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/* Stall access on a context fault and let the handler deal with it */ |
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SET_CFCFG(base, ctx, 1); |
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/* Redirect all cacheable requests to L2 slave port. */ |
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SET_RCISH(base, ctx, 1); |
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SET_RCOSH(base, ctx, 1); |
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SET_RCNSH(base, ctx, 1); |
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/* Turn on BFB prefetch */ |
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SET_BFBDFE(base, ctx, 1); |
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/* Enable the MMU */ |
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SET_M(base, ctx, 1); |
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} |
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static struct iommu_domain *msm_iommu_domain_alloc(unsigned type) |
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{ |
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struct msm_priv *priv; |
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if (type != IOMMU_DOMAIN_UNMANAGED) |
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return NULL; |
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priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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goto fail_nomem; |
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INIT_LIST_HEAD(&priv->list_attached); |
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priv->domain.geometry.aperture_start = 0; |
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priv->domain.geometry.aperture_end = (1ULL << 32) - 1; |
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priv->domain.geometry.force_aperture = true; |
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return &priv->domain; |
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fail_nomem: |
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kfree(priv); |
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return NULL; |
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} |
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static void msm_iommu_domain_free(struct iommu_domain *domain) |
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{ |
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struct msm_priv *priv; |
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unsigned long flags; |
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spin_lock_irqsave(&msm_iommu_lock, flags); |
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priv = to_msm_priv(domain); |
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kfree(priv); |
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spin_unlock_irqrestore(&msm_iommu_lock, flags); |
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} |
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static int msm_iommu_domain_config(struct msm_priv *priv) |
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{ |
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spin_lock_init(&priv->pgtlock); |
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priv->cfg = (struct io_pgtable_cfg) { |
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.pgsize_bitmap = msm_iommu_ops.pgsize_bitmap, |
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.ias = 32, |
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.oas = 32, |
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.tlb = &msm_iommu_flush_ops, |
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.iommu_dev = priv->dev, |
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}; |
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priv->iop = alloc_io_pgtable_ops(ARM_V7S, &priv->cfg, priv); |
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if (!priv->iop) { |
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dev_err(priv->dev, "Failed to allocate pgtable\n"); |
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return -EINVAL; |
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} |
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msm_iommu_ops.pgsize_bitmap = priv->cfg.pgsize_bitmap; |
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return 0; |
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} |
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/* Must be called under msm_iommu_lock */ |
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static struct msm_iommu_dev *find_iommu_for_dev(struct device *dev) |
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{ |
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struct msm_iommu_dev *iommu, *ret = NULL; |
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struct msm_iommu_ctx_dev *master; |
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list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) { |
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master = list_first_entry(&iommu->ctx_list, |
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struct msm_iommu_ctx_dev, |
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list); |
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if (master->of_node == dev->of_node) { |
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ret = iommu; |
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break; |
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} |
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} |
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return ret; |
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} |
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static struct iommu_device *msm_iommu_probe_device(struct device *dev) |
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{ |
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struct msm_iommu_dev *iommu; |
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unsigned long flags; |
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spin_lock_irqsave(&msm_iommu_lock, flags); |
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iommu = find_iommu_for_dev(dev); |
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spin_unlock_irqrestore(&msm_iommu_lock, flags); |
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if (!iommu) |
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return ERR_PTR(-ENODEV); |
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return &iommu->iommu; |
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} |
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static void msm_iommu_release_device(struct device *dev) |
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{ |
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} |
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static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) |
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{ |
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int ret = 0; |
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unsigned long flags; |
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struct msm_iommu_dev *iommu; |
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struct msm_priv *priv = to_msm_priv(domain); |
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struct msm_iommu_ctx_dev *master; |
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priv->dev = dev; |
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msm_iommu_domain_config(priv); |
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spin_lock_irqsave(&msm_iommu_lock, flags); |
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list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) { |
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master = list_first_entry(&iommu->ctx_list, |
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struct msm_iommu_ctx_dev, |
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list); |
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if (master->of_node == dev->of_node) { |
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ret = __enable_clocks(iommu); |
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if (ret) |
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goto fail; |
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list_for_each_entry(master, &iommu->ctx_list, list) { |
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if (master->num) { |
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dev_err(dev, "domain already attached"); |
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ret = -EEXIST; |
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goto fail; |
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} |
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master->num = |
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msm_iommu_alloc_ctx(iommu->context_map, |
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0, iommu->ncb); |
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if (IS_ERR_VALUE(master->num)) { |
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ret = -ENODEV; |
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goto fail; |
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} |
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config_mids(iommu, master); |
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__program_context(iommu->base, master->num, |
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priv); |
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} |
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__disable_clocks(iommu); |
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list_add(&iommu->dom_node, &priv->list_attached); |
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} |
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} |
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fail: |
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spin_unlock_irqrestore(&msm_iommu_lock, flags); |
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return ret; |
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} |
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static void msm_iommu_detach_dev(struct iommu_domain *domain, |
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struct device *dev) |
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{ |
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struct msm_priv *priv = to_msm_priv(domain); |
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unsigned long flags; |
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struct msm_iommu_dev *iommu; |
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struct msm_iommu_ctx_dev *master; |
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int ret; |
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free_io_pgtable_ops(priv->iop); |
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spin_lock_irqsave(&msm_iommu_lock, flags); |
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list_for_each_entry(iommu, &priv->list_attached, dom_node) { |
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ret = __enable_clocks(iommu); |
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if (ret) |
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goto fail; |
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list_for_each_entry(master, &iommu->ctx_list, list) { |
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msm_iommu_free_ctx(iommu->context_map, master->num); |
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__reset_context(iommu->base, master->num); |
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} |
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__disable_clocks(iommu); |
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} |
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fail: |
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spin_unlock_irqrestore(&msm_iommu_lock, flags); |
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} |
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static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova, |
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phys_addr_t pa, size_t len, int prot, gfp_t gfp) |
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{ |
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struct msm_priv *priv = to_msm_priv(domain); |
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unsigned long flags; |
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int ret; |
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spin_lock_irqsave(&priv->pgtlock, flags); |
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ret = priv->iop->map(priv->iop, iova, pa, len, prot, GFP_ATOMIC); |
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spin_unlock_irqrestore(&priv->pgtlock, flags); |
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return ret; |
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} |
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static void msm_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, |
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size_t size) |
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{ |
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struct msm_priv *priv = to_msm_priv(domain); |
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__flush_iotlb_range(iova, size, SZ_4K, false, priv); |
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} |
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static size_t msm_iommu_unmap(struct iommu_domain *domain, unsigned long iova, |
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size_t len, struct iommu_iotlb_gather *gather) |
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{ |
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struct msm_priv *priv = to_msm_priv(domain); |
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unsigned long flags; |
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spin_lock_irqsave(&priv->pgtlock, flags); |
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len = priv->iop->unmap(priv->iop, iova, len, gather); |
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spin_unlock_irqrestore(&priv->pgtlock, flags); |
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return len; |
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} |
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static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, |
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dma_addr_t va) |
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{ |
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struct msm_priv *priv; |
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struct msm_iommu_dev *iommu; |
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struct msm_iommu_ctx_dev *master; |
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unsigned int par; |
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unsigned long flags; |
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phys_addr_t ret = 0; |
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spin_lock_irqsave(&msm_iommu_lock, flags); |
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priv = to_msm_priv(domain); |
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iommu = list_first_entry(&priv->list_attached, |
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struct msm_iommu_dev, dom_node); |
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if (list_empty(&iommu->ctx_list)) |
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goto fail; |
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master = list_first_entry(&iommu->ctx_list, |
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struct msm_iommu_ctx_dev, list); |
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if (!master) |
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goto fail; |
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ret = __enable_clocks(iommu); |
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if (ret) |
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goto fail; |
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/* Invalidate context TLB */ |
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SET_CTX_TLBIALL(iommu->base, master->num, 0); |
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SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA); |
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par = GET_PAR(iommu->base, master->num); |
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/* We are dealing with a supersection */ |
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if (GET_NOFAULT_SS(iommu->base, master->num)) |
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ret = (par & 0xFF000000) | (va & 0x00FFFFFF); |
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else /* Upper 20 bits from PAR, lower 12 from VA */ |
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ret = (par & 0xFFFFF000) | (va & 0x00000FFF); |
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if (GET_FAULT(iommu->base, master->num)) |
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ret = 0; |
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__disable_clocks(iommu); |
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fail: |
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spin_unlock_irqrestore(&msm_iommu_lock, flags); |
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return ret; |
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} |
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static bool msm_iommu_capable(enum iommu_cap cap) |
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{ |
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return false; |
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} |
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static void print_ctx_regs(void __iomem *base, int ctx) |
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{ |
|
unsigned int fsr = GET_FSR(base, ctx); |
|
pr_err("FAR = %08x PAR = %08x\n", |
|
GET_FAR(base, ctx), GET_PAR(base, ctx)); |
|
pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr, |
|
(fsr & 0x02) ? "TF " : "", |
|
(fsr & 0x04) ? "AFF " : "", |
|
(fsr & 0x08) ? "APF " : "", |
|
(fsr & 0x10) ? "TLBMF " : "", |
|
(fsr & 0x20) ? "HTWDEEF " : "", |
|
(fsr & 0x40) ? "HTWSEEF " : "", |
|
(fsr & 0x80) ? "MHF " : "", |
|
(fsr & 0x10000) ? "SL " : "", |
|
(fsr & 0x40000000) ? "SS " : "", |
|
(fsr & 0x80000000) ? "MULTI " : ""); |
|
|
|
pr_err("FSYNR0 = %08x FSYNR1 = %08x\n", |
|
GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx)); |
|
pr_err("TTBR0 = %08x TTBR1 = %08x\n", |
|
GET_TTBR0(base, ctx), GET_TTBR1(base, ctx)); |
|
pr_err("SCTLR = %08x ACTLR = %08x\n", |
|
GET_SCTLR(base, ctx), GET_ACTLR(base, ctx)); |
|
} |
|
|
|
static void insert_iommu_master(struct device *dev, |
|
struct msm_iommu_dev **iommu, |
|
struct of_phandle_args *spec) |
|
{ |
|
struct msm_iommu_ctx_dev *master = dev_iommu_priv_get(dev); |
|
int sid; |
|
|
|
if (list_empty(&(*iommu)->ctx_list)) { |
|
master = kzalloc(sizeof(*master), GFP_ATOMIC); |
|
master->of_node = dev->of_node; |
|
list_add(&master->list, &(*iommu)->ctx_list); |
|
dev_iommu_priv_set(dev, master); |
|
} |
|
|
|
for (sid = 0; sid < master->num_mids; sid++) |
|
if (master->mids[sid] == spec->args[0]) { |
|
dev_warn(dev, "Stream ID 0x%hx repeated; ignoring\n", |
|
sid); |
|
return; |
|
} |
|
|
|
master->mids[master->num_mids++] = spec->args[0]; |
|
} |
|
|
|
static int qcom_iommu_of_xlate(struct device *dev, |
|
struct of_phandle_args *spec) |
|
{ |
|
struct msm_iommu_dev *iommu; |
|
unsigned long flags; |
|
int ret = 0; |
|
|
|
spin_lock_irqsave(&msm_iommu_lock, flags); |
|
list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) |
|
if (iommu->dev->of_node == spec->np) |
|
break; |
|
|
|
if (!iommu || iommu->dev->of_node != spec->np) { |
|
ret = -ENODEV; |
|
goto fail; |
|
} |
|
|
|
insert_iommu_master(dev, &iommu, spec); |
|
fail: |
|
spin_unlock_irqrestore(&msm_iommu_lock, flags); |
|
|
|
return ret; |
|
} |
|
|
|
irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) |
|
{ |
|
struct msm_iommu_dev *iommu = dev_id; |
|
unsigned int fsr; |
|
int i, ret; |
|
|
|
spin_lock(&msm_iommu_lock); |
|
|
|
if (!iommu) { |
|
pr_err("Invalid device ID in context interrupt handler\n"); |
|
goto fail; |
|
} |
|
|
|
pr_err("Unexpected IOMMU page fault!\n"); |
|
pr_err("base = %08x\n", (unsigned int)iommu->base); |
|
|
|
ret = __enable_clocks(iommu); |
|
if (ret) |
|
goto fail; |
|
|
|
for (i = 0; i < iommu->ncb; i++) { |
|
fsr = GET_FSR(iommu->base, i); |
|
if (fsr) { |
|
pr_err("Fault occurred in context %d.\n", i); |
|
pr_err("Interesting registers:\n"); |
|
print_ctx_regs(iommu->base, i); |
|
SET_FSR(iommu->base, i, 0x4000000F); |
|
} |
|
} |
|
__disable_clocks(iommu); |
|
fail: |
|
spin_unlock(&msm_iommu_lock); |
|
return 0; |
|
} |
|
|
|
static struct iommu_ops msm_iommu_ops = { |
|
.capable = msm_iommu_capable, |
|
.domain_alloc = msm_iommu_domain_alloc, |
|
.domain_free = msm_iommu_domain_free, |
|
.attach_dev = msm_iommu_attach_dev, |
|
.detach_dev = msm_iommu_detach_dev, |
|
.map = msm_iommu_map, |
|
.unmap = msm_iommu_unmap, |
|
/* |
|
* Nothing is needed here, the barrier to guarantee |
|
* completion of the tlb sync operation is implicitly |
|
* taken care when the iommu client does a writel before |
|
* kick starting the other master. |
|
*/ |
|
.iotlb_sync = NULL, |
|
.iotlb_sync_map = msm_iommu_sync_map, |
|
.iova_to_phys = msm_iommu_iova_to_phys, |
|
.probe_device = msm_iommu_probe_device, |
|
.release_device = msm_iommu_release_device, |
|
.device_group = generic_device_group, |
|
.pgsize_bitmap = MSM_IOMMU_PGSIZES, |
|
.of_xlate = qcom_iommu_of_xlate, |
|
}; |
|
|
|
static int msm_iommu_probe(struct platform_device *pdev) |
|
{ |
|
struct resource *r; |
|
resource_size_t ioaddr; |
|
struct msm_iommu_dev *iommu; |
|
int ret, par, val; |
|
|
|
iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL); |
|
if (!iommu) |
|
return -ENODEV; |
|
|
|
iommu->dev = &pdev->dev; |
|
INIT_LIST_HEAD(&iommu->ctx_list); |
|
|
|
iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk"); |
|
if (IS_ERR(iommu->pclk)) { |
|
dev_err(iommu->dev, "could not get smmu_pclk\n"); |
|
return PTR_ERR(iommu->pclk); |
|
} |
|
|
|
ret = clk_prepare(iommu->pclk); |
|
if (ret) { |
|
dev_err(iommu->dev, "could not prepare smmu_pclk\n"); |
|
return ret; |
|
} |
|
|
|
iommu->clk = devm_clk_get(iommu->dev, "iommu_clk"); |
|
if (IS_ERR(iommu->clk)) { |
|
dev_err(iommu->dev, "could not get iommu_clk\n"); |
|
clk_unprepare(iommu->pclk); |
|
return PTR_ERR(iommu->clk); |
|
} |
|
|
|
ret = clk_prepare(iommu->clk); |
|
if (ret) { |
|
dev_err(iommu->dev, "could not prepare iommu_clk\n"); |
|
clk_unprepare(iommu->pclk); |
|
return ret; |
|
} |
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
iommu->base = devm_ioremap_resource(iommu->dev, r); |
|
if (IS_ERR(iommu->base)) { |
|
dev_err(iommu->dev, "could not get iommu base\n"); |
|
ret = PTR_ERR(iommu->base); |
|
goto fail; |
|
} |
|
ioaddr = r->start; |
|
|
|
iommu->irq = platform_get_irq(pdev, 0); |
|
if (iommu->irq < 0) { |
|
ret = -ENODEV; |
|
goto fail; |
|
} |
|
|
|
ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val); |
|
if (ret) { |
|
dev_err(iommu->dev, "could not get ncb\n"); |
|
goto fail; |
|
} |
|
iommu->ncb = val; |
|
|
|
msm_iommu_reset(iommu->base, iommu->ncb); |
|
SET_M(iommu->base, 0, 1); |
|
SET_PAR(iommu->base, 0, 0); |
|
SET_V2PCFG(iommu->base, 0, 1); |
|
SET_V2PPR(iommu->base, 0, 0); |
|
par = GET_PAR(iommu->base, 0); |
|
SET_V2PCFG(iommu->base, 0, 0); |
|
SET_M(iommu->base, 0, 0); |
|
|
|
if (!par) { |
|
pr_err("Invalid PAR value detected\n"); |
|
ret = -ENODEV; |
|
goto fail; |
|
} |
|
|
|
ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL, |
|
msm_iommu_fault_handler, |
|
IRQF_ONESHOT | IRQF_SHARED, |
|
"msm_iommu_secure_irpt_handler", |
|
iommu); |
|
if (ret) { |
|
pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret); |
|
goto fail; |
|
} |
|
|
|
list_add(&iommu->dev_node, &qcom_iommu_devices); |
|
|
|
ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL, |
|
"msm-smmu.%pa", &ioaddr); |
|
if (ret) { |
|
pr_err("Could not add msm-smmu at %pa to sysfs\n", &ioaddr); |
|
goto fail; |
|
} |
|
|
|
iommu_device_set_ops(&iommu->iommu, &msm_iommu_ops); |
|
iommu_device_set_fwnode(&iommu->iommu, &pdev->dev.of_node->fwnode); |
|
|
|
ret = iommu_device_register(&iommu->iommu); |
|
if (ret) { |
|
pr_err("Could not register msm-smmu at %pa\n", &ioaddr); |
|
goto fail; |
|
} |
|
|
|
bus_set_iommu(&platform_bus_type, &msm_iommu_ops); |
|
|
|
pr_info("device mapped at %p, irq %d with %d ctx banks\n", |
|
iommu->base, iommu->irq, iommu->ncb); |
|
|
|
return ret; |
|
fail: |
|
clk_unprepare(iommu->clk); |
|
clk_unprepare(iommu->pclk); |
|
return ret; |
|
} |
|
|
|
static const struct of_device_id msm_iommu_dt_match[] = { |
|
{ .compatible = "qcom,apq8064-iommu" }, |
|
{} |
|
}; |
|
|
|
static int msm_iommu_remove(struct platform_device *pdev) |
|
{ |
|
struct msm_iommu_dev *iommu = platform_get_drvdata(pdev); |
|
|
|
clk_unprepare(iommu->clk); |
|
clk_unprepare(iommu->pclk); |
|
return 0; |
|
} |
|
|
|
static struct platform_driver msm_iommu_driver = { |
|
.driver = { |
|
.name = "msm_iommu", |
|
.of_match_table = msm_iommu_dt_match, |
|
}, |
|
.probe = msm_iommu_probe, |
|
.remove = msm_iommu_remove, |
|
}; |
|
|
|
static int __init msm_iommu_driver_init(void) |
|
{ |
|
int ret; |
|
|
|
ret = platform_driver_register(&msm_iommu_driver); |
|
if (ret != 0) |
|
pr_err("Failed to register IOMMU driver\n"); |
|
|
|
return ret; |
|
} |
|
subsys_initcall(msm_iommu_driver_init); |
|
|
|
|