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338 lines
8.6 KiB
338 lines
8.6 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Driver for Allwinner A10 PS2 host controller |
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* |
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* Author: Vishnu Patekar <[email protected]> |
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* Aaron.maoye <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/serio.h> |
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#include <linux/interrupt.h> |
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#include <linux/errno.h> |
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#include <linux/slab.h> |
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#include <linux/io.h> |
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#include <linux/clk.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/platform_device.h> |
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#define DRIVER_NAME "sun4i-ps2" |
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/* register offset definitions */ |
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#define PS2_REG_GCTL 0x00 /* PS2 Module Global Control Reg */ |
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#define PS2_REG_DATA 0x04 /* PS2 Module Data Reg */ |
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#define PS2_REG_LCTL 0x08 /* PS2 Module Line Control Reg */ |
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#define PS2_REG_LSTS 0x0C /* PS2 Module Line Status Reg */ |
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#define PS2_REG_FCTL 0x10 /* PS2 Module FIFO Control Reg */ |
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#define PS2_REG_FSTS 0x14 /* PS2 Module FIFO Status Reg */ |
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#define PS2_REG_CLKDR 0x18 /* PS2 Module Clock Divider Reg*/ |
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/* PS2 GLOBAL CONTROL REGISTER PS2_GCTL */ |
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#define PS2_GCTL_INTFLAG BIT(4) |
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#define PS2_GCTL_INTEN BIT(3) |
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#define PS2_GCTL_RESET BIT(2) |
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#define PS2_GCTL_MASTER BIT(1) |
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#define PS2_GCTL_BUSEN BIT(0) |
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/* PS2 LINE CONTROL REGISTER */ |
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#define PS2_LCTL_NOACK BIT(18) |
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#define PS2_LCTL_TXDTOEN BIT(8) |
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#define PS2_LCTL_STOPERREN BIT(3) |
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#define PS2_LCTL_ACKERREN BIT(2) |
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#define PS2_LCTL_PARERREN BIT(1) |
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#define PS2_LCTL_RXDTOEN BIT(0) |
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/* PS2 LINE STATUS REGISTER */ |
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#define PS2_LSTS_TXTDO BIT(8) |
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#define PS2_LSTS_STOPERR BIT(3) |
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#define PS2_LSTS_ACKERR BIT(2) |
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#define PS2_LSTS_PARERR BIT(1) |
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#define PS2_LSTS_RXTDO BIT(0) |
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#define PS2_LINE_ERROR_BIT \ |
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(PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR | \ |
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PS2_LSTS_PARERR | PS2_LSTS_RXTDO) |
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/* PS2 FIFO CONTROL REGISTER */ |
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#define PS2_FCTL_TXRST BIT(17) |
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#define PS2_FCTL_RXRST BIT(16) |
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#define PS2_FCTL_TXUFIEN BIT(10) |
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#define PS2_FCTL_TXOFIEN BIT(9) |
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#define PS2_FCTL_TXRDYIEN BIT(8) |
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#define PS2_FCTL_RXUFIEN BIT(2) |
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#define PS2_FCTL_RXOFIEN BIT(1) |
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#define PS2_FCTL_RXRDYIEN BIT(0) |
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/* PS2 FIFO STATUS REGISTER */ |
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#define PS2_FSTS_TXUF BIT(10) |
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#define PS2_FSTS_TXOF BIT(9) |
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#define PS2_FSTS_TXRDY BIT(8) |
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#define PS2_FSTS_RXUF BIT(2) |
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#define PS2_FSTS_RXOF BIT(1) |
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#define PS2_FSTS_RXRDY BIT(0) |
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#define PS2_FIFO_ERROR_BIT \ |
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(PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_RXUF | PS2_FSTS_RXOF) |
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#define PS2_SAMPLE_CLK 1000000 |
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#define PS2_SCLK 125000 |
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struct sun4i_ps2data { |
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struct serio *serio; |
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struct device *dev; |
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/* IO mapping base */ |
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void __iomem *reg_base; |
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/* clock management */ |
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struct clk *clk; |
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/* irq */ |
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spinlock_t lock; |
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int irq; |
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}; |
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static irqreturn_t sun4i_ps2_interrupt(int irq, void *dev_id) |
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{ |
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struct sun4i_ps2data *drvdata = dev_id; |
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u32 intr_status; |
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u32 fifo_status; |
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unsigned char byte; |
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unsigned int rxflags = 0; |
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u32 rval; |
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spin_lock(&drvdata->lock); |
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/* Get the PS/2 interrupts and clear them */ |
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intr_status = readl(drvdata->reg_base + PS2_REG_LSTS); |
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fifo_status = readl(drvdata->reg_base + PS2_REG_FSTS); |
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/* Check line status register */ |
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if (intr_status & PS2_LINE_ERROR_BIT) { |
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rxflags = (intr_status & PS2_LINE_ERROR_BIT) ? SERIO_FRAME : 0; |
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rxflags |= (intr_status & PS2_LSTS_PARERR) ? SERIO_PARITY : 0; |
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rxflags |= (intr_status & PS2_LSTS_PARERR) ? SERIO_TIMEOUT : 0; |
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rval = PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR | |
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PS2_LSTS_PARERR | PS2_LSTS_RXTDO; |
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writel(rval, drvdata->reg_base + PS2_REG_LSTS); |
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} |
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/* Check FIFO status register */ |
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if (fifo_status & PS2_FIFO_ERROR_BIT) { |
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rval = PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_TXRDY | |
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PS2_FSTS_RXUF | PS2_FSTS_RXOF | PS2_FSTS_RXRDY; |
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writel(rval, drvdata->reg_base + PS2_REG_FSTS); |
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} |
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rval = (fifo_status >> 16) & 0x3; |
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while (rval--) { |
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byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff; |
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serio_interrupt(drvdata->serio, byte, rxflags); |
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} |
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writel(intr_status, drvdata->reg_base + PS2_REG_LSTS); |
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writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS); |
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spin_unlock(&drvdata->lock); |
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return IRQ_HANDLED; |
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} |
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static int sun4i_ps2_open(struct serio *serio) |
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{ |
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struct sun4i_ps2data *drvdata = serio->port_data; |
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u32 src_clk = 0; |
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u32 clk_scdf; |
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u32 clk_pcdf; |
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u32 rval; |
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unsigned long flags; |
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/* Set line control and enable interrupt */ |
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rval = PS2_LCTL_STOPERREN | PS2_LCTL_ACKERREN |
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| PS2_LCTL_PARERREN | PS2_LCTL_RXDTOEN; |
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writel(rval, drvdata->reg_base + PS2_REG_LCTL); |
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/* Reset FIFO */ |
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rval = PS2_FCTL_TXRST | PS2_FCTL_RXRST | PS2_FCTL_TXUFIEN |
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| PS2_FCTL_TXOFIEN | PS2_FCTL_RXUFIEN |
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| PS2_FCTL_RXOFIEN | PS2_FCTL_RXRDYIEN; |
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writel(rval, drvdata->reg_base + PS2_REG_FCTL); |
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src_clk = clk_get_rate(drvdata->clk); |
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/* Set clock divider register */ |
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clk_scdf = src_clk / PS2_SAMPLE_CLK - 1; |
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clk_pcdf = PS2_SAMPLE_CLK / PS2_SCLK - 1; |
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rval = (clk_scdf << 8) | clk_pcdf; |
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writel(rval, drvdata->reg_base + PS2_REG_CLKDR); |
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/* Set global control register */ |
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rval = PS2_GCTL_RESET | PS2_GCTL_INTEN | PS2_GCTL_MASTER |
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| PS2_GCTL_BUSEN; |
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spin_lock_irqsave(&drvdata->lock, flags); |
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writel(rval, drvdata->reg_base + PS2_REG_GCTL); |
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spin_unlock_irqrestore(&drvdata->lock, flags); |
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return 0; |
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} |
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static void sun4i_ps2_close(struct serio *serio) |
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{ |
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struct sun4i_ps2data *drvdata = serio->port_data; |
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u32 rval; |
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/* Shut off the interrupt */ |
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rval = readl(drvdata->reg_base + PS2_REG_GCTL); |
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writel(rval & ~(PS2_GCTL_INTEN), drvdata->reg_base + PS2_REG_GCTL); |
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synchronize_irq(drvdata->irq); |
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} |
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static int sun4i_ps2_write(struct serio *serio, unsigned char val) |
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{ |
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unsigned long expire = jiffies + msecs_to_jiffies(10000); |
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struct sun4i_ps2data *drvdata = serio->port_data; |
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do { |
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if (readl(drvdata->reg_base + PS2_REG_FSTS) & PS2_FSTS_TXRDY) { |
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writel(val, drvdata->reg_base + PS2_REG_DATA); |
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return 0; |
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} |
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} while (time_before(jiffies, expire)); |
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return SERIO_TIMEOUT; |
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} |
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static int sun4i_ps2_probe(struct platform_device *pdev) |
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{ |
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struct resource *res; /* IO mem resources */ |
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struct sun4i_ps2data *drvdata; |
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struct serio *serio; |
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struct device *dev = &pdev->dev; |
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int error; |
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drvdata = kzalloc(sizeof(struct sun4i_ps2data), GFP_KERNEL); |
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serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
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if (!drvdata || !serio) { |
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error = -ENOMEM; |
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goto err_free_mem; |
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} |
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spin_lock_init(&drvdata->lock); |
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/* IO */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!res) { |
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dev_err(dev, "failed to locate registers\n"); |
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error = -ENXIO; |
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goto err_free_mem; |
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} |
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drvdata->reg_base = ioremap(res->start, resource_size(res)); |
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if (!drvdata->reg_base) { |
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dev_err(dev, "failed to map registers\n"); |
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error = -ENOMEM; |
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goto err_free_mem; |
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} |
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drvdata->clk = clk_get(dev, NULL); |
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if (IS_ERR(drvdata->clk)) { |
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error = PTR_ERR(drvdata->clk); |
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dev_err(dev, "couldn't get clock %d\n", error); |
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goto err_ioremap; |
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} |
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error = clk_prepare_enable(drvdata->clk); |
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if (error) { |
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dev_err(dev, "failed to enable clock %d\n", error); |
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goto err_clk; |
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} |
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serio->id.type = SERIO_8042; |
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serio->write = sun4i_ps2_write; |
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serio->open = sun4i_ps2_open; |
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serio->close = sun4i_ps2_close; |
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serio->port_data = drvdata; |
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serio->dev.parent = dev; |
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strlcpy(serio->name, dev_name(dev), sizeof(serio->name)); |
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strlcpy(serio->phys, dev_name(dev), sizeof(serio->phys)); |
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/* shutoff interrupt */ |
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writel(0, drvdata->reg_base + PS2_REG_GCTL); |
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/* Get IRQ for the device */ |
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drvdata->irq = platform_get_irq(pdev, 0); |
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if (drvdata->irq < 0) { |
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error = drvdata->irq; |
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goto err_disable_clk; |
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} |
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drvdata->serio = serio; |
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drvdata->dev = dev; |
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error = request_irq(drvdata->irq, sun4i_ps2_interrupt, 0, |
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DRIVER_NAME, drvdata); |
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if (error) { |
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dev_err(drvdata->dev, "failed to allocate interrupt %d: %d\n", |
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drvdata->irq, error); |
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goto err_disable_clk; |
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} |
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serio_register_port(serio); |
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platform_set_drvdata(pdev, drvdata); |
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return 0; /* success */ |
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err_disable_clk: |
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clk_disable_unprepare(drvdata->clk); |
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err_clk: |
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clk_put(drvdata->clk); |
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err_ioremap: |
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iounmap(drvdata->reg_base); |
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err_free_mem: |
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kfree(serio); |
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kfree(drvdata); |
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return error; |
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} |
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static int sun4i_ps2_remove(struct platform_device *pdev) |
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{ |
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struct sun4i_ps2data *drvdata = platform_get_drvdata(pdev); |
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serio_unregister_port(drvdata->serio); |
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free_irq(drvdata->irq, drvdata); |
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clk_disable_unprepare(drvdata->clk); |
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clk_put(drvdata->clk); |
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iounmap(drvdata->reg_base); |
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kfree(drvdata); |
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return 0; |
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} |
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static const struct of_device_id sun4i_ps2_match[] = { |
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{ .compatible = "allwinner,sun4i-a10-ps2", }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, sun4i_ps2_match); |
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static struct platform_driver sun4i_ps2_driver = { |
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.probe = sun4i_ps2_probe, |
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.remove = sun4i_ps2_remove, |
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.driver = { |
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.name = DRIVER_NAME, |
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.of_match_table = sun4i_ps2_match, |
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}, |
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}; |
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module_platform_driver(sun4i_ps2_driver); |
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MODULE_AUTHOR("Vishnu Patekar <[email protected]>"); |
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MODULE_AUTHOR("Aaron.maoye <[email protected]>"); |
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MODULE_DESCRIPTION("Allwinner A10/Sun4i PS/2 driver"); |
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MODULE_LICENSE("GPL v2");
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