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715 lines
20 KiB
715 lines
20 KiB
/* |
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* Copyright (C) 2004 Red Hat |
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* Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
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* |
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* May be copied or modified under the terms of the GNU General Public License |
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* Based in part on the ITE vendor provided SCSI driver. |
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* |
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* Documentation: |
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* Datasheet is freely available, some other documents under NDA. |
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* |
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* The ITE8212 isn't exactly a standard IDE controller. It has two |
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* modes. In pass through mode then it is an IDE controller. In its smart |
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* mode its actually quite a capable hardware raid controller disguised |
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* as an IDE controller. Smart mode only understands DMA read/write and |
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* identify, none of the fancier commands apply. The IT8211 is identical |
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* in other respects but lacks the raid mode. |
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* |
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* Errata: |
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* o Rev 0x10 also requires master/slave hold the same DMA timings and |
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* cannot do ATAPI MWDMA. |
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* o The identify data for raid volumes lacks CHS info (technically ok) |
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* but also fails to set the LBA28 and other bits. We fix these in |
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* the IDE probe quirk code. |
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* o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode |
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* raid then the controller firmware dies |
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* o Smart mode without RAID doesn't clear all the necessary identify |
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* bits to reduce the command set to the one used |
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* |
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* This has a few impacts on the driver |
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* - In pass through mode we do all the work you would expect |
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* - In smart mode the clocking set up is done by the controller generally |
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* but we must watch the other limits and filter. |
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* - There are a few extra vendor commands that actually talk to the |
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* controller but only work PIO with no IRQ. |
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* |
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* Vendor areas of the identify block in smart mode are used for the |
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* timing and policy set up. Each HDD in raid mode also has a serial |
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* block on the disk. The hardware extra commands are get/set chip status, |
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* rebuild, get rebuild status. |
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* |
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* In Linux the driver supports pass through mode as if the device was |
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* just another IDE controller. If the smart mode is running then |
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* volumes are managed by the controller firmware and each IDE "disk" |
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* is a raid volume. Even more cute - the controller can do automated |
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* hotplug and rebuild. |
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* |
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* The pass through controller itself is a little demented. It has a |
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* flaw that it has a single set of PIO/MWDMA timings per channel so |
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* non UDMA devices restrict each others performance. It also has a |
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* single clock source per channel so mixed UDMA100/133 performance |
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* isn't perfect and we have to pick a clock. Thankfully none of this |
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* matters in smart mode. ATAPI DMA is not currently supported. |
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* |
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* It seems the smart mode is a win for RAID1/RAID10 but otherwise not. |
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* |
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* TODO |
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* - ATAPI UDMA is ok but not MWDMA it seems |
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* - RAID configuration ioctls |
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* - Move to libata once it grows up |
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*/ |
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|
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#include <linux/types.h> |
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#include <linux/module.h> |
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#include <linux/slab.h> |
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#include <linux/pci.h> |
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#include <linux/ide.h> |
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#include <linux/init.h> |
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#define DRV_NAME "it821x" |
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#define QUIRK_VORTEX86 1 |
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struct it821x_dev |
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{ |
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unsigned int smart:1, /* Are we in smart raid mode */ |
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timing10:1; /* Rev 0x10 */ |
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u8 clock_mode; /* 0, ATA_50 or ATA_66 */ |
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u8 want[2][2]; /* Mode/Pri log for master slave */ |
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/* We need these for switching the clock when DMA goes on/off |
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The high byte is the 66Mhz timing */ |
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u16 pio[2]; /* Cached PIO values */ |
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u16 mwdma[2]; /* Cached MWDMA values */ |
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u16 udma[2]; /* Cached UDMA values (per drive) */ |
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u16 quirks; |
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}; |
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#define ATA_66 0 |
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#define ATA_50 1 |
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#define ATA_ANY 2 |
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#define UDMA_OFF 0 |
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#define MWDMA_OFF 0 |
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/* |
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* We allow users to force the card into non raid mode without |
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* flashing the alternative BIOS. This is also necessary right now |
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* for embedded platforms that cannot run a PC BIOS but are using this |
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* device. |
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*/ |
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static int it8212_noraid; |
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/** |
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* it821x_program - program the PIO/MWDMA registers |
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* @drive: drive to tune |
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* @timing: timing info |
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* |
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* Program the PIO/MWDMA timing for this channel according to the |
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* current clock. |
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*/ |
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static void it821x_program(ide_drive_t *drive, u16 timing) |
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{ |
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ide_hwif_t *hwif = drive->hwif; |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
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int channel = hwif->channel; |
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u8 conf; |
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/* Program PIO/MWDMA timing bits */ |
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if(itdev->clock_mode == ATA_66) |
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conf = timing >> 8; |
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else |
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conf = timing & 0xFF; |
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pci_write_config_byte(dev, 0x54 + 4 * channel, conf); |
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} |
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/** |
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* it821x_program_udma - program the UDMA registers |
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* @drive: drive to tune |
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* @timing: timing info |
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* |
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* Program the UDMA timing for this drive according to the |
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* current clock. |
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*/ |
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static void it821x_program_udma(ide_drive_t *drive, u16 timing) |
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{ |
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ide_hwif_t *hwif = drive->hwif; |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
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int channel = hwif->channel; |
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u8 unit = drive->dn & 1, conf; |
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/* Program UDMA timing bits */ |
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if(itdev->clock_mode == ATA_66) |
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conf = timing >> 8; |
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else |
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conf = timing & 0xFF; |
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if (itdev->timing10 == 0) |
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pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf); |
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else { |
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pci_write_config_byte(dev, 0x56 + 4 * channel, conf); |
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pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf); |
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} |
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} |
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/** |
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* it821x_clock_strategy |
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* @drive: drive to set up |
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* |
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* Select between the 50 and 66Mhz base clocks to get the best |
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* results for this interface. |
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*/ |
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static void it821x_clock_strategy(ide_drive_t *drive) |
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{ |
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ide_hwif_t *hwif = drive->hwif; |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
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ide_drive_t *pair = ide_get_pair_dev(drive); |
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int clock, altclock, sel = 0; |
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u8 unit = drive->dn & 1, v; |
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if(itdev->want[0][0] > itdev->want[1][0]) { |
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clock = itdev->want[0][1]; |
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altclock = itdev->want[1][1]; |
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} else { |
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clock = itdev->want[1][1]; |
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altclock = itdev->want[0][1]; |
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} |
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/* |
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* if both clocks can be used for the mode with the higher priority |
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* use the clock needed by the mode with the lower priority |
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*/ |
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if (clock == ATA_ANY) |
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clock = altclock; |
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/* Nobody cares - keep the same clock */ |
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if(clock == ATA_ANY) |
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return; |
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/* No change */ |
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if(clock == itdev->clock_mode) |
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return; |
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/* Load this into the controller ? */ |
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if(clock == ATA_66) |
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itdev->clock_mode = ATA_66; |
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else { |
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itdev->clock_mode = ATA_50; |
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sel = 1; |
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} |
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pci_read_config_byte(dev, 0x50, &v); |
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v &= ~(1 << (1 + hwif->channel)); |
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v |= sel << (1 + hwif->channel); |
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pci_write_config_byte(dev, 0x50, v); |
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/* |
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* Reprogram the UDMA/PIO of the pair drive for the switch |
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* MWDMA will be dealt with by the dma switcher |
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*/ |
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if(pair && itdev->udma[1-unit] != UDMA_OFF) { |
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it821x_program_udma(pair, itdev->udma[1-unit]); |
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it821x_program(pair, itdev->pio[1-unit]); |
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} |
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/* |
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* Reprogram the UDMA/PIO of our drive for the switch. |
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* MWDMA will be dealt with by the dma switcher |
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*/ |
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if(itdev->udma[unit] != UDMA_OFF) { |
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it821x_program_udma(drive, itdev->udma[unit]); |
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it821x_program(drive, itdev->pio[unit]); |
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} |
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} |
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/** |
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* it821x_set_pio_mode - set host controller for PIO mode |
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* @hwif: port |
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* @drive: drive |
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* |
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* Tune the host to the desired PIO mode taking into the consideration |
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* the maximum PIO mode supported by the other device on the cable. |
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*/ |
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static void it821x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
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{ |
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struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
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ide_drive_t *pair = ide_get_pair_dev(drive); |
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const u8 pio = drive->pio_mode - XFER_PIO_0; |
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u8 unit = drive->dn & 1, set_pio = pio; |
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/* Spec says 89 ref driver uses 88 */ |
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static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 }; |
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static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY }; |
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/* |
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* Compute the best PIO mode we can for a given device. We must |
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* pick a speed that does not cause problems with the other device |
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* on the cable. |
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*/ |
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if (pair) { |
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u8 pair_pio = pair->pio_mode - XFER_PIO_0; |
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/* trim PIO to the slowest of the master/slave */ |
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if (pair_pio < set_pio) |
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set_pio = pair_pio; |
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} |
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/* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */ |
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itdev->want[unit][1] = pio_want[set_pio]; |
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itdev->want[unit][0] = 1; /* PIO is lowest priority */ |
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itdev->pio[unit] = pio_timings[set_pio]; |
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it821x_clock_strategy(drive); |
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it821x_program(drive, itdev->pio[unit]); |
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} |
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/** |
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* it821x_tune_mwdma - tune a channel for MWDMA |
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* @drive: drive to set up |
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* @mode_wanted: the target operating mode |
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* |
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* Load the timing settings for this device mode into the |
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* controller when doing MWDMA in pass through mode. The caller |
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* must manage the whole lack of per device MWDMA/PIO timings and |
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* the shared MWDMA/PIO timing register. |
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*/ |
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static void it821x_tune_mwdma(ide_drive_t *drive, u8 mode_wanted) |
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{ |
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ide_hwif_t *hwif = drive->hwif; |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif); |
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u8 unit = drive->dn & 1, channel = hwif->channel, conf; |
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static u16 dma[] = { 0x8866, 0x3222, 0x3121 }; |
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static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY }; |
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itdev->want[unit][1] = mwdma_want[mode_wanted]; |
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itdev->want[unit][0] = 2; /* MWDMA is low priority */ |
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itdev->mwdma[unit] = dma[mode_wanted]; |
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itdev->udma[unit] = UDMA_OFF; |
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/* UDMA bits off - Revision 0x10 do them in pairs */ |
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pci_read_config_byte(dev, 0x50, &conf); |
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if (itdev->timing10) |
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conf |= channel ? 0x60: 0x18; |
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else |
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conf |= 1 << (3 + 2 * channel + unit); |
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pci_write_config_byte(dev, 0x50, conf); |
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it821x_clock_strategy(drive); |
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/* FIXME: do we need to program this ? */ |
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/* it821x_program(drive, itdev->mwdma[unit]); */ |
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} |
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/** |
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* it821x_tune_udma - tune a channel for UDMA |
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* @drive: drive to set up |
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* @mode_wanted: the target operating mode |
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* |
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* Load the timing settings for this device mode into the |
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* controller when doing UDMA modes in pass through. |
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*/ |
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static void it821x_tune_udma(ide_drive_t *drive, u8 mode_wanted) |
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{ |
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ide_hwif_t *hwif = drive->hwif; |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
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u8 unit = drive->dn & 1, channel = hwif->channel, conf; |
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static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 }; |
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static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 }; |
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itdev->want[unit][1] = udma_want[mode_wanted]; |
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itdev->want[unit][0] = 3; /* UDMA is high priority */ |
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itdev->mwdma[unit] = MWDMA_OFF; |
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itdev->udma[unit] = udma[mode_wanted]; |
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if(mode_wanted >= 5) |
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itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */ |
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/* UDMA on. Again revision 0x10 must do the pair */ |
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pci_read_config_byte(dev, 0x50, &conf); |
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if (itdev->timing10) |
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conf &= channel ? 0x9F: 0xE7; |
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else |
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conf &= ~ (1 << (3 + 2 * channel + unit)); |
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pci_write_config_byte(dev, 0x50, conf); |
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it821x_clock_strategy(drive); |
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it821x_program_udma(drive, itdev->udma[unit]); |
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} |
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/** |
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* it821x_dma_read - DMA hook |
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* @drive: drive for DMA |
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* |
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* The IT821x has a single timing register for MWDMA and for PIO |
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* operations. As we flip back and forth we have to reload the |
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* clock. In addition the rev 0x10 device only works if the same |
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* timing value is loaded into the master and slave UDMA clock |
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* so we must also reload that. |
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* |
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* FIXME: we could figure out in advance if we need to do reloads |
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*/ |
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static void it821x_dma_start(ide_drive_t *drive) |
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{ |
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ide_hwif_t *hwif = drive->hwif; |
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struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
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u8 unit = drive->dn & 1; |
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if(itdev->mwdma[unit] != MWDMA_OFF) |
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it821x_program(drive, itdev->mwdma[unit]); |
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else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10) |
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it821x_program_udma(drive, itdev->udma[unit]); |
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ide_dma_start(drive); |
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} |
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/** |
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* it821x_dma_write - DMA hook |
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* @drive: drive for DMA stop |
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* |
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* The IT821x has a single timing register for MWDMA and for PIO |
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* operations. As we flip back and forth we have to reload the |
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* clock. |
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*/ |
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static int it821x_dma_end(ide_drive_t *drive) |
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{ |
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ide_hwif_t *hwif = drive->hwif; |
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struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
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int ret = ide_dma_end(drive); |
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u8 unit = drive->dn & 1; |
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if(itdev->mwdma[unit] != MWDMA_OFF) |
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it821x_program(drive, itdev->pio[unit]); |
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return ret; |
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} |
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/** |
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* it821x_set_dma_mode - set host controller for DMA mode |
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* @hwif: port |
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* @drive: drive |
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* |
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* Tune the ITE chipset for the desired DMA mode. |
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*/ |
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static void it821x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
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{ |
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const u8 speed = drive->dma_mode; |
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|
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/* |
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* MWDMA tuning is really hard because our MWDMA and PIO |
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* timings are kept in the same place. We can switch in the |
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* host dma on/off callbacks. |
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*/ |
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if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6) |
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it821x_tune_udma(drive, speed - XFER_UDMA_0); |
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else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) |
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it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0); |
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} |
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/** |
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* it821x_cable_detect - cable detection |
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* @hwif: interface to check |
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* |
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* Check for the presence of an ATA66 capable cable on the |
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* interface. Problematic as it seems some cards don't have |
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* the needed logic onboard. |
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*/ |
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static u8 it821x_cable_detect(ide_hwif_t *hwif) |
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{ |
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/* The reference driver also only does disk side */ |
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return ATA_CBL_PATA80; |
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} |
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|
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/** |
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* it821x_quirkproc - post init callback |
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* @drive: drive |
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* |
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* This callback is run after the drive has been probed but |
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* before anything gets attached. It allows drivers to do any |
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* final tuning that is needed, or fixups to work around bugs. |
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*/ |
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static void it821x_quirkproc(ide_drive_t *drive) |
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{ |
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struct it821x_dev *itdev = ide_get_hwifdata(drive->hwif); |
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u16 *id = drive->id; |
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|
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if (!itdev->smart) { |
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/* |
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* If we are in pass through mode then not much |
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* needs to be done, but we do bother to clear the |
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* IRQ mask as we may well be in PIO (eg rev 0x10) |
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* for now and we know unmasking is safe on this chipset. |
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*/ |
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drive->dev_flags |= IDE_DFLAG_UNMASK; |
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} else { |
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/* |
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* Perform fixups on smart mode. We need to "lose" some |
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* capabilities the firmware lacks but does not filter, and |
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* also patch up some capability bits that it forgets to set |
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* in RAID mode. |
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*/ |
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|
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/* Check for RAID v native */ |
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if (strstr((char *)&id[ATA_ID_PROD], |
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"Integrated Technology Express")) { |
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/* In raid mode the ident block is slightly buggy |
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We need to set the bits so that the IDE layer knows |
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LBA28. LBA48 and DMA ar valid */ |
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id[ATA_ID_CAPABILITY] |= (3 << 8); /* LBA28, DMA */ |
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id[ATA_ID_COMMAND_SET_2] |= 0x0400; /* LBA48 valid */ |
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id[ATA_ID_CFS_ENABLE_2] |= 0x0400; /* LBA48 on */ |
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/* Reporting logic */ |
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printk(KERN_INFO "%s: IT8212 %sRAID %d volume", |
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drive->name, id[147] ? "Bootable " : "", |
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id[ATA_ID_CSFO]); |
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if (id[ATA_ID_CSFO] != 1) |
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printk(KERN_CONT "(%dK stripe)", id[146]); |
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printk(KERN_CONT ".\n"); |
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} else { |
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/* Non RAID volume. Fixups to stop the core code |
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doing unsupported things */ |
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id[ATA_ID_FIELD_VALID] &= 3; |
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id[ATA_ID_QUEUE_DEPTH] = 0; |
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id[ATA_ID_COMMAND_SET_1] = 0; |
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id[ATA_ID_COMMAND_SET_2] &= 0xC400; |
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id[ATA_ID_CFSSE] &= 0xC000; |
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id[ATA_ID_CFS_ENABLE_1] = 0; |
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id[ATA_ID_CFS_ENABLE_2] &= 0xC400; |
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id[ATA_ID_CSF_DEFAULT] &= 0xC000; |
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id[127] = 0; |
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id[ATA_ID_DLF] = 0; |
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id[ATA_ID_CSFO] = 0; |
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id[ATA_ID_CFA_POWER] = 0; |
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printk(KERN_INFO "%s: Performing identify fixups.\n", |
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drive->name); |
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} |
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|
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/* |
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* Set MWDMA0 mode as enabled/support - just to tell |
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* IDE core that DMA is supported (it821x hardware |
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* takes care of DMA mode programming). |
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*/ |
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if (ata_id_has_dma(id)) { |
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id[ATA_ID_MWDMA_MODES] |= 0x0101; |
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drive->current_speed = XFER_MW_DMA_0; |
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} |
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} |
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|
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} |
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|
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static const struct ide_dma_ops it821x_pass_through_dma_ops = { |
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.dma_host_set = ide_dma_host_set, |
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.dma_setup = ide_dma_setup, |
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.dma_start = it821x_dma_start, |
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.dma_end = it821x_dma_end, |
|
.dma_test_irq = ide_dma_test_irq, |
|
.dma_lost_irq = ide_dma_lost_irq, |
|
.dma_timer_expiry = ide_dma_sff_timer_expiry, |
|
.dma_sff_read_status = ide_dma_sff_read_status, |
|
}; |
|
|
|
/** |
|
* init_hwif_it821x - set up hwif structs |
|
* @hwif: interface to set up |
|
* |
|
* We do the basic set up of the interface structure. The IT8212 |
|
* requires several custom handlers so we override the default |
|
* ide DMA handlers appropriately |
|
*/ |
|
|
|
static void init_hwif_it821x(ide_hwif_t *hwif) |
|
{ |
|
struct pci_dev *dev = to_pci_dev(hwif->dev); |
|
struct ide_host *host = pci_get_drvdata(dev); |
|
struct it821x_dev *itdevs = host->host_priv; |
|
struct it821x_dev *idev = itdevs + hwif->channel; |
|
u8 conf; |
|
|
|
ide_set_hwifdata(hwif, idev); |
|
|
|
pci_read_config_byte(dev, 0x50, &conf); |
|
if (conf & 1) { |
|
idev->smart = 1; |
|
hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; |
|
/* Long I/O's although allowed in LBA48 space cause the |
|
onboard firmware to enter the twighlight zone */ |
|
hwif->rqsize = 256; |
|
} |
|
|
|
/* Pull the current clocks from 0x50 also */ |
|
if (conf & (1 << (1 + hwif->channel))) |
|
idev->clock_mode = ATA_50; |
|
else |
|
idev->clock_mode = ATA_66; |
|
|
|
idev->want[0][1] = ATA_ANY; |
|
idev->want[1][1] = ATA_ANY; |
|
|
|
/* |
|
* Not in the docs but according to the reference driver |
|
* this is necessary. |
|
*/ |
|
|
|
if (dev->revision == 0x10) { |
|
idev->timing10 = 1; |
|
hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; |
|
if (idev->smart == 0) |
|
printk(KERN_WARNING DRV_NAME " %s: revision 0x10, " |
|
"workarounds activated\n", pci_name(dev)); |
|
} |
|
|
|
if (idev->smart == 0) { |
|
/* MWDMA/PIO clock switching for pass through mode */ |
|
hwif->dma_ops = &it821x_pass_through_dma_ops; |
|
} else |
|
hwif->host_flags |= IDE_HFLAG_NO_SET_MODE; |
|
|
|
if (hwif->dma_base == 0) |
|
return; |
|
|
|
hwif->ultra_mask = ATA_UDMA6; |
|
hwif->mwdma_mask = ATA_MWDMA2; |
|
|
|
/* Vortex86SX quirk: prevent Ultra-DMA mode to fix BadCRC issue */ |
|
if (idev->quirks & QUIRK_VORTEX86) { |
|
if (dev->revision == 0x11) |
|
hwif->ultra_mask = 0; |
|
} |
|
} |
|
|
|
static void it8212_disable_raid(struct pci_dev *dev) |
|
{ |
|
/* Reset local CPU, and set BIOS not ready */ |
|
pci_write_config_byte(dev, 0x5E, 0x01); |
|
|
|
/* Set to bypass mode, and reset PCI bus */ |
|
pci_write_config_byte(dev, 0x50, 0x00); |
|
pci_write_config_word(dev, PCI_COMMAND, |
|
PCI_COMMAND_PARITY | PCI_COMMAND_IO | |
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
|
pci_write_config_word(dev, 0x40, 0xA0F3); |
|
|
|
pci_write_config_dword(dev,0x4C, 0x02040204); |
|
pci_write_config_byte(dev, 0x42, 0x36); |
|
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); |
|
} |
|
|
|
static int init_chipset_it821x(struct pci_dev *dev) |
|
{ |
|
u8 conf; |
|
static char *mode[2] = { "pass through", "smart" }; |
|
|
|
/* Force the card into bypass mode if so requested */ |
|
if (it8212_noraid) { |
|
printk(KERN_INFO DRV_NAME " %s: forcing bypass mode\n", |
|
pci_name(dev)); |
|
it8212_disable_raid(dev); |
|
} |
|
pci_read_config_byte(dev, 0x50, &conf); |
|
printk(KERN_INFO DRV_NAME " %s: controller in %s mode\n", |
|
pci_name(dev), mode[conf & 1]); |
|
return 0; |
|
} |
|
|
|
static const struct ide_port_ops it821x_port_ops = { |
|
/* it821x_set_{pio,dma}_mode() are only used in pass-through mode */ |
|
.set_pio_mode = it821x_set_pio_mode, |
|
.set_dma_mode = it821x_set_dma_mode, |
|
.quirkproc = it821x_quirkproc, |
|
.cable_detect = it821x_cable_detect, |
|
}; |
|
|
|
static const struct ide_port_info it821x_chipset = { |
|
.name = DRV_NAME, |
|
.init_chipset = init_chipset_it821x, |
|
.init_hwif = init_hwif_it821x, |
|
.port_ops = &it821x_port_ops, |
|
.pio_mask = ATA_PIO4, |
|
}; |
|
|
|
/** |
|
* it821x_init_one - pci layer discovery entry |
|
* @dev: PCI device |
|
* @id: ident table entry |
|
* |
|
* Called by the PCI code when it finds an ITE821x controller. |
|
* We then use the IDE PCI generic helper to do most of the work. |
|
*/ |
|
|
|
static int it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
|
{ |
|
struct it821x_dev *itdevs; |
|
int rc; |
|
|
|
itdevs = kcalloc(2, sizeof(*itdevs), GFP_KERNEL); |
|
if (itdevs == NULL) { |
|
printk(KERN_ERR DRV_NAME " %s: out of memory\n", pci_name(dev)); |
|
return -ENOMEM; |
|
} |
|
|
|
itdevs->quirks = id->driver_data; |
|
|
|
rc = ide_pci_init_one(dev, &it821x_chipset, itdevs); |
|
if (rc) |
|
kfree(itdevs); |
|
|
|
return rc; |
|
} |
|
|
|
static void it821x_remove(struct pci_dev *dev) |
|
{ |
|
struct ide_host *host = pci_get_drvdata(dev); |
|
struct it821x_dev *itdevs = host->host_priv; |
|
|
|
ide_pci_remove(dev); |
|
kfree(itdevs); |
|
} |
|
|
|
static const struct pci_device_id it821x_pci_tbl[] = { |
|
{ PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 }, |
|
{ PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 }, |
|
{ PCI_VDEVICE(RDC, PCI_DEVICE_ID_RDC_D1010), QUIRK_VORTEX86 }, |
|
{ 0, }, |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(pci, it821x_pci_tbl); |
|
|
|
static struct pci_driver it821x_pci_driver = { |
|
.name = "ITE821x IDE", |
|
.id_table = it821x_pci_tbl, |
|
.probe = it821x_init_one, |
|
.remove = it821x_remove, |
|
.suspend = ide_pci_suspend, |
|
.resume = ide_pci_resume, |
|
}; |
|
|
|
static int __init it821x_ide_init(void) |
|
{ |
|
return ide_pci_register_driver(&it821x_pci_driver); |
|
} |
|
|
|
static void __exit it821x_ide_exit(void) |
|
{ |
|
pci_unregister_driver(&it821x_pci_driver); |
|
} |
|
|
|
module_init(it821x_ide_init); |
|
module_exit(it821x_ide_exit); |
|
|
|
module_param_named(noraid, it8212_noraid, int, S_IRUGO); |
|
MODULE_PARM_DESC(noraid, "Force card into bypass mode"); |
|
|
|
MODULE_AUTHOR("Alan Cox"); |
|
MODULE_DESCRIPTION("PCI driver module for the ITE 821x"); |
|
MODULE_LICENSE("GPL");
|
|
|