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328 lines
7.3 KiB
328 lines
7.3 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* linux/arch/arm/mach-sa1100/gpio.c |
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* |
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* Generic SA-1100 GPIO handling |
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*/ |
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#include <linux/gpio/driver.h> |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/io.h> |
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#include <linux/syscore_ops.h> |
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#include <soc/sa1100/pwer.h> |
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#include <mach/hardware.h> |
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#include <mach/irqs.h> |
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struct sa1100_gpio_chip { |
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struct gpio_chip chip; |
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void __iomem *membase; |
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int irqbase; |
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u32 irqmask; |
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u32 irqrising; |
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u32 irqfalling; |
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u32 irqwake; |
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}; |
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#define sa1100_gpio_chip(x) container_of(x, struct sa1100_gpio_chip, chip) |
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enum { |
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R_GPLR = 0x00, |
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R_GPDR = 0x04, |
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R_GPSR = 0x08, |
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R_GPCR = 0x0c, |
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R_GRER = 0x10, |
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R_GFER = 0x14, |
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R_GEDR = 0x18, |
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R_GAFR = 0x1c, |
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}; |
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static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset) |
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{ |
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return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) & |
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BIT(offset); |
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} |
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static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
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{ |
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int reg = value ? R_GPSR : R_GPCR; |
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writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); |
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} |
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static int sa1100_get_direction(struct gpio_chip *chip, unsigned offset) |
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{ |
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void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; |
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if (readl_relaxed(gpdr) & BIT(offset)) |
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return GPIO_LINE_DIRECTION_OUT; |
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return GPIO_LINE_DIRECTION_IN; |
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} |
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static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset) |
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{ |
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void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; |
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unsigned long flags; |
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local_irq_save(flags); |
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writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr); |
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local_irq_restore(flags); |
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return 0; |
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} |
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static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value) |
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{ |
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void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; |
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unsigned long flags; |
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local_irq_save(flags); |
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sa1100_gpio_set(chip, offset, value); |
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writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr); |
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local_irq_restore(flags); |
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return 0; |
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} |
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static int sa1100_to_irq(struct gpio_chip *chip, unsigned offset) |
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{ |
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return sa1100_gpio_chip(chip)->irqbase + offset; |
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} |
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static struct sa1100_gpio_chip sa1100_gpio_chip = { |
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.chip = { |
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.label = "gpio", |
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.get_direction = sa1100_get_direction, |
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.direction_input = sa1100_direction_input, |
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.direction_output = sa1100_direction_output, |
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.set = sa1100_gpio_set, |
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.get = sa1100_gpio_get, |
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.to_irq = sa1100_to_irq, |
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.base = 0, |
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.ngpio = GPIO_MAX + 1, |
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}, |
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.membase = (void *)&GPLR, |
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.irqbase = IRQ_GPIO0, |
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}; |
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/* |
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* SA1100 GPIO edge detection for IRQs: |
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* IRQs are generated on Falling-Edge, Rising-Edge, or both. |
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* Use this instead of directly setting GRER/GFER. |
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*/ |
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static void sa1100_update_edge_regs(struct sa1100_gpio_chip *sgc) |
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{ |
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void *base = sgc->membase; |
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u32 grer, gfer; |
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grer = sgc->irqrising & sgc->irqmask; |
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gfer = sgc->irqfalling & sgc->irqmask; |
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writel_relaxed(grer, base + R_GRER); |
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writel_relaxed(gfer, base + R_GFER); |
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} |
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static int sa1100_gpio_type(struct irq_data *d, unsigned int type) |
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{ |
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struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); |
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unsigned int mask = BIT(d->hwirq); |
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if (type == IRQ_TYPE_PROBE) { |
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if ((sgc->irqrising | sgc->irqfalling) & mask) |
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return 0; |
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type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
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} |
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if (type & IRQ_TYPE_EDGE_RISING) |
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sgc->irqrising |= mask; |
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else |
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sgc->irqrising &= ~mask; |
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if (type & IRQ_TYPE_EDGE_FALLING) |
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sgc->irqfalling |= mask; |
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else |
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sgc->irqfalling &= ~mask; |
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sa1100_update_edge_regs(sgc); |
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return 0; |
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} |
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/* |
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* GPIO IRQs must be acknowledged. |
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*/ |
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static void sa1100_gpio_ack(struct irq_data *d) |
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{ |
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struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); |
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writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR); |
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} |
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static void sa1100_gpio_mask(struct irq_data *d) |
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{ |
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struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); |
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unsigned int mask = BIT(d->hwirq); |
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sgc->irqmask &= ~mask; |
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sa1100_update_edge_regs(sgc); |
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} |
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static void sa1100_gpio_unmask(struct irq_data *d) |
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{ |
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struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); |
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unsigned int mask = BIT(d->hwirq); |
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sgc->irqmask |= mask; |
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sa1100_update_edge_regs(sgc); |
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} |
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static int sa1100_gpio_wake(struct irq_data *d, unsigned int on) |
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{ |
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struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); |
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int ret = sa11x0_gpio_set_wake(d->hwirq, on); |
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if (!ret) { |
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if (on) |
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sgc->irqwake |= BIT(d->hwirq); |
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else |
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sgc->irqwake &= ~BIT(d->hwirq); |
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} |
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return ret; |
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} |
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/* |
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* This is for GPIO IRQs |
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*/ |
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static struct irq_chip sa1100_gpio_irq_chip = { |
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.name = "GPIO", |
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.irq_ack = sa1100_gpio_ack, |
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.irq_mask = sa1100_gpio_mask, |
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.irq_unmask = sa1100_gpio_unmask, |
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.irq_set_type = sa1100_gpio_type, |
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.irq_set_wake = sa1100_gpio_wake, |
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}; |
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static int sa1100_gpio_irqdomain_map(struct irq_domain *d, |
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unsigned int irq, irq_hw_number_t hwirq) |
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{ |
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struct sa1100_gpio_chip *sgc = d->host_data; |
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irq_set_chip_data(irq, sgc); |
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irq_set_chip_and_handler(irq, &sa1100_gpio_irq_chip, handle_edge_irq); |
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irq_set_probe(irq); |
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return 0; |
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} |
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static const struct irq_domain_ops sa1100_gpio_irqdomain_ops = { |
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.map = sa1100_gpio_irqdomain_map, |
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.xlate = irq_domain_xlate_onetwocell, |
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}; |
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static struct irq_domain *sa1100_gpio_irqdomain; |
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/* |
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* IRQ 0-11 (GPIO) handler. We enter here with the |
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* irq_controller_lock held, and IRQs disabled. Decode the IRQ |
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* and call the handler. |
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*/ |
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static void sa1100_gpio_handler(struct irq_desc *desc) |
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{ |
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struct sa1100_gpio_chip *sgc = irq_desc_get_handler_data(desc); |
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unsigned int irq, mask; |
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void __iomem *gedr = sgc->membase + R_GEDR; |
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mask = readl_relaxed(gedr); |
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do { |
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/* |
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* clear down all currently active IRQ sources. |
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* We will be processing them all. |
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*/ |
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writel_relaxed(mask, gedr); |
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irq = sgc->irqbase; |
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do { |
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if (mask & 1) |
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generic_handle_irq(irq); |
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mask >>= 1; |
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irq++; |
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} while (mask); |
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mask = readl_relaxed(gedr); |
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} while (mask); |
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} |
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static int sa1100_gpio_suspend(void) |
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{ |
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struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip; |
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/* |
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* Set the appropriate edges for wakeup. |
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*/ |
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writel_relaxed(sgc->irqwake & sgc->irqrising, sgc->membase + R_GRER); |
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writel_relaxed(sgc->irqwake & sgc->irqfalling, sgc->membase + R_GFER); |
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/* |
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* Clear any pending GPIO interrupts. |
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*/ |
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writel_relaxed(readl_relaxed(sgc->membase + R_GEDR), |
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sgc->membase + R_GEDR); |
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return 0; |
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} |
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static void sa1100_gpio_resume(void) |
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{ |
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sa1100_update_edge_regs(&sa1100_gpio_chip); |
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} |
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static struct syscore_ops sa1100_gpio_syscore_ops = { |
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.suspend = sa1100_gpio_suspend, |
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.resume = sa1100_gpio_resume, |
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}; |
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static int __init sa1100_gpio_init_devicefs(void) |
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{ |
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register_syscore_ops(&sa1100_gpio_syscore_ops); |
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return 0; |
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} |
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device_initcall(sa1100_gpio_init_devicefs); |
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static const int sa1100_gpio_irqs[] __initconst = { |
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/* Install handlers for GPIO 0-10 edge detect interrupts */ |
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IRQ_GPIO0_SC, |
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IRQ_GPIO1_SC, |
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IRQ_GPIO2_SC, |
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IRQ_GPIO3_SC, |
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IRQ_GPIO4_SC, |
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IRQ_GPIO5_SC, |
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IRQ_GPIO6_SC, |
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IRQ_GPIO7_SC, |
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IRQ_GPIO8_SC, |
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IRQ_GPIO9_SC, |
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IRQ_GPIO10_SC, |
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/* Install handler for GPIO 11-27 edge detect interrupts */ |
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IRQ_GPIO11_27, |
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}; |
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void __init sa1100_init_gpio(void) |
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{ |
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struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip; |
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int i; |
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/* clear all GPIO edge detects */ |
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writel_relaxed(0, sgc->membase + R_GFER); |
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writel_relaxed(0, sgc->membase + R_GRER); |
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writel_relaxed(-1, sgc->membase + R_GEDR); |
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gpiochip_add_data(&sa1100_gpio_chip.chip, NULL); |
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sa1100_gpio_irqdomain = irq_domain_add_simple(NULL, |
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28, IRQ_GPIO0, |
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&sa1100_gpio_irqdomain_ops, sgc); |
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for (i = 0; i < ARRAY_SIZE(sa1100_gpio_irqs); i++) |
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irq_set_chained_handler_and_data(sa1100_gpio_irqs[i], |
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sa1100_gpio_handler, sgc); |
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}
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