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426 lines
11 KiB
426 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2008, 2009 Provigent Ltd. |
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* |
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* Author: Baruch Siach <[email protected]> |
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* |
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* Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061) |
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* |
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* Data sheet: ARM DDI 0190B, September 2000 |
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*/ |
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#include <linux/spinlock.h> |
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#include <linux/errno.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/ioport.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/module.h> |
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#include <linux/bitops.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/device.h> |
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#include <linux/amba/bus.h> |
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#include <linux/slab.h> |
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#include <linux/pinctrl/consumer.h> |
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#include <linux/pm.h> |
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#define GPIODIR 0x400 |
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#define GPIOIS 0x404 |
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#define GPIOIBE 0x408 |
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#define GPIOIEV 0x40C |
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#define GPIOIE 0x410 |
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#define GPIORIS 0x414 |
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#define GPIOMIS 0x418 |
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#define GPIOIC 0x41C |
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#define PL061_GPIO_NR 8 |
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#ifdef CONFIG_PM |
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struct pl061_context_save_regs { |
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u8 gpio_data; |
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u8 gpio_dir; |
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u8 gpio_is; |
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u8 gpio_ibe; |
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u8 gpio_iev; |
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u8 gpio_ie; |
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}; |
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#endif |
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struct pl061 { |
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raw_spinlock_t lock; |
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void __iomem *base; |
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struct gpio_chip gc; |
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struct irq_chip irq_chip; |
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int parent_irq; |
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#ifdef CONFIG_PM |
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struct pl061_context_save_regs csave_regs; |
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#endif |
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}; |
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static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) |
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{ |
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struct pl061 *pl061 = gpiochip_get_data(gc); |
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if (readb(pl061->base + GPIODIR) & BIT(offset)) |
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return GPIO_LINE_DIRECTION_OUT; |
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return GPIO_LINE_DIRECTION_IN; |
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} |
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static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) |
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{ |
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struct pl061 *pl061 = gpiochip_get_data(gc); |
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unsigned long flags; |
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unsigned char gpiodir; |
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raw_spin_lock_irqsave(&pl061->lock, flags); |
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gpiodir = readb(pl061->base + GPIODIR); |
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gpiodir &= ~(BIT(offset)); |
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writeb(gpiodir, pl061->base + GPIODIR); |
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raw_spin_unlock_irqrestore(&pl061->lock, flags); |
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return 0; |
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} |
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static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, |
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int value) |
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{ |
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struct pl061 *pl061 = gpiochip_get_data(gc); |
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unsigned long flags; |
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unsigned char gpiodir; |
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raw_spin_lock_irqsave(&pl061->lock, flags); |
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writeb(!!value << offset, pl061->base + (BIT(offset + 2))); |
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gpiodir = readb(pl061->base + GPIODIR); |
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gpiodir |= BIT(offset); |
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writeb(gpiodir, pl061->base + GPIODIR); |
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/* |
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* gpio value is set again, because pl061 doesn't allow to set value of |
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* a gpio pin before configuring it in OUT mode. |
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*/ |
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writeb(!!value << offset, pl061->base + (BIT(offset + 2))); |
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raw_spin_unlock_irqrestore(&pl061->lock, flags); |
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return 0; |
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} |
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static int pl061_get_value(struct gpio_chip *gc, unsigned offset) |
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{ |
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struct pl061 *pl061 = gpiochip_get_data(gc); |
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return !!readb(pl061->base + (BIT(offset + 2))); |
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} |
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static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value) |
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{ |
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struct pl061 *pl061 = gpiochip_get_data(gc); |
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writeb(!!value << offset, pl061->base + (BIT(offset + 2))); |
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} |
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static int pl061_irq_type(struct irq_data *d, unsigned trigger) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct pl061 *pl061 = gpiochip_get_data(gc); |
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int offset = irqd_to_hwirq(d); |
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unsigned long flags; |
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u8 gpiois, gpioibe, gpioiev; |
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u8 bit = BIT(offset); |
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if (offset < 0 || offset >= PL061_GPIO_NR) |
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return -EINVAL; |
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if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) && |
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(trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) |
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{ |
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dev_err(gc->parent, |
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"trying to configure line %d for both level and edge " |
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"detection, choose one!\n", |
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offset); |
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return -EINVAL; |
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} |
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raw_spin_lock_irqsave(&pl061->lock, flags); |
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gpioiev = readb(pl061->base + GPIOIEV); |
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gpiois = readb(pl061->base + GPIOIS); |
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gpioibe = readb(pl061->base + GPIOIBE); |
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if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
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bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH; |
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/* Disable edge detection */ |
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gpioibe &= ~bit; |
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/* Enable level detection */ |
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gpiois |= bit; |
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/* Select polarity */ |
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if (polarity) |
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gpioiev |= bit; |
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else |
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gpioiev &= ~bit; |
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irq_set_handler_locked(d, handle_level_irq); |
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dev_dbg(gc->parent, "line %d: IRQ on %s level\n", |
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offset, |
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polarity ? "HIGH" : "LOW"); |
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} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { |
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/* Disable level detection */ |
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gpiois &= ~bit; |
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/* Select both edges, setting this makes GPIOEV be ignored */ |
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gpioibe |= bit; |
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irq_set_handler_locked(d, handle_edge_irq); |
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dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset); |
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} else if ((trigger & IRQ_TYPE_EDGE_RISING) || |
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(trigger & IRQ_TYPE_EDGE_FALLING)) { |
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bool rising = trigger & IRQ_TYPE_EDGE_RISING; |
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/* Disable level detection */ |
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gpiois &= ~bit; |
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/* Clear detection on both edges */ |
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gpioibe &= ~bit; |
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/* Select edge */ |
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if (rising) |
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gpioiev |= bit; |
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else |
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gpioiev &= ~bit; |
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irq_set_handler_locked(d, handle_edge_irq); |
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dev_dbg(gc->parent, "line %d: IRQ on %s edge\n", |
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offset, |
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rising ? "RISING" : "FALLING"); |
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} else { |
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/* No trigger: disable everything */ |
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gpiois &= ~bit; |
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gpioibe &= ~bit; |
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gpioiev &= ~bit; |
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irq_set_handler_locked(d, handle_bad_irq); |
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dev_warn(gc->parent, "no trigger selected for line %d\n", |
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offset); |
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} |
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writeb(gpiois, pl061->base + GPIOIS); |
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writeb(gpioibe, pl061->base + GPIOIBE); |
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writeb(gpioiev, pl061->base + GPIOIEV); |
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raw_spin_unlock_irqrestore(&pl061->lock, flags); |
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return 0; |
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} |
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static void pl061_irq_handler(struct irq_desc *desc) |
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{ |
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unsigned long pending; |
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int offset; |
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struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
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struct pl061 *pl061 = gpiochip_get_data(gc); |
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struct irq_chip *irqchip = irq_desc_get_chip(desc); |
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chained_irq_enter(irqchip, desc); |
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pending = readb(pl061->base + GPIOMIS); |
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if (pending) { |
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for_each_set_bit(offset, &pending, PL061_GPIO_NR) |
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generic_handle_irq(irq_find_mapping(gc->irq.domain, |
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offset)); |
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} |
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chained_irq_exit(irqchip, desc); |
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} |
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static void pl061_irq_mask(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct pl061 *pl061 = gpiochip_get_data(gc); |
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u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); |
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u8 gpioie; |
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raw_spin_lock(&pl061->lock); |
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gpioie = readb(pl061->base + GPIOIE) & ~mask; |
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writeb(gpioie, pl061->base + GPIOIE); |
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raw_spin_unlock(&pl061->lock); |
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} |
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static void pl061_irq_unmask(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct pl061 *pl061 = gpiochip_get_data(gc); |
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u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); |
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u8 gpioie; |
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raw_spin_lock(&pl061->lock); |
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gpioie = readb(pl061->base + GPIOIE) | mask; |
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writeb(gpioie, pl061->base + GPIOIE); |
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raw_spin_unlock(&pl061->lock); |
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} |
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/** |
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* pl061_irq_ack() - ACK an edge IRQ |
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* @d: IRQ data for this IRQ |
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* |
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* This gets called from the edge IRQ handler to ACK the edge IRQ |
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* in the GPIOIC (interrupt-clear) register. For level IRQs this is |
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* not needed: these go away when the level signal goes away. |
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*/ |
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static void pl061_irq_ack(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct pl061 *pl061 = gpiochip_get_data(gc); |
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u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); |
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raw_spin_lock(&pl061->lock); |
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writeb(mask, pl061->base + GPIOIC); |
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raw_spin_unlock(&pl061->lock); |
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} |
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static int pl061_irq_set_wake(struct irq_data *d, unsigned int state) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct pl061 *pl061 = gpiochip_get_data(gc); |
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return irq_set_irq_wake(pl061->parent_irq, state); |
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} |
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static int pl061_probe(struct amba_device *adev, const struct amba_id *id) |
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{ |
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struct device *dev = &adev->dev; |
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struct pl061 *pl061; |
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struct gpio_irq_chip *girq; |
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int ret, irq; |
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pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); |
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if (pl061 == NULL) |
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return -ENOMEM; |
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pl061->base = devm_ioremap_resource(dev, &adev->res); |
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if (IS_ERR(pl061->base)) |
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return PTR_ERR(pl061->base); |
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raw_spin_lock_init(&pl061->lock); |
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pl061->gc.request = gpiochip_generic_request; |
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pl061->gc.free = gpiochip_generic_free; |
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pl061->gc.base = -1; |
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pl061->gc.get_direction = pl061_get_direction; |
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pl061->gc.direction_input = pl061_direction_input; |
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pl061->gc.direction_output = pl061_direction_output; |
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pl061->gc.get = pl061_get_value; |
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pl061->gc.set = pl061_set_value; |
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pl061->gc.ngpio = PL061_GPIO_NR; |
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pl061->gc.label = dev_name(dev); |
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pl061->gc.parent = dev; |
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pl061->gc.owner = THIS_MODULE; |
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/* |
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* irq_chip support |
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*/ |
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pl061->irq_chip.name = dev_name(dev); |
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pl061->irq_chip.irq_ack = pl061_irq_ack; |
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pl061->irq_chip.irq_mask = pl061_irq_mask; |
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pl061->irq_chip.irq_unmask = pl061_irq_unmask; |
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pl061->irq_chip.irq_set_type = pl061_irq_type; |
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pl061->irq_chip.irq_set_wake = pl061_irq_set_wake; |
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writeb(0, pl061->base + GPIOIE); /* disable irqs */ |
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irq = adev->irq[0]; |
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if (!irq) |
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dev_warn(&adev->dev, "IRQ support disabled\n"); |
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pl061->parent_irq = irq; |
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girq = &pl061->gc.irq; |
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girq->chip = &pl061->irq_chip; |
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girq->parent_handler = pl061_irq_handler; |
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girq->num_parents = 1; |
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girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), |
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GFP_KERNEL); |
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if (!girq->parents) |
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return -ENOMEM; |
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girq->parents[0] = irq; |
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girq->default_type = IRQ_TYPE_NONE; |
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girq->handler = handle_bad_irq; |
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ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061); |
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if (ret) |
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return ret; |
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amba_set_drvdata(adev, pl061); |
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dev_info(dev, "PL061 GPIO chip registered\n"); |
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return 0; |
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} |
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#ifdef CONFIG_PM |
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static int pl061_suspend(struct device *dev) |
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{ |
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struct pl061 *pl061 = dev_get_drvdata(dev); |
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int offset; |
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pl061->csave_regs.gpio_data = 0; |
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pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR); |
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pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS); |
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pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE); |
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pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV); |
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pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE); |
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for (offset = 0; offset < PL061_GPIO_NR; offset++) { |
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if (pl061->csave_regs.gpio_dir & (BIT(offset))) |
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pl061->csave_regs.gpio_data |= |
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pl061_get_value(&pl061->gc, offset) << offset; |
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} |
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return 0; |
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} |
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static int pl061_resume(struct device *dev) |
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{ |
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struct pl061 *pl061 = dev_get_drvdata(dev); |
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int offset; |
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for (offset = 0; offset < PL061_GPIO_NR; offset++) { |
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if (pl061->csave_regs.gpio_dir & (BIT(offset))) |
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pl061_direction_output(&pl061->gc, offset, |
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pl061->csave_regs.gpio_data & |
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(BIT(offset))); |
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else |
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pl061_direction_input(&pl061->gc, offset); |
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} |
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writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); |
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writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); |
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writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); |
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writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); |
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return 0; |
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} |
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static const struct dev_pm_ops pl061_dev_pm_ops = { |
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.suspend = pl061_suspend, |
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.resume = pl061_resume, |
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.freeze = pl061_suspend, |
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.restore = pl061_resume, |
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}; |
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#endif |
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static const struct amba_id pl061_ids[] = { |
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{ |
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.id = 0x00041061, |
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.mask = 0x000fffff, |
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}, |
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{ 0, 0 }, |
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}; |
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MODULE_DEVICE_TABLE(amba, pl061_ids); |
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static struct amba_driver pl061_gpio_driver = { |
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.drv = { |
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.name = "pl061_gpio", |
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#ifdef CONFIG_PM |
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.pm = &pl061_dev_pm_ops, |
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#endif |
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}, |
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.id_table = pl061_ids, |
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.probe = pl061_probe, |
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}; |
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module_amba_driver(pl061_gpio_driver); |
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MODULE_LICENSE("GPL v2");
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